DS8207Q 00

®
RT8207Q
Complete DDRII/DDRIII/Low-Power DDRIII/DDRIV Memory
Power Supply Controller
General Description
The RT8207Q provides a complete power supply for DDRII/
DDRIII/Low-Power DDRIII/DDRIV memory systems. It
integrates a synchronous PWM Buck controller with a
1.5A sink/source tracking linear regulator and buffered low
noise reference.
The PWM controller provides the high efficiency, excellent
transient response, and high DC output accuracy needed
for stepping down high voltage batteries to generate low
voltage chipset RAM supplies in notebook computers.
The constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
a relatively constant switching frequency.
The RT8207Q achieves high efficiency at a reduced cost
by eliminating the current sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs. The Buck conversion allows this device
to directly step down high voltage batteries for the highest
possible efficiency.
The RT8207Q provides all of the protection features
including thermal shutdown and is available in the
WQFN-24L 4x4 package.
Features
z
PWM Controller
Resistor Adjustable Current Limit with Low Side
RDS(ON) Sense
` Quick Load Step Response Within 100ns
` 1% VVDDQ Accuracy Over Line and Load
` Fixed 1.8V (DDRII), 1.5V (DDRIII) or Adjustable
0.75V to 3.3V Output Range for 1.35V (Low-Power
DDRIII) and 1.2V (DDRIV)
` 4.5V to 26V Battery Input Range
` Resistor Adjustable Frequency
` Over/Under Voltage Protection
` Internal Current Limit Ramp Soft-Start
` Drives Large Synchronous-Rectifier FETs
` Power Good Indicator
1.5A LDO (VTT), Buffered Reference (VTTREF)
` Capable to Sink and Source 1.5A
` External Input Available to Minimize Power Losses
` Integrated Divider Tracks 1/2 VDDQ for Both VTT
and VTTREF
` Buffered Low Noise 10mA VTTREF Output
` Remote Sensing (VTTSNS)
` ±20mV Accuracy for Both VTTREF and VTT
` Supports High-Z in S3 and Soft-Off in S4/S5
RoHS Compliant and Halogen Free
`
z
The 1.5A sink/source LDO maintains fast transient
response, only requiring 20μF of ceramic output
capacitance. In addition, the LDO supply input is available
externally to significantly reduce the total power losses.
The RT8207Q supports all of the sleep state controls
placing VTT at high-Z in S3 and discharging VDDQ, VTT
and VTTREF (soft-off) in S4/S5.
z
Simplified Application Circuit
VVDDP
C1
R2
VTT
C3
C4
VVDDP for DDRII
GND for DDRIII
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
RT8207Q
VDDP
TON
VDD
BOOT
CS
VTT
UGATE
VTTSNS
PHASE
VTTREF
LGATE
VLDOIN
FB
VDDQ
RTON
VIN
R4
R3
C7
C6
Q1 L1
Q2
VVDDQ
C5
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1
RT8207Q
Applications
z
Ordering Information
RT8207Q
Note :
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
0S=YM
DNN
YMDNN : Date Code
Pin Configurations
(TOP VIEW)
Package Type
QW : WQFN-24L 4x4 (W-Type)
(Exposed Pad-Option 1)
Lead Plating System
G : Green (Halogen Free and Pb Free)
`
0S= : Product Code
Suitable for use in SnPb or Pb-free soldering processes.
VTT
VLDOIN
BOOT
UGATE
PHASE
LGATE
z
DDRI/II/III/Low-Power DDRIII/DDRIV Memory Power
Supplies
Notebook Computers
SSTL18, SSTL15 and HSTL Bus Termination
24 23 22 21 20 19
VTTGND
VTTSNS
GND
MODE
VTTREF
NC
1
18
2
17
3
16
GND
4
15
25
5
14
13
6
7
8
PGND
NC
CS
VDDP
VDD
PGOOD
9 10 11 12
NC
VDDQ
FB
S3
S5
TON
z
Marking Information
WQFN-24L 4x4
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is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VTTGND
Power Ground Output for VTT LDO.
2
VTTSNS
Voltage Sense Input for VTT LDO. Connect to the terminal of the VTT LDO
output capacitor.
3,
GND
25 (Exposed Pad)
Analog Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum thermal dissipation.
4
MODE
Output Discharge Mode Setting. Connect to VDDQ for tracking discharge.
Connect to GND for non-tracking discharge. Connect to VDD for no discharge.
5
VTTREF
Buffered Reference Output.
NC
No Internal Connection.
VDDQ
Reference Input for VTT and VTTREF. Discharge current sinking terminal for
VDDQ non-tracking discharge. Output voltage feedback input for VDDQ output if
the FB pin is connected to VDD or GND.
9
FB
VDDQ Output Setting. Connect to GND for DDR3 (VVDDQ = 1.5V) power supply.
Connect to VDD for DDR2 (V VDDQ = 1.8V) power supply. Or connect to a
resistive voltage divider from VDDQ to GND to adjust the output of PWM from
0.75V to 3.3V.
10
S3
S3 Signal Input.
11
S5
S5 Signal Input.
12
TON
On-Time Setting Set the UGATE On-Time Through a Pull-up Resistor
Connecting to V IN.
13
PGOOD
Power Good Open Drain Output. In High state when VDDQ output voltage is
within the target range.
14
VDD
Supply Voltage Input for Analog Supply.
15
VDDP
Supply Voltage Input for LGATE Gate Driver.
16
CS
Current Limit Threshold Setting Input. Connect to VDD through the voltage
setting resistor.
18
PGND
Power Ground for Low Side MOSFET.
19
LGATE
Low Side Gate Driver Output for VDDQ.
20
PHASE
Switch Node. External inductor connection for VDDQ and behave as the current
sense comparator input for low side MOSFET RDS(ON) sensing.
21
UGATE
High Side Gate Driver Output for VDDQ.
22
BOOT
Boost Flying Capacitor Connection for VDDQ.
23
VLDOIN
Power Input for VTT LDO.
24
VTT
Power Output for VTT LDO.
6, 7, 17
8
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8207Q
Function Block Diagram
TRIG
On-time
Compute
1-SHOT
VDDQ
TON
BOOT
+
0.75V VREF
+
115%VREF
FB
OV
+
70% VREF
UV
-
R
Comp
S
UGATE
DRV
PHASE
Min. TOFF
Q
TRIG
Latch
S1
Q
VDDP
1-SHOT
Latch
S1
Q
LGATE
DRV
PGND
Diode
Emulation
-
90% VREF
SS Timer
VDD
PWM
Q
+
+
+
-
Thermal
Shutdown
S5
+
GM
-
CS
10µA
SS Int.
PGOOD
Buck Controller
VDDQ
S5
S3
MODE
Discharge
Mode
Select
Thermal
Shutdown
VTTREF
VLDOIN
+
+
-
+
-
VTT
+
-
VTTSNS
GND
-
110% VVTTREF
+
90% VVTTREF
-
VTTGND
+
VTT LDO
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Operation
The RT8207Q provides a complete power supply for DDRII/
DDRIII/Low-Power DDRIII/DDRV memory systems. It
integrates a synchronous PWM buck controller based on
constant on-time architecture, a buffered low noise
reference (VTTREF), and a sink/source tracking linear
regulator (VTT).
Protection
Enable
Current Limit Setting
The RT8207Q is enabled by S5 logic high. S3 is
responsible for VTT LDO enable when S5 is high. RT8207Q
enter shutdown mode when S5 is low.
The RT8207Q provides adjustable inductor valley current
limit setting by resistor between CS and VDD. Users
choose CS resistor depending on low side MOSFET turnon resistor and the maximum inductor valley current.
Soft-Start
The RT8207Q provides internal current limit ramp type
soft-start each time the RT8207Q is enabled. The inductor
current limit will increase gradually up to setting point.
This internal ramp also controls the PGOOD blanking time.
Constant On-time Calculation
On-time calculation is based on TON resistor, VIN and
VDDQ. Under no protection is triggered and none OC limit
condition, the FB comparator triggers one-shot on-time
calculation when FB < VREF.
PGOOD Indicator
If FB is between 90% and 115% of VREF, the PGOOD
open drain NMOS will off after PGOOD blanking time.
PGOOD will be pulled high by external power source
through the PGOOD resistor.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
The RT8207Q provide OV/UV comparator to monitor the
FB voltage. RT8207Q has internal temperature sense
circuit to provide OTP. When OV/UV/OTP occurs and
latches, users can reset the protection by re-enable S5
or VDD power on reset.
VTTREF/VTT LDO
VTTREF is enabled by S5 logic high and follows the half
VDDQ voltage. The VTT LDO is enabled by S3 logic high
when the RT8207Q is enabled. VTTLDO provides different
source and sink capability depending on VDDQ/VLDOIN
voltage. After VTT voltage is first inside the 10% range of
VTTREF voltage, VTT LDO current limit folds back when
VTT is outside 15% range of VTTREF.
Discharge Mode Selection
The RT8207Q provides three kinds of discharge mode
selection by MODE setting. Each time the S5 goes from
high to low, the RT8207Q begins discharge for three power
rails of VDDQ/VTTREF/VTT before entering the shutdown
mode.
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RT8207Q
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, TON to GND -----------------------------------------------------------------------------------BOOT to PHASE ---------------------------------------------------------------------------------------------------------z VDD, VDDP, CS, MODE, S3, S5, VTTSNS, VDDQ, VTTREF, VTT, VLDOIN,
FB, PGOOD to GND -----------------------------------------------------------------------------------------------------z PGND, VTTGND to GND ------------------------------------------------------------------------------------------------z PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z LGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z UGATE to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z Other Pins ------------------------------------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C
WQFN-24L 4x4 -----------------------------------------------------------------------------------------------------------z Package Thermal Resistance (Note 2)
WQFN-24L 4x4, θJA ------------------------------------------------------------------------------------------------------WQFN-24L 4x4, θJC -----------------------------------------------------------------------------------------------------z Junction Temperature ----------------------------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------z Storage Temperature Range -------------------------------------------------------------------------------------------z ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------z
z
Recommended Operating Conditions
z
z
z
z
−0.3V to 32V
−0.3V to 6V
−0.3V to 6V
−0.3V to 0.3V
−1V to 32V
−8V to 38V
−0.3V to 6V
−2.5V to 7.5V
−0.3V to 6V
−5V to 7.5V
−0.3V to 6.5V
3.57W
28°C/W
7°C/W
150°C
260°C
−65°C to 150°C
2kV
(Note 4)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 4.5V to 26V
Control Voltage, VDD, VVDDP ----------------------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 15V, VDD = VVDDP = 5V, RTON = 1MΩ, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
PWM Controller
Quiescent Supply Current
(VDD + VDDP)
FB forced above the regulation point,
VS5 = 5V, VS3 = 0V
--
470
1000
μA
TON Operating Current
R TON = 1MΩ
--
15
--
μA
IVLDOIN BIAS Current
VS5 = VS3 = 5V, VTT = No Load
--
1
--
μA
IVLDOIN Standby Current
VS5 = 5V, VS3 = 0V, VTT = No Load
--
0.1
10
μA
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Parameter
Min
Typ
Max
V DD + VVDDP
--
1
10
TON
--
0.1
5
S5/S3 = 0V
−1
0.1
1
IVLDOIN
--
0.1
1
0.742
0.75
0.758
FB = GND
--
1.5
--
FB = V DD
--
1.8
--
FB = 0.75V
−1
0.1
1
μA
0.75
--
3.3
V
267
334
401
ns
250
400
550
ns
--
100
--
kΩ
V S5 = GND
--
15
--
Ω
CS Sink Current
V CS > 4.5V, After UV Blank Time
9
10
11
μA
Current Comparator Offset
GND − PHASE, RCS = 5kΩ
−15
--
15
mV
Zero Crossing Threshold
GND − PHASE
−5
--
10
mV
GND − PHASE, RCS = 5kΩ
35
50
65
GND − PHASE, RCS = 20kΩ
170
200
230
60
70
80
%
110
115
120
%
Shutdown Current
(V S5 = VS3 = 0V)
FB Reference Voltage
Symbol
ISHDN
V REF
Fixed VDDQ Output Voltage
FB Input Bias Current
Test Conditions
V DD = 4.5V to 5.5V
VDDQ Voltage Range
On-Time
V VDDQ = 1.25V
Minimum Off-Time
VDDQ Input Resistance
VDDQ Shutdown Discharge
Resistance
Unit
μA
V
V
Current Sensing
Fault Protection
Current Limit (Positive)
Under Voltage Protection
Threshold
V UVP
Over Voltage Protection
Threshold
V OVP
With respect to error comparator threshold
mV
Over Voltage Fault Delay
FB forced above over voltage threshold
--
20
--
μs
VDD POR Threshold
Rising edge, hysteresis = 120mV, PWM
disabled below this level
3.9
4.2
4.5
V
Under Voltage Blank Time
--
5
--
ms
Thermal Shutdown
T SD
From S5 signal going high
--
165
--
°C
Thermal Shutdown
Hysteresis
ΔT SD
--
10
--
°C
Driver On-Resistance
UGATE Driver Source
RUGATEsr
BOOT − PHASE Forced to 5V
--
2.5
5
Ω
UGATE Driver Sink
RUGATEsk BOOT − PHASE Forced to 5V
--
1.5
3
Ω
LGATE Driver Source
RLGATEsr
DL, High State
--
2.5
5
Ω
LGATE Driver Sink
RLGATEsk
DL, Low State
--
0.8
1.6
Ω
LGATE Rising (PHASE = 1.5V)
--
40
--
UGATE Rising
--
40
--
VDDP to BOOT, 10mA
--
--
80
Dead Time
Internal Boost Charging
Switch On Resistance
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
ns
Ω
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7
RT8207Q
Parameter
Symbol
Test Conditions
Min
Typ
Max Unit
-2
---
0.8
--
V
V
−1
0
1
μA
−13
−10
−7
%
--
3
--
%
--
2.5
--
μs
Logic I/O
Logic Input Low Voltage
Logic Input High Voltage
S3, S5 Low
S3, S5 High
Logic Input Current
S3, S5 = VDD/GND
PGOOD (upper side threshold decide by Over Voltage threshold)
Measured at FB, with respect to reference,
no load
Trip Threshold (Falling)
Trip Threshold (Hysteresis)
Falling edge, FB forced below PGOOD trip
threshold
ISINK = 1mA
Fault Propagation Delay
Output Low Voltage
Leakage Current
VTT LDO
VTT Output Tolerance
VTT Source Current Limit
VTT Sink Current Limit
ILEAK
V VTTTOL
IVTTOCLSRC
IVTTOCLSNK
VTT Leakage Current
IVTTLK
VTTSNS Leakage Current
VTT Discharge Current
IVTTSNSLK
IDSCHRG
VTTREF Output Voltage
V VTTREF
VDDQ/2, VTTREF Output
Voltage Tolerance
V VTTREFTOL
VTTREF Source Current
Limit
IVTTREFOCL
--
--
0.4
V
--
--
1
μA
V VDDQ = V LDOIN = 1.2V/1.35/1.5V/1.8V,
⎪ IVTT ⎪= 0A
−20
--
20
V VDDQ = V LDOIN = 1.2V/1.35/1.5V/1.8V,
⎪ IVTT ⎪< 1A
−30
--
30
V VDDQ = V LDOIN = 1.2V/1.35, ⎪ IVTT ⎪< 1.2A
V VDDQ = V LDOIN = 1.5V/1.8V, ⎪ IVTT ⎪< 1.5A
−40
−40
---
40
40
1.6
2.6
3.6
--
1.3
--
1.6
2.6
3.6
--
1.3
--
−10
--
10
μA
−1
10
-30
1
--
μA
mA
--
0.9/
0.75
--
V
V LDOIN = VVDDQ = 1.5V, ⎪ I VTTREF ⎪ <10mA
−15
--
15
V LDOIN = V VDDQ = 1.8V, ⎪ IVTTREF ⎪ <10mA
−18
--
18
V VTTREF = 0V
10
40
80
High state, forced to 5V
⎛V
⎞
VT T = ⎜ VDDQ ⎟ × 0.95 PGOOD = High
2
⎝
⎠
V TT = 0V
⎛V
⎞
VT T = ⎜ VDDQ ⎟ × 1.05 , PGOOD = High
⎝ 2
⎠
V TT = V VDDQ
⎛V
⎞
S5 = 5V, S3 = 0V, VTT = ⎜ VDDQ ⎟
2 ⎠
⎝
ISINK = 1mA
V VDDQ = 0V, VTT = 0.5V, S5 = S3 =0V
⎛V
⎞
VVTTREF = ⎜ VDDQ ⎟
⎝ 2
⎠
mV
A
A
mV
mA
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Typical Application Circuit
VIN
4.5V to 26V
RTON
620k
12
VVDDP
5V
15
R1
5.1
C1
1µF
VDDP
14 VDD
C2
1µF
R2
100k
RT8207Q
BOOT 22
TON
PHASE
R3
5.6k
16 CS
13 PGOOD
PGOOD
VDDQ Control
4
Discharge Mode
C4
0.1µF
R6
0
Q1
BSC09
4N03S
20
LGATE 19
VVDDQ
1.2V
L1
1µH
C7
220µF
R7*
Q2
BSC032N03S
R8
6k
C5*
C9
0.1µF
R9
10k
VLDOIN 23
MODE
C6*
FB 9
* : Optional
10 S3
11 S5
VTT/VTTREF Control
UGATE 21
C9
10µF x 3
R5
0
VDDQ 8
24
VTT
GND
2
VTTSNS
18 PGND
1
VTTGND VTTREF 5
3, 25 (Exposed Pad)
VTT
0.6V
C8
10µF x 2
C3
33nF
Figure 1. Adjustable Voltage Regulator
VIN
4.5V to 26V
RTON
620k
12
VVDDP
5V
15
R1
5.1
C1
1µF
C2
1µF
R2
100k
PGOOD
VTT/VTTREF Control
VDDQ Control
Discharge Mode
RT8207Q
TON
VDDP
14 VDD
R3
5.6k
16 CS
13 PGOOD
10 S3
11
S5
4
MODE
3, 25 (Exposed Pad)
GND
18 PGND
1
VTTGND
BOOT 22
UGATE 21
PHASE
R6
0
C4
0.1µF
20
LGATE 19
VDDQ
C8
10µF x 2
R5
0
Q1
BSC09
4N03S
VVDDQ
1.8V/1.5V
L1
1µH
C6
220µF
R7*
Q2
BSC032N03S
C5*
8
VLDOIN 23
24
VTT
2
VTTSNS
VTTREF 5
* : Optional
C7
10µF x 2
VTT
0.9V/0.75V
C3
33nF
FB 9
VVDDP for DDRII
GND for DDRIII
Figure 2. Fixed Voltage Regulator
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8207Q
Typical Operating Characteristics
VDDQ Efficiency vs. Output Current
VDDQ Efficiency vs. Output Current
100
DDRII
90
90
80
80
Efficiency (%) 1
Efficiency (%) 1
100
70
60
50
40
30
DDRII
70
60
50
40
30
20
20
10
10
VIN = 8V, VDDQ = 1.8V, S3 = GND, S5 = 5V
0
0.001
0.01
0.1
1
VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V
0
0.001
10
0.01
Output Current (A)
VDDQ Efficiency vs. Output Current
DDRII
90
90
80
80
70
60
50
40
30
20
DDRIII
70
60
50
40
30
10
VIN = 20V, VDDQ = 1.8V, S3 = GND, S5 = 5V
0
0.001
0.01
0.1
1
VIN = 8V, VDDQ = 1.5V, S3 = GND, S5 = 5V
0
0.001
10
0.01
100
DDRIII
90
80
80
70
70
Efficiency (%) 1
90
60
50
40
30
VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
0.01
0.1
1
Output Current (A)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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10
10
DDRIII
60
50
40
30
20
20
0
0.001
1
VDDQ Efficiency vs. Output Current
VDDQ Efficiency vs. Output Current
10
0.1
Output Current (A)
Output Current (A)
Efficiency (%) 1
10
20
10
100
1
VDDQ Efficiency vs. Output Current
100
Efficiency (%) 1
Efficiency (%) 1
100
0.1
Output Current (A)
10
10
0
0.001
VIN = 20V, VDDQ = 1.5V, S3 = GND, S5 = 5V
0.01
0.1
1
10
Output Current (A)
is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Switching Frequency vs. Output Current
Switching Frequency vs. Output Current
500
DDRII, VIN = 8V, VDDQ = 1.8V, S3 = GND, S5 = 5V
450
Switching Frequency (kHz) 1
Switching Frequency (kHz) 1
500
400
350
300
250
200
150
100
50
0
0.001
0.01
0.1
1
450
DDRII, VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V
400
350
300
250
200
150
100
50
0
0.001
10
0.01
Switching Frequency vs. Output Current
Switching Frequency (kHz) 1
Switching Frequency (kHz) 1
400
350
300
250
200
150
100
50
0
0.001
0.01
0.1
1
450
DDRIII, VIN = 8V, VVDDQ = 1.5V, S3 = GND, S5 = 5V
400
350
300
250
200
150
100
50
0
0.001
10
0.01
Output Current (A)
Switching Frequency (kHz) 1
Switching Frequency (kHz) 1
DDRIII, VIN = 12V, VVDDQ = 1.5V, S3 = GND, S5 = 5V
400
350
300
250
200
150
100
50
0.01
0.1
1
Output Current (A)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
1
10
Switching Frequency vs. Output Current
500
450
0
0.001
0.1
Output Current (A)
Switching Frequency vs. Output Current
500
10
Switching Frequency vs. Output Current
500
DDRII, VIN = 20V, VDDQ = 1.8V, S3 = GND, S5 = 5V
450
1
Output Current (A)
Output Current (A)
500
0.1
10
DDRIII, VIN = 20V, VVDDQ = 1.5V, S3 = GND, S5 = 5V
450
400
350
300
250
200
150
100
50
0
0.001
0.01
0.1
1
10
Output Current (A)
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11
RT8207Q
VDDQ Output Voltage vs. Output Current
VDDQ Output Voltage vs. Output Current
1.820
1.515
DDRII
1.815
Output Voltage (V) 1
1.810
Output Voltage (V) 1
DDRIII
1.510
1.805
1.800
1.795
1.790
1.505
1.500
1.495
1.490
1.485
1.785
VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V
1.780
0.001
0.01
0.1
1
1.480
0.001
10
0.01
DDRII
DDRIII
0.7475
Output Voltage (V) 1
Output Voltage (V) 1
0.7480
0.8990
0.8985
0.8980
0.8975
0.7470
0.7465
0.7460
0.7455
VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V
0.8970
VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V
0.7450
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
0.6
0.9
1.2
1.5
-1.5 -1.2 -0.9 -0.6 -0.3
Output Current (A)
0
0.3
0.6
0.9
1.2
1.5
Output Current (A)
VTTREF Output Voltage vs. Output Current
VTTREF Output Voltage vs. Output Current
0.760
DDRII
DDRIII
0.758
Output Voltage (V) 1
0.910
Output Voltage (V) 1
10
VTT Output Voltage vs. Output Current
VTT Output Voltage vs. Output Current
0.9000
0.912
1
Output Current (A)
Output Current (A)
0.8995
0.1
0.908
0.906
0.904
0.902
0.900
0.756
0.754
0.752
0.750
0.748
VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V
0.898
VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V
0.746
-10
-8
-6
-4
-2
0
2
4
6
Output Current (mA)
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12
8
10
-10
-8
-6
-4
-2
0
2
4
6
8
10
Output Current (mA)
is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Standby Current vs. Input Voltage
Shutdown Current vs. Input Voltage
3.00
No Load, S3 = GND, S5 = 5V
580
Shutdown Current (µA) 1
Standby Current (µA)1
600
560
540
520
500
No Load, S3 = S5 = GND
2.50
2.00
1.50
1.00
0.50
0.00
480
5
8
11
14
17
20
23
5
26
8
11
1.502
DDRII
1.79675
20
23
26
DDRIII
1.498
1.79350
VDDQ Voltage (V) 1
VDDQ Voltage (V) 1
17
VDDQ Voltage vs. Temperature
VDDQ Voltage vs. Temperature
1.80000
14
Input Voltage (V)
Input Voltage (V)
1.79025
1.78700
1.78375
1.78050
1.494
1.490
1.486
1.482
1.478
1.77725
VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V
1.77400
-50
-25
0
25
50
75
100
125
VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
1.474
-50
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
VDDQ and VTT Start Up
VDDQ Start Up
100
125
No Load
VDDQ
(1V/Div)
VDDQ
(1V/Div)
VTT
(500mV/Div)
PGOOD
(5V/Div)
IL
(10A/Div)
UGATE
(20V/Div)
S5
(5V/Div)
LGATE
(5V/Div)
VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V
Time (1ms/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
VIN = 12V, VDDQ = 1.5V
S3 = GND, S5 = 5V, ILOAD = 10A
Time (400μs/Div)
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13
RT8207Q
Shutdown
Shutdown
No Load
Tracking Mode
VDDQ
(1V/Div)
VTT
(1V/Div)
VDDQ
(1V/Div)
VTT
(1V/Div)
VTTREF
(500mV/Div)
VTTREF
(500mV/Div)
S5
(5V/Div)
VIN = 12V
VDDQ = 1.5V, S3 = S5 = 5V, MODE = VDDQ
S5
(5V/Div)
VIN = 12V
VDDQ = 1.5V, S3 = S5 = 5V, MODE = GND
Time (400μs/Div)
Time (400μs/Div)
VDDQ Load Transient Response
VDDQ Load Transient Response
DDRII, VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V,
ILOAD = 0.1A to 10A
DDRIII, VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
ILOAD = 0.1A to 10A
VDDQ
(50mV/Div)
VDDQ
(50mV/Div)
IL
(10A/Div)
IL
(10A/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
UGATE
(20V/Div)
VTT
(20mV/Div)
VTTREF
(20mV/Div)
No Load
Non-Tracking Mode
LGATE
(10V/Div)
Time (20μs/Div)
Time (20μs/Div)
VTT Load Transient Response
VTT Load Transient Response
DDRII, VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V,
IVTT = −1.5A to 1.5A
VTT
(20mV/Div)
VTTREF
(20mV/Div)
IVTT
(2A/Div)
IVTT
(2A/Div)
VTT - VTTREF
(20mV/Div)
VTT - VTTREF
(20mV/Div)
Time (200μs/Div)
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DDRIII, VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V,
IVTT = −1.5A to 1.5A
Time (200μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
UVP
OVP
VDDQ
(2V/Div)
No Load
VDDQ
(1V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
Time (40μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
LGATE
(5V/Div)
VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
Time (40μs/Div)
is a registered trademark of Richtek Technology Corporation.
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15
RT8207Q
Application Information
The RT8207Q PWM controller provides the high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage chipset RAM supplies in notebook
computers. Richtek's Mach ResponseTM technology is
specifically designed for providing 100ns “instant-on”
response to load steps while maintaining a relatively
constant operating frequency and inductor operating point
over a wide range of input voltages. The topology solves
the poor load transient response timing problems of fixedfrequency current mode PWMs, and avoids the problems
caused by widely varying switching frequencies in
conventional constant-on-time and constant-off-time PWM
schemes. The DRV TM mode PWM modulator is
specifically designed to have better noise immunity for
such a single output application.
The 1.5A sink/source LDO maintains fast transient
response, only requiring 20μF of ceramic output
capacitance. In addition, the LDO supply input is available
externally to significantly reduce the total power losses.
The RT8207Q supports all of the sleep state controls,
placing VTT at high-Z in S3 and discharging VDDQ, VTT
and VTTREF (soft-off) in S4/S5.
PWM Operation
The Mach ResponseTM DRVTM mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current-sense resistor, so the output
ripple voltage provides the PWM ramp signal. Referring to
the function diagrams of the RT8207Q, the synchronous
high side MOSFET is turned on at the beginning of each
cycle. After the internal one-shot timer expires, the
MOSFET will be turned off. The pulse width of this oneshot is determined by the converter's input and output
voltages to keep the frequency fairly constant over the
entire input voltage range. Another one-shot sets a
minimum off-time (400ns typ.).
On-Time Control
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
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16
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VVDDQ, thereby making the on-time of the
high side switch directly proportional to the output voltage
and inversely proportional to the input voltage. This
implementation results in a nearly constant switching
frequency without the need of a clock generator, as shown
below :
t ON = 3.85p x RTON x VVDDQ / (VIN − 0.5)
And then the switching frequency is :
f = VVDDQ / (VIN x t ON )
where RTON is the resistor connected from VIN to the TON
pin.
Diode-Emulation Mode
In diode-emulation mode, the RT8207Q automatically
reduces switching frequency at light load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly without increasing VDDQ ripples or load
regulation. As the output current decreases from heavy
load condition, the inductor current will also be reduced
and eventually come to the point where its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. To
emulate the behavior of diodes, the low side MOSFET
allows only partial negative current to flow when the
inductor freewheeling current reaches negative. As the load
current is further decreased, it takes longer and longer
time to discharge the output capacitor to the level that
requires the next “ON” cycle. The on-time is kept the
same as that in the heavy load condition. In contrast, when
the output current increases from light load to heavy load,
the switching frequency increases to the preset value as
the inductor current reaches the continuous condition. The
transition load point to the light load operation is shown in
figure below and can be calculated as follows :
ILOAD(SKIP) ≈
VIN − VVDDQ
x tON
2L
where tON is the on-time.
is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
IL
Slope = (VIN - VVDDQ) / L
IPEAK
ILOAD = IPEAK / 2
0
tON
t
Figure 3. Boundary Condition of CCM/DCM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode-emulation
operation, but this is a normal operating condition that
results in high light load efficiency. Trade offs in DEM
noise vs. light load efficiency is made by varying the
inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values result
in higher full load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
The disadvantages for using higher inductor values include
larger physical size and degraded load transient response
(especially at low input voltage levels).
Current Limit Setting for VDDQ (CS)
The RT8207Q provides cycle-by-cycle current limiting
control. The current limit circuit employs a unique “valley”
current sensing algorithm. If the magnitude of the current
sense signal at PHASE is above the current limit
threshold, the PWM is not allowed to initiate a new cycle
(Figure 4). The actual peak current is greater than the
current limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current limit
characteristic and maximum load capability are a function
of the sense resistance, inductor value, battery and output
voltage.
IL
IPEAK
ILOAD
ILIM
The RT8207Q uses the on resistance of the synchronous
rectifier as the current sense element and supports
temperature compensated MOSFET RDS(ON) sensing. The
setting resistor, RILIM, between the CS pin and VDD sets
the current limit threshold. The CS pin sinks an internal
10μA (typ.) current source at room temperature. This
current has a 4700ppm/°C temperature slope to
compensate the temperature dependency of RDS(ON).
When the voltage drop across the low side MOSFET
equals the voltage across the RILIM setting resistor, the
positive current limit will activate. The high side MOSFET
will not be turned on until the voltage drop across the low
side MOSFET falls below the current limit threshold.
Choose a current limit setting resistor via the following
equation :
RILIM = ILIMIT x RDS(ON) /10μA
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signal seen by PHASE and PGND.
Current Protection for VTT
The LDO has an internally fixed constant over current
limiting of 2.6A while operating at normal condition. After
the first time VTT voltage comes to within 15% of its set
voltage, from then on, when the output voltage goes outside
20% of its set voltage, this over current point is reduced
to 1.3A.
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from the VDDP supply.
The average drive current is proportional to the gate charge
at VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins.
A dead-time to prevent shoot through is internally
generated between high side MOSFET off to low side
MOSFET on, and low side MOSFET off to high side
MOSFET on.
t
0
Figure 4. “Valley” Current Limit
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
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17
RT8207Q
The low side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). The internal pull down transistor
that drives LGATE low is robust, with a 0.8Ω typical onresistance. A 5V bias voltage is delivered from the VDDP
supply. The instantaneous drive current is supplied by the
flying capacitor between VDDP and PGND.
For high current applications, some combinations of high
and low side MOSFETs may cause excessive gate drain
coupling, which leads to efficiency killing, EMI producing
shoot through currents. This is often remedied by adding
a resistor in series with BOOT, which increases the turnon rising time of the high side MOSFET without degrading
the turn-off time (Figure 5).
VIN
BOOT
R
Soft-Start
The RT8207Q provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. Soft-start (SS) automatically
begins once the chip is enabled. During soft-start, internal
current limit circuit gradually ramps up the inductor current
from zero. The maximum current-limit value is set
externally as described in previous section. The soft-start
time is determined by the current limit level and output
capacitor value. If the current limit threshold is set for
200mV, the typical soft-start duration is 3ms after S5 is
enabled.
The soft-start function of VTT is achieved by the current
limit and VTTREF voltage through the internal RC delay
ramp up after S3 is high. During VTT startup, the current
limit level is 2.6A. This allows the output to start up
smoothly and safely under enough source/sink ability.
UGATE
PHASE
Figure 5. Increasing the UGATE Rise Time
Power Good Output (PGOOD)
The power good output is an open drain output that requires
a pull-up resistor. When the output voltage is 15% above
or 10% below its set voltage, PGOOD will be pulled low. It
is held low until the output voltage returns to tolerances
once more. During soft-start, PGOOD is actively held low
and only allowed to be pulled high after soft-start is over
and the output reaches 93% of its set voltage. There is a
2.5μs delay built into PGOOD circuitry to prevent false
transition.
POR Protection
The RT8207Q has a VDDP supply power on reset
protection (POR). When the VDDP voltage is higher than
4.2V (typ.), VDDQ, VTT and VTTREF will be activated.
This is a non-latch protection.
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18
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage condition. If the output exceeds 15% of its set
voltage threshold, over voltage protection will be triggered
and the LGATE low side gate driver will be forced high.
This activates the low side MOSFET switch which rapidly
discharges the output capacitor and reduces the input
voltage. There is a 5μs latch delay built into the over voltage
protection circuit. The RT8207Q will be latched if the output
voltage remains above the OV threshold after the latch
delay period and can only be released by VDD power on
reset or S5.
Note that latching the LGATE high will cause the output
voltage to dip slightly negative when energy has been
previously stored in the LC tank circuit. For loads that
cannot tolerate a negative voltage, place a power Schottky
diode across the output to act as a reverse polarity clamp.
If the over voltage condition is caused by a shorted high
side switch, turning the low side MOSFET on 100% will
create an electrical shorted circuit between the battery
and GND, to blow the fuse and disconnect the battery
from the output.
is a registered trademark of Richtek Technology Corporation.
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December 2012
RT8207Q
VIN
Output Under Voltage Protection (UVP)
VVDDQ
The output voltage can be continuously monitored for under
voltage condition. When UVP is enabled, the under voltage
protection is triggered if the output is less than 70% of its
set voltage threshold. Then, both UGATE and LGATE gate
drivers will be forced low while entering soft discharge
mode. During soft-start, the UVP has a blanking time
around 5ms.
Thermal Protection
The RT8207Q monitors the temperature of itself. If the
temperature exceeds the threshold, 165°C (typ.), the PWM
output, VTTREF and VTT will be shut down. The RT8207Q
is latched once thermal shutdown is triggered and can
only be released by VDD power on reset or S5.
Output Voltage Setting (FB)
The RT8207Q can be used as DDR2 (VVDDQ = 1.8V) and
DDR3 (VVDDQ = 1.5V) power supply or as an adjustable
output voltage (0.75V < VVDDQ < 3.3V) by connecting the
FB pin according to Table 1.
Table 1. FB and Output Voltage Setting
FB
VDDQ (V)
VTTREF and
VTT
NOTE
VDD
1.8
VVDDQ / 2
DDR2
GND
1.5
VVDDQ /2
DDR3
FB
Resistors
Adjustable
VVDDQ / 2
0.75V <
VVDDQ < 3.3V
Connect a resistive voltage divider at FB between VDDQ
and GND to adjust the respective output voltage between
0.75V and 3.3V (Figure 6). Choose R2 to be approximately
10kΩ and solve for R1 using the equation as follows :
⎛ ⎛ R1 ⎞ ⎞
VVDDQ = VREF x ⎜ 1 + ⎜
⎟⎟
⎝ ⎝ R2 ⎠ ⎠
where VREF is 0.75V (typ.).
UGATE
PHASE
LGATE
R1
VDDQ
FB
R2
GND
Figure 6. Setting VDDQ with a Resistive Voltage Divider
VTT Linear Regulator and VTTREF
The RT8207Q integrates a high performance low dropout
linear regulator that is capable of sourcing and sinking
currents up to 1.5A. This VTT linear regulator employs
ultimate fast response feedback loop so that small ceramic
capacitors are enough for keeping track of VTTREF within
40mV at all conditions, including fast load transient. To
achieve tight regulation with minimum effect of wiring
resistance, a remote sensing terminal, VTTSNS, should
be connected to the positive node of the VTT output
capacitor(s) as a separate trace from the VTT pin. For
stable operation, total capacitance of the VTT output
terminal can be equal to or greater than 20μF. It is
recommended to attach two 10μF ceramic capacitors in
parallel to minimize the effect of ESR and ESL. If ESR of
the output capacitor is greater than 2mΩ, insert an RC
filter between the output and VTTSNS input to achieve
loop stability. The RC filter time constant should be almost
the same or slightly lower than the time constant made
by the output capacitor and its ESR. The VTTREF block
consists of on-chip 1/2 divider, LPF and buffer. This regulator
also has sink and source capability up to 10mA. Bypass
VTTREF to GND with a 33nF ceramic capacitor for stable
operation.
VDD sources the load of VTTREF to follow half voltage of
VDDQ. If VTTREF capacitor is so large that the VTTREF
is unable to follow half VDDQ voltage at time during soft
start period, VTTREF will sink large current from VDD which
causes large voltage drop at VDDP to VDD resistor and
has the opportunity of UVLO. The following equation
provides the maximum value of VTTREF capacitor
calculation.
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December 2012
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19
RT8207Q
V
0.03
× TSS = C VTTREF × VDDQ
1.1× R VDD + 12
2
TSS
VDDQ and VTT Discharge Control
V
× COUT
= VDDQ
0.03 + t × VIN
RDS ON 2L
CVTTREF =
V
× COUT
0.03
2 ×
× VDDQ
VVDDQ 1.1× R VDD + 12 0.03
V
+ t × IN
RDS ON 2L
Where RVDD is the resistor between VDDP and VDD. RDS
is the turn on resistor of low-side MOSFET. CVTTREF is the
capacitor on the VTTREF pin. TSS is the soft-start time for
VDDQ at the no load condition.
Output Management by S3, S5 Control
In DDR2/DDR3 memory applications, it is important to
always keep VDDQ higher than VTT/VTTREF, even during
start-up and shutdown. The RT8207Q provides this
management by simply connecting both S3 and S5
terminals to the sleep-mode signals such as SLP_S3 and
SLP_S5 in notebook PC system. All VDDQ, VTTREF and
VTT are turned on at S0 state (S3 = S5 = high). In S3
state (S3 = low, S5 = high), VDDQ and VTTREF voltages
are kept on while VTT is turned off and left at high
impedance (high-Z) state. The VTT output is floated and
does not sink or source current in this state. In S4/S5
states (S3 = S5 = low), all of the three outputs are
disabled. Outputs are discharged to ground according to
the discharge mode selected by the MODE pin (see VDDQ
and VTT Discharge Control Section). The code of each
state represents the following : S0 = full ON, S3 = suspend
to RAM (STR), S4 = suspend to disk (STD), S5 = soft
OFF. (See Table 2)
VDDQ
VTTREF
VTT
S0
Hi
Hi
On
On
On
S3
Lo
Hi
On
On
Off (Hi-Z)
S4/S5 Lo
Lo
Off
Off
Off
(Discharge) (Discharge) (Discharge)
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20
Table 3. Discharge Selection
MODE
Discharge Mode
VDD
No discharge
VDDQ
Tracking discharge
GND
Non-tracking discharge
When in tracking discharge mode, the RT8207Q
discharges outputs through the internal VTT regulator
transistors and VTT output tracks half of the VDDQ voltage
during this discharge. Note that the VDDQ discharge
current flows via VLDOIN to VTTGND; thus VLDOIN must
be connected to VDDQ in this mode. The internal LDO
can handle up to 1.5A and discharge quickly. After VDDQ
is discharged down to 0.15V, the terminal LDO will be
turned off and the operation mode is changed to the nontracking discharge mode.
When in non-tracking discharge mode, the RT8207Q
discharges outputs using internal MOSFETs which are
connected to VDDQ and VTT. The current capability of
these MOSFETs is limited to discharge slowly. Note that
the VDDQ discharge current flows from VDDQ to GND in
this mode.
When in no discharge mode, the RT8207Q does not
discharge output charge at all.
Output Inductor Selection
Table 2. S3 and S5 Truth Table
STATE S3 S5
The RT8207Q discharges VDDQ, VTTREF and VTT outputs
when S5 is low or in the S4/S5 state. There are two
different discharge modes. For the RT8207Q, the
discharge mode is set by connecting the MODE pin
according to Table 3.
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
t
x (VIN − VVDDQ )
L = ON
LIR x ILOAD(MAX)
where LIR is the ratio of the peak-to-peak ripple current to
the maximum average inductor current.
is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(IPEAK) :
IPEAK = ILOAD(MAX) + ⎡⎣(LIR / 2) x ILOAD(MAX) ⎤⎦
This inductor ripple current also impacts transient-response
performance, especially at low VIN − VVDDQ differences.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The peak amplitude of
the output transient (VSAG) is also a function of the output
transient. VSAG also features a function of the maximum
duty factor, which can be calculated from the on-time and
minimum off-time :
(ΔILOAD )2 x L x (tON + tOFF(MIN) )
2 x COUT x VVDDQ x ⎡⎣ VIN x tON − VVDDQ x (tON + tOFF(MIN) )⎤⎦
where minimum off-time, tOFF(MIN), is 400ns typically.
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance must be high enough to absorb the
inductor energy going from a full-load to no-load condition
without tripping the OVP circuit.
For CPU core voltage converters and other applications
where the output is subject to violent load transients, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance :
VP−P
ESR ≤
ILOAD(MAX)
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple :
ESR ≤
For low input-to-output voltage differentials (VIN/VVDDQ <
2), additional output capacitance is required to maintain
stability and good efficiency in ultrasonic mode.
The amount of overshoot due to stored inductor energy
can be calculated as :
VSOAR =
(IPEAK )2 x L
2 x COUT x VVDDQ
where IPEAK is the peak inductor current.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
fESR =
VSAG
=
Organic semiconductor capacitor(s) or specialty polymer
capacitor(s) are recommended.
f
1
≤ SW
2 x π x ESR x COUT
4
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic, unstable operation. However,
it is easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
inductor and connecting VDDQ or the FB voltage-divider
close to the inductor.
Unstable operation manifests itself in two related and
distinctly different ways : double-pulsing and feedback loop
instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough voltage
ramp in the output voltage signal. This “fools” the error
comparator into triggering a new cycle immediately after
the 400ns minimum off-time period has expired. Double
pulsing is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it may
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
VP−P
LIR x ILOAD(MAX)
where VP−P is the peak-to-peak output voltage ripple.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
21
Loop instability can result in oscillations at the output in
the form of line or load perturbations, which can trip the
over voltage protection latch or cause the output voltage
to fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully observe
the output-voltage-ripple envelope for overshoot and ringing.
It helps to simultaneously monitor the inductor current
with an AC current probe. Do not allow more than one
cycle of ringing after the initial step-response under- or
over-shoot.
Maximum Power Dissipation (W)1
RT8207Q
PD(MAX) = (TJ(MAX) − TA) / θJA
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
4.0
Figure 7. Derating Curve of Maximum Power Dissipation
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. Certain points must be considered before
starting a layout for the RT8207Q.
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
`
Connect an RC low pass filter from VDDP to VDD; 1μF
and 5.1Ω are recommended. Place the filter capacitor
close to the IC.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-24L 4x4 package, the thermal resistance, θJA, is
28°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
`
Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.
`
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
`
All sensitive analog traces and components such as
VDDQ, FB, PGND, PGOOD, CS, VDD, and TON should
be placed away from high voltage switching nodes such
as PHASE, LGATE, UGATE, and BOOT to avoid
coupling. Use internal layer(s) as ground plane(s) and
shield the feedback trace from power traces and
components.
P D(MAX) = (125°C − 25°C) / (28°C/W) = 3.57W for
WQFN-24L 4x4 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T(MAX) and thermal resistance,
θJA. The derating curve in Figure 7 allows the designer to
see the effect of rising ambient emperature on the
maximum power dissipation.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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22
is a registered trademark of Richtek Technology Corporation.
DS8207Q-00
December 2012
RT8207Q
`
VLDOIN should be connected to VDDQ output with short
and wide trace. If different power source is used for
VLDOIN, an input bypass capacitor should be placed as
close as possible to the pin with short and wide trace.
`
The output capacitor for VTT should be placed close to
the pin with short and wide connection in order to avoid
additional ESR and/or ESL of the trace.
`
It is strongly recommended to connect VTTSNS to the
positive node of VTT output capacitor(s) as a separate
trace from the high current power line to avoid additional
ESR and/or ESL. If it is needed to sense the voltage of
the point of the load, it is recommended to attach the
output capacitor(s) at that point. It is also recommended
to minimize any additional ESR and/or ESL of ground
trace between the GND pin and the output capacitor(s).
`
Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
`
Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed as close to the IC
as possible to minimize loops and reduce losses.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8207Q-00
December 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
23
RT8207Q
Outline Dimension
D2
D
SEE DETAIL A
L
1
E
E2
e
b
A3
Symbol
D2
E2
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A1
1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
3.950
4.050
0.156
0.159
Option 1
2.400
2.500
0.094
0.098
Option 2
2.650
2.750
0.104
0.108
E
3.950
4.050
0.156
0.159
Option 1
2.400
2.500
0.094
0.098
Option 2
2.650
2.750
0.104
0.108
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 24L QFN 4x4 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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24
DS8207Q-00
December 2012