INTEGRATED CIRCUITS DATA SHEET UAA2077BM 2 GHz image rejecting front-end Product specification Supersedes data of July 1995 File under Integrated Circuits, IC03 1995 Dec 13 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM Image rejection is achieved in the internal architecture by two RF mixers in quadrature and two all-pass filters in I and Q IF channels that phase shift the IF by 45° and 135° respectively. The two phase shifted IFs are recombined and buffered to furnish the IF output signal. FEATURES • Low-noise, wide dynamic range amplifier • Very low noise figure • Dual balanced mixer for over 25 dB on-chip image rejection For instance, signals presented at the RF input at the LO + IF frequency are rejected through this signal processing while signals at the LO − IF frequency can form the IF signal. An internal switch enables the upper or lower image frequency to be rejected. • IF I/Q combiner at 188 MHz • On-chip quadrature network • Down-conversion mixer for closed-loop transmitters • Independent TX/RX fast ON/OFF power-down modes The receiver section consists of a low-noise amplifier that drives a quadrature mixer pair. The IF amplifier has on-chip 45° and 135° phase shifting and a combining network for image rejection. The IF driver has differential open-collector type outputs. • Very small outline packaging • Very small application (no image filter). APPLICATIONS The LO part consists of an internal all-pass type phase shifter to provide quadrature LO signals to the receive mixers. The centre frequency of the phase shifter is adjustable for maximum image rejection in a given band. The all-pass filters outputs are buffered before being fed to the receive mixers. • 1800 MHz front-end for DCS1800 hand-portable equipment • Compact digital mobile communication equipment • TDMA receivers e.g. PCS and RF-LANS. The transmit section consists of a low-noise amplifier and a down-conversion mixer. In the transmit mode an internal LO buffer is used to drive the transmit IF down-conversion mixer. GENERAL DESCRIPTION UAA2077BM contains both a receiver front-end and a high frequency transmit mixer intended to be used in mobile telephones. Designed in an advanced BiCMOS process it combines high performance with low power consumption and a high degree of integration, thus reducing external component costs and total front-end size. All RF and IF inputs or outputs are balanced. Pins RXON, TXON and SXON enable a selection to be made of whether to reject the upper or lower image frequency and control of the different power-down modes. Special care has been taken for fast power-up switching. The main advantage of the UAA2077BM is its ability to provide over 25 dB of image rejection. Consequently, the image filter between the LNA and the mixer is suppressed. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC supply voltage 3.6 4.0 5.3 V ICC(RX) receive supply current 21.5 26.5 33.5 mA ICC(TX) transmit supply current 10.5 13.5 18 mA ICC(PD) supply current in power-down − − 50 µA Tamb operating ambient temperature −30 +25 +85 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UAA2077BM SSOP20 1995 Dec 13 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm 2 VERSION SOT266-1 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM BLOCK DIAGRAM n.c. n.c. TXON 4 7 11 SXON RXON handbook, full pagewidth VCCLNA 3 12 9 +45o UAA2077BM MIXER 17 RFINA RFINB LNAGND 5 6 LNA +135o 18 8 IFA IF COMBINER IFB low-noise amplifier RECEIVE SECTION VCCLO VQUADLO TRANSMIT SECTION 15 QUADRATURE PHASE SHIFTER 10 MIXER 19 LOGND 16 20 LOCAL OSCILLATOR SECTION 14 13 LOINA LOINB 2 1 MGD154 TXINB TXINA Fig.1 Block diagram. 1995 Dec 13 3 TXOA TXOB Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM PINNING SYMBOL PIN DESCRIPTION TXINA 1 transmit mixer input A (balanced) TXINB 2 transmit mixer input B (balanced) VCCLNA 3 supply voltage for LNA, IF parts and TX mixer n.c. 4 not connected RFINA 5 RF input A (balanced) RFINB 6 RF input B (balanced) n.c. 7 not connected LNAGND 8 ground for LNA, IF parts and TX mixer SXON 9 SX mode enable (see Table 1) VQUADLO 10 input voltage for LO quadrature trimming TXON 11 RXON handbook, halfpage TXINA 1 20 TXOB TXINB 2 19 TXOA VCCLNA 3 18 IFB n.c. 4 17 IFA RFINA 5 16 LOGND UAA2077BM RFINB 6 15 VCCLO TX mode enable (see Table 1) n.c. 7 14 LOINA 12 RX mode enable (see Table 1) LNAGND 8 13 LOINB LOINB 13 LO input B (balanced) SXON 9 12 RXON LOINA 14 LO input A (balanced) 15 supply voltage for LO parts VQUADLO 10 11 TXON VCCLO LOGND 16 ground for LO parts MGD155 IFA 17 IF output A (balanced) IFB 18 IF output B (balanced) TXOA 19 transmit mixer IF output A (balanced) TXOB 20 transmit mixer IF output B (balanced) 1995 Dec 13 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM The IF output is differential and of the open-collector type. Typical application will load the output with a differential 1 kΩ load; for example, a 1 kΩ resistor load at each IF output, plus a differential 2 kΩ load consisting of the input impedance of the IF filter or the input impedance of the matching network for the IF filter. The power gain refers to the available power on this 2 kΩ load. The path to VCC for the DC current should be achieved via tuning inductors. The output voltage is limited to VCC + 3Vbe or 3 diode forward voltage drops. FUNCTIONAL DESCRIPTION Receive section The circuit contains a low-noise amplifier followed by two high dynamic range mixers. These mixers are of the Gilbert-cell type, the whole internal architecture is fully differential. The local oscillator, shifted in phase to 45° and 135°, mixes the amplified RF to create I and Q channels. The two I and Q channels are buffered, phase shifted by 45° and 135° respectively, amplified and recombined internally to realize the image rejection. Fast switching, ON/OFF, of the receive section is controlled by the hardware input RXON. Balanced signal interfaces are used for minimizing crosstalk due to package parasitics. handbook, full pagewidth MIXER VCCLNA IF amplifier +45o IFA RFINA RFINB IF COMBINER MIXER IFB LNA LNAGND IF amplifier +135o MGD157 RXON LOIN Fig.3 Block diagram, receive section. 1995 Dec 13 5 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM Local oscillator section Transmit mixer The local oscillator (LO) input directly drives the two internal all-pass networks to provide quadrature LO to the receive mixers. This mixer is used for down-conversion to the transmit IF. Its inputs are coupled to the transmit RF which is down-converted to a modulated transmit IF frequency, phase-locked with the baseband modulation. The centre frequency of the receive band is adjustable by the voltage on pin VQUADLO. This should be achieved by connecting a resistor between VQUADLO and VCC. Over 25 dB of image rejection can be obtained by an optimum resistor value. The IF outputs are high-impedance (open-collector type). Typical application will load the output with a differential 500 Ω load; for example, a 500 Ω resistor load, connected to VCC for DC path, at each TX output, plus a differential 1 kΩ consisting of the input impedance of the matching network for the following TX part. The mixer can also be used for frequency up-conversion. A synthesizer-ON mode (SX mode) is used to power-up all LO input buffers, thus minimizing the pulling effect on the external VCO when entering the receive or transmit mode. This mode is active when SXON = 1. Fast switching ON/OFF, of the transmit section is controlled by the hardware input TXON. to RX handbook, halfpage VCCLO handbook, halfpage TX MIXER TXOA TXOB LOIN QUAD VQUADLO MGD153 LOGND to TX TXON TXINB TXINA MGD156 LOINA LOINB Fig.4 Block diagram, LO section. Fig.5 Block diagram, transmit mixer. Table 1 Control of power status EXTERNAL PIN LEVEL CIRCUIT MODE OF OPERATION TXON RXON SXON LOW LOW LOW power-down mode LOW HIGH LOW RX mode, fLO < fRF: receive section and LO buffers to RX on HIGH LOW LOW TX mode: transmit section and LO buffers to TX on LOW LOW HIGH SX mode: complete LO section on LOW HIGH HIGH SRX mode, fLO < fRF: receive section on and SX mode active HIGH LOW HIGH STX mode: transmit section on and SX mode active HIGH HIGH LOW RX mode, fLO > fRF: receive section and LO buffers to RX on HIGH HIGH HIGH SRX mode, fLO > fRF: receive section on and SX mode active 1995 Dec 13 6 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage − 9.0 V ∆GND difference in ground supply voltage applied between LOGND and LNAGND − 0.6 V Pi(max) maximum power input − +20 dBm Tj(max) maximum operating junction temperature − +150 °C Pdis(max) maximum power dissipation in quiet air − 250 mW Tstg storage temperature −65 +150 °C THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE UNIT 120 K/W HANDLING All pins withstand the ESD test in accordance with MIL-STD-883C class 2 (method 3015.5), except pins LOINA and LOINB which withstand 1500 V (class 1). 1995 Dec 13 7 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM DC CHARACTERISTICS VCC = 4 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Pins: VCCLNA and VCCLO VCC supply voltage ICC(RX) over full temperature range 3.6 4.0 5.3 V supply current in RX mode 21.5 26.5 33.5 mA ICC(TX) supply current in TX mode 10.5 13.5 18 mA ICC(PD) supply current in power-down mode − − 50 µA ICC(SX) supply current in SX mode 5.5 7.5 10 mA ICC(SRX) supply current in SRX mode − 29 − mA ICC(STX) supply current in STX mode − 18 − mA − 1.25 − V Pins: RXON, TXON and SXON Vth CMOS threshold voltage note 1 VIH HIGH level input voltage 0.7VCC − VCC V VIL LOW level input voltage −0.3 − 0.8 V IIH HIGH level static input current pins at VCC − 0.4 V −1 − +1 µA IIL LOW level static input current pins at 0.4 V −1 − +1 µA receive section on − 2.0 − V receive section on − 2.5 − mA transmit section on − 2.0 − V transmit section on − 0.9 − mA RXON, TXON or SXON HIGH − 3.3 − V Pins: RFINA and RFINB VI DC input voltage level Pins: IFA and IFB IO DC output current Pins: TXINA and TXINB VI DC input voltage level Pins: TXOA and TXOB IO DC output current Pins: LOINA and LOINB VLOIN DC input voltage level Note 1. The referenced inputs should be connected to a valid CMOS input level. 1995 Dec 13 8 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM AC CHARACTERISTICS VCC = 4 V; Tamb = −30 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Receive section (receive section enabled) RiRX RF input resistance (real part of the parallel input impedance) balanced; at 1850 MHz − 60 − Ω CiRX RF input capacitance (imaginary part of the parallel input impedance) balanced; at 1850 MHz − 1 − pF fiRX RF input frequency 1800 − 2000 MHz RLiRX return loss on matched RF input balanced; note 1 11 15 − dB GCPRX conversion power gain differential RF inputs to differential IF outputs loaded to 1 kΩ differential 17 20 23 dB Grip gain ripple as a function of RF frequency between 1805 and 1880 MHz; note 2 − 0.2 − dB ∆G/T gain variation with temperature Tamb = −30 to +25 °C; note 2 −20 0 +10 mdB/°C Tamb = +25 to +85 °C; note 2 −40 −30 −20 mdB/°C CP1RX 1 dB compression point differential RF inputs to differential IF outputs; note 1 −26 −23 − dBm DES3 3 dB desensitisation point interferer frequency offset: 3 MHz; differential RF inputs to differential IF outputs; note 1 − −30 − dBm interferer frequency offset: 20 MHz; − differential RF inputs to differential IF outputs; note 1 −27 − dBm IP2DRX 2nd-order intercept point differential RF inputs to differential IF outputs; note 2 +15 +22 − dBm IP3RX 3rd-order intercept point differential RF inputs to differential IF outputs; note 2 −23 −17 − dBm NFRX overall noise figure differential RF inputs to differential IF outputs; notes 2 and 3 − 4.3 5.0 dB ZLRX typical application IF output load balanced impedance − 1 − kΩ RLiRX return loss on matched IF input balanced; note 1 11 15 − dB foRX IF frequency range 170 188 210 MHz IRRX rejection of image frequency VQUADLO tuned 20 − − dB fLO < fRF; fIF = 188 MHz; note 4 25 32 − dB 1600 − 2200 MHz Local oscillator section (receive section enabled) fiLO LO input frequency RiLO LO input resistance (real part of the parallel input impedance) balanced − 45 − Ω CiLO LO input capacitance (imaginary part of the parallel input impedance) balanced − 2 − pF 1995 Dec 13 9 Philips Semiconductors Product specification 2 GHz image rejecting front-end SYMBOL PARAMETER UAA2077BM CONDITIONS MIN. TYP. MAX. UNIT RLiLO return loss on matched input (including standby mode) note 1 9 12 − dB ∆RLiLO return loss variation between SX, SRX and STX modes linear S11 variation; note 1 − 5 − mU PiLO LO input power level −6 −3 +3 dBm RILO reverse isolation LOIN to RFIN at LO frequency; note 1 40 − − dB Rtune image rejection tuning resistor connected between VQUADLO and VCC 0 4.7 − kΩ Transmit section (transmit section enabled) ZLTX TX IF typical load impedance balanced − 500 − Ω RLoTX return loss on matched TX IF output note 1 11 15 − dB RiTX TX RF input resistance (real part of the parallel input impedance) balanced; at 1750 MHz − 65 − Ω CiTX TX RF input capacitance (imaginary part of the parallel input impedance) balanced; at 1750 MHz − 1 − pF fiTX TX input frequency 1600 − 2000 MHz RLiTX return loss on matched TX input note 1 10 15 − dB GCPTX conversion power gain 6 9 12 dB foTX TX output frequency 50 − 400 MHz CP1TX 1 dB input compression point note 2 −25 −22 − dBm differential transmitter inputs to differential transmitter IF outputs loaded with 500 Ω differential IP2TX 2nd-order intercept point note 2 − +22 − dBm IP3TX 3rd-order intercept point note 2 −20 −16 − dBm NFTX noise figure double sideband; notes 2 and 3 − 5 9 dB ITX isolation LOIN to TXIN; note 1 40 − − dB RITX reverse isolation TXIN to LOIN; note 1 40 − − dB 1 5 20 µs Timing tstu start-up time of each block Notes 1. Measured and guaranteed only on UAA2077BM demonstration board at Tamb = +25 °C. 2. Measured and guaranteed only on UAA2077BM demonstration board. 3. This value includes printed-circuit board and balun losses. 4. Measured and guaranteed only on UAA2077BM demonstration board at Tamb = +25 °C, with a 4.7 kΩ resistor connected between VQUADLO and VCC. 1995 Dec 13 10 1995 Dec 13 11 1 2 C8 8.2 pF R4 560 kΩ SXON VQUADLO C14 1.2 pF 4V 8.2 pF C3 L1 5.6 nH R8 4.7 kΩ C6 8.2 pF 8.2 pF C1 4V 8.2 pF 8.2 pF C17 C2 1.2 pF L6 5.6 nH C15 1.8 pF L7 4.7 nH C16 1.8 pF C18 C30 8.2 pF L15 6.8 nH C5 82 pF 1 2 C31 82 pF C7 8.2 pF 10 9 R3 560 kΩ TXON 1 2 11 12 13 14 7 8 15 6 16 5 UAA2077BM 17 18 19 20 4 3 2 1 C9 8.2 pF R5 560 kΩ RXON R2 560 Ω 4V R1 560 Ω Fig.6 Application diagram. Figure 6 illustrates the electrical diagram of the UAA2077BM Philips demonstration board for DCS1800 applications. For measurement purposes all matching is to 50 Ω. Different values will be used in a real application. RFIN 1.8 to 2 GHz TXIN 1.6 to 1.8 GHz L8 4.7 nH 4V L12 100 nH L11 100 nH 3.3 nH L9 C21 2.2 pF C29 8.2 pF C24 3.9 pF C23 4V 3.3 nH L10 MBG014 C25 12 pF C28 1 nF L14 56 nH C27 8.2 pF IFB 56 nH L13 12 pF C26 TXOUT 93 MHz C22 IFA 82 pF 3.9 pF L4 120 nH C13 22 pF LOIN 1.55 to 1.75 GHz C20 2.2 pF R7 1200 Ω C12 120 nH L5 22 pF C19 8.2 pF C10 12 pF C11 C4 120 pF R6 1200 Ω 4V L2 180 nH L3 180 nH 12 pF IF 188 MHz 2 GHz image rejecting front-end handbook, full pagewidth Philips Semiconductors Product specification UAA2077BM APPLICATION INFORMATION Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-04-05 95-02-25 SOT266-1 1995 Dec 13 EUROPEAN PROJECTION 12 o Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1995 Dec 13 13 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Dec 13 14 Philips Semiconductors Product specification 2 GHz image rejecting front-end UAA2077BM NOTES 1995 Dec 13 15 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. 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(02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 © Philips Electronics N.V. 1995 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 413061/1100/03/pp16 Document order number: Date of release: 1995 Dec 13 9397 750 00526