S3C7524/C7528/P7528/C7534/C7538/P7538 1 PRODUCT OVERVIEW PRODUCT OVERVIEW The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy consumption and low operating voltage. You can select from two ROM sizes: 4K or 8K bytes Except for the difference in ROM size, the features and functions of the S3C7524 and the S3C7528, the S3C7534 and the S3C7538 are identical. With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, theS3C7524/C7528 /C5304/C5308 offers an excellent design solution for a wide variety of telecommunication applications. Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the S3C7524/C7528, and up to 23 pins of the available 30-pin SDIP or 32-pin SOP package for the S3C7534/C7538 can be assign to I/O. Six vectored interrupts for S3C7524/C7528 and four vectored interrupts for S3C7534/C7538 provide fast response to internal and external events. In addition, the S3C7524/C7528/C7534/C7538 's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C7524/C7528 microcontroller is also available in OTP (One Time Programmable) version, S3P7528. The S3C7534/C7538 microcontroller is also available in OTP (One Time Programmable) version, S3P7538. The S3P7528/P7538 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM. The S3P7528 is comparable to S3C7524/C7528, both in function and in pin configuration. Also, the S3P7538 is comparable to the S3C7534/C7538, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 FEATURES SUMMARY Memory Interrupts • 768 × 4-bit RAM • • 4,096 × 8-bit ROM (S3C7524/C7534) 8,192 × 8-bit ROM (S3C7528/C7538) 3 external interrupt vectors (S3C7524/C7528) 1 external interrupt vectors (S3C7534/C7538) • 3 internal interrupt vectors • 2 quasi-interrupts 35 I/O Pins • Input only: 4 pins (S3C7524/C7528) 1 pins (S3C7534/C7538) Power-Down Modes • • Idle: Only CPU clock stops I/O: 23 pins (S3C7524/C7528) 14 pins (S3C7534/C7538) • Stop: System clock stops • N-channel open-drain I/O: 8 pins Oscillation Sources • Crystal, or ceramic for main system clock • Main system clock frequency: 0.4–6.0 MHz (typical) DTMF Generator • CPU clock divider circuit (by 4, 8, or 64) • Instruction Execution Times Memory-Mapped I/O Structure • Data memory bank 15 16 dual-tone frequencies for tone dialing 8-Bit Basic Timer • 0.95, 1.91, and 15.3 µs at 4.19 MHz • Programmable interval timer • 1.12, 2.23, 17.88 µs at 3.58 MHz • Watchdog timer • 0.67, 1.33, 10.7 µs at 6.0 MHz Two 8-Bit Timer/Counters Operating Temperature • Programmable 8-bit timer • • External event counter function • Arbitrary clock frequency output Watch Timer – 40 °C to 85 °C Operating Voltage Range • 2.0 V to 5.5 V Package Types • Real-time and interval time measurement • • 42 SDIP, 44 QFP (S3C7524/C7528) Four frequency outputs to the BUZ pin • 30 SDIP, 32 SOP (S3C7534/C7538) Bit Sequential Carrier • 1-2 Supports 8-bit serial data transfer in arbitrary format S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW BLOCK DIAGRAM INT0, INT1, INT2, INT4 RESET Xin Xout BASIC TIMER 8-BIT TIMER/ COUNTER 0 8-BIT TIMER/ COUNTER 1 P6.0–P6.3 / KS0–KS3 I/O PORT 6 P7.0–P7.3 / KS4–KS7 I/O PORT 7 P8.0–P8.3 P9.0–P9.2 INTERRUPT CONTROL BLOCK CLOCK PROGRAM COUNTER INTERNAL INTERRUPTS WATCH TIMER STACK POINTER WATCH-DOG TIMER INPUT PORT 1 INSTRUCTION DECODER PROGRAM STATUS WORD I/O PORT 8 I/O PORT 9 ARITHMETIC AND LOGIC UNIT 768 x 4-BIT DATA MEMORY I/O PORT 2 FLAGS P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ I/O PORT 3 P3.0 / TCL0 P3.1 / TCL1 P3.2 P3.3 I/O PORT 4 P4.0 / BTCO P4.1 −P4.3 I/O PORT 5 P5.0–P5.3 PROGRAM MEMORY S3C7524/C7534: 4 KBytes S3C7528/C7538: 8 KBytes DTMF GENERATOR DTMF NOTE: S3C7534/C7538 does not use P1.1/INT1, P1.2/INT2, P1.3/INT3, P3.2, P3.3, INT1, INT2, INT4, P8.0-P8.3, and P9.0-P9.2. Figure 1–1. S3C7524/C7528 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 PIN ASSIGNMENTS S3C7524/C7528 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (42-SDIP-600) P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ P3.0 / TCL0 P3.1 / TCL1 VDD V SS XOUT XIN TEST P4.0 / BTCO P4.1 RESET P3.2 P3.3 P4.2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 Figure 1–2. S3C7524/C7528 Pin Assignment Diagrams (42–SDIP) 1-4 PRODUCT OVERVIEW 44 43 42 41 40 39 38 37 36 35 34 P2.1 / TCLO1 P2.0 / TCLO0 P1.3 / INT4 P1.2 / INT2 P1.1 / INT1 P1.0 / INT0 NC P9.2 P9.1 P9.0 DTMF S3C7524/C7528/P7528/C7534/C7538/P7538 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 KS57C5204/C5208 29 28 (44-QFP-1010B) 27 26 25 24 23 P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 RESET P3.2 P3.3 P4.2 NC P4.3 P8.0 P8.1 P8.2 P8.3 P5.0 12 13 14 15 16 17 18 19 20 21 22 P2.2 / CLO P2.3 / BUZ P3.0 / TCL0 P3.1 / TCL1 VDD VSS XOUT XIN TEST P4.0 / BTCO P4.1 Figure 1–3. S3C7524/C7528 Pin Assignment Diagrams (44–QFP) 1-5 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 S3C7534/C7538 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (30-SDIP-400) VSS XOUT XIN TEST P4.0 / BTCO P4.1 RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P3.1 / TCL1 P3.0 / TCL0 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 1–4. S3C7534/C7538 Pin Assignment Diagrams (30–SDIP) S3C7534/C7538 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (32-SOP-405A) VSS XOUT XIN TEST P4.0 / BTCO P4.1 RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1 / TCL1 P3.0 / TCL0 P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 NC DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 1–5. S3C7534/C7538 Pin Assignment Diagrams (32–SOP) 1-6 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C7524/C7528 Pin Descriptions Pin Name Pin Reset Type Value Description Pin Number Share Pin Circuit Type P1.0 P1.1 P1.2 P1.3 I I 4-bit input port. 1-bit and 4-bit read and test is possible. Each pull-up resistors are assignable by software. 1 (39) 2 (40) 3 (41) 4 (42) INT0 INT1 INT2 INT4 A-4 P2.0 P2.1 P2.2 P2.3 I/O I 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 5 (43) 6 (44) 7 (1) 8 (2) TCLO0 TCLO1 CLO BUZ D-2 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 9 (3) 10 (4) 19 (13) 20 (14) TCL0 TCL1 D-4 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. N-channel open-drain or push-pull output can be selected by software (1-bit unit) Ports 4 and 5 can be paired to support 8-bit data transfer. 16 (10) 17 (11) 21 (15) 22 (17) BTCO E-2 D-4 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 I/O I P5.0–P5.3 P6.0–P6.3 I/O I P7.0–P7.3 P8.0–P8.3 P9.0–P9.2 I/O I 27–30 (22–25) 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 31–34 (26–29) 35–38 (30–33) KS0–KS3 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. Ports 8 and 9 can be paired to enable 8-bit data transfer. 23–26 (18–21) 40–42 (35–37) – KS4–KS7 D-2 1-7 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 Table 1-1. S3C7524/C7528 Pin Descriptions (Continued) Pin Name Pin Reset Type Value Description Pin Number Share Pin Circuit Type DTMF O – DTMF output. 39 (34) – G-6 BTCO I/O I Basic timer clock output 16 (10) P4.0 E-2 INT0 INT1 I I External interrupts. The triggering edge for INT0 and INT1 is selectable. 1 (39) 2 (40) P1.0 P1.1 A-3 INT2 I I Quasi-interrupt with detection of rising edges 3 (41) P1.2 A-3 INT4 I I External interrupt with detection of rising and falling edges. 4 (42) P1.3 A-3 TCLO0 I/O I Timer/counter 0 clock output 5 (43) P2.0 D-2 TCLO1 I/O I Timer/counter 1 clock output 6 (44) P2.1 D-2 CLO I/O I Clock output 7 (1) P2.2 D-2 BUZ I/O I 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound 8 (2) P2.3 D-2 TCL0 I/O I External clock input for timer/counter 0 9 (3) P3.0 D-4 TCL1 I/O I External clock input for timer/counter 1 10 (4) P3.1 D-4 KS0–KS3 I/O I Quasi-interrupt inputs with falling edge detection 31–34 (26–29) 35–38 (30–33) P6.0– P6.3 P7.0– P7.3 D-4 VDD – – Power supply 11 (5) – – VSS – – Ground 12 (6) – – RESET – – RESET signal 18 (12) – B Xin Xout – – Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use Xin and input Xin's reverse phase to Xout) 14 (8) 13 (7) – – TEST – – Test signal input 15 (9) – – NC – – No connection (16, 38) – – KS4–KS7 NOTE: Parentheses indicate pin number for 44 QFP package. 1-8 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW Table 1-2. S3C7534/C7538 Pin Descriptions Pin Name Pin Type P1.0 I P2.0 P2.1 P2.2 P2.3 I/O P3.0 P3.1 Description Pin Number Share Pin Circuit Type 1-bit input port. 1-bit and 4-bit read and test is possible. Each bit pull-up resistors are assignable. 23 (25) INT0 A-4 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 2 and 3 can be paired to enable 8-bit data transfer. 24 (26) 25 (27) 26 (28) 27 (29) TCLO0 TCLO1 CLO BUZ D-2 28 (30) 29 (31) TCL0 TCL1 D-4 P4.0 P4.1 P4.2 P4.3 P5.0–P5.3 I/O 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. The N-channel open-drain or push-pull output can be selected by software (1-bit unit). Ports 4 and 5 can be paired to enable 8-bit data transfer. 5 (5) 6 (6) 8 (8) 9 (10) 10–13 (11–14) BTCO E-2 P6.0–P6.3 I/O 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. Each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 14–17 (15–18) 18–21 (19–22) KS0–KS3 D-4 P7.0–P7.3 KS4–KS7 1-9 PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538 Table 1-1. S3C7534/C7538 Pin Descriptions (Continued) Pin Name I/O Type Description Pin Number Share Pin Circuit Type DTMF O DTMF output. 22 (23) – G-6 INT0 I External interrupt input. The triggering edge for INT0 is selectable. 23 (25) P1.0 A-3 TCLO0 I/O Timer/counter 0 clock output 24 (26) P2.0 D-2 TCLO1 I/O Timer/counter 1 clock output 25 (27) P2.1 D-2 CLO I/O Clock output 26 (28) P2.2 D-2 BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 4.19 MHz for buzzer sound 27 (29) P2.3 D-2 TCL0 I/O External clock input for timer/counter 0 28 (30) P3.0 D-4 TCL1 I/O External clock input for timer/counter 1 29 (31) P3.1 D-4 BTCO I/O Basic timer clock output 5 (5) P4.0 E-2 30 (32) – – VDD – Power supply VSS – Ground 1 (1) – – Xin Xout – Crystal, or ceramic oscillator signal for main system clock. (For external clock input, use Xin and input Xin's reverse phase to Xout) 3 (3) 2 (2) – – NC – No connection (9, 24) – – TEST – Test signal input 4 (4) – – RESET – RESET signal 7 (7) – B 14–17 (15–18) 18–21 (19–22) P6.0– P6.3 P7.0– P7.3 D-4 KS0–KS3 I/O Quasi-interrupt inputs with falling edge detection KS4–KS7 NOTE: Parentheses indicate the pin number for 32-SOP package. 1-10 S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD PULL-UP RESISTOR P-CHANNEL P-CHANNEL IN RESISTOR ENABLE N-CHANNEL IN SCHMITT TRIGGER Figure 1–8. Pin Circuit Type A-4 Figure 1–6. Pin Circuit Type A VDD VDD PULL-UP RESISTOR P-CHANNEL DATA OUT IN N-CHANNEL SCHMITT TRIGGER Figure 1–7. Pin Circuit Type B OUTPUT DISABLE Figure 1–9. Pin Circuit Type C 1-11 PRODUCT OVERVIEW KS57C5204/C5208/P5208/C5304/C5308/P5308 MICROCONTROLLER VDD VDD PULL-UP RESISTOR RESISTOR ENABLE P-CHANNEL PNE VDD DATA PULL-UP RESISTOR PULL-UP RESISTOR ENABLE P-CHANNEL I/O DATA OUTPUT DISABLE CIRCUIT TYPE C I/O Figure 1–10. Pin Circuit Type D-2 OUTPUT DISABLE N-CHANNEL Figure 1–12. Pin Circuit Type E-2 VDD PULL-UP RESISTOR RESISTOR ENABLE DATA OUTPUT DISABLE DTMF OUT P-CHANNEL CIRCUIT TYPE C I/O OUTPUT DISABLE SCHMITT TRIGER Figure 1–11. Pin Circuit Type D-4 1-12 Figure 1–13. Pin Circuit Type G-6 S3C7524/C7528/P7528/C7534/C7538/P7538 13 ELECTRICAL DATA ELECTRICAL DATA In this section, information on S3C7524/C7528 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — System clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at Xin and Xout — TCL timing — Input timing for RESET — Input timing for external interrupts — Serial data transfer timing Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 13–1 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Supply Voltage VDD – Input Voltage VI1 Output Voltage VO – Output Current High I OH One I/O port active – 15 All I/O ports active – 35 One I/O port active + 30 (Peak value) Output Current Low I OL Rating All I/O ports Units – 0.3 to + 6.5 V – 0.3 to VDD + 0.3 V – 0.3 to VDD + 0.3 V mA mA + 15 (note) All I/O ports active + 100 (Peak value) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for output current low ( IOL ) are calculated as peak value × Duty . Table 13-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Input high voltage Input low voltage 13–2 Symbol Conditions Min Typ Max Units – VDD V VIH1 All input pins except those specified below for VIH2 – VIH3 0.7 VDD VIH2 Ports 1, 3, 6, 7, and RESET 0.8 VDD VDD VIH3 Xin and Xout VDD – 0.1 VDD VIL1 All input pins except those specified below for VIL2–VIL3 VIL2 Ports 1, 3, 6, 7, and RESET VIL3 Xin and Xout – – 0.3 VDD 0.2 VDD 0.1 V S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Units VDD – 1.0 – – V V Output high voltage VOH IOH = – 1 mA Ports except 1 Output low voltage VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 4 and 5 only – 0.4 2 VDD = 2.0 to 5.5 V, IOL = 1.6mA – – 0.4 VDD = 4.5 V to 5.5 V IOL= 4 mA, all out ports except 4,5 – – 2 VDD = 2.0 to 5.5 V, IOL = 1.6mA – – 0.4 ILIH1 VI = VDD All input pins except those specified below – – 3 ILIH2 VI = VDD Xin and Xout ILIL1 VI = 0 V VOL2 Input high leakage current Input low leakage current V µA 20 – – –3 µA All input pins except below and RESET ILIL2 VI = 0 V Xin and Xout only Output high leakage current ILOH VO = VDD All out pins – – 3 µA Output low leakage current ILOL VO = 0 V Xin and Xout only – – –3 µA Pull-up resistor RL1 VDD = 5 V; VI = 0 V 25 47 100 kΩ VDD = 3 V 50 95 200 VDD = 5 V; VI = 0 V; RESET VDD = 3 V 100 220 400 200 450 800 – 20 except RESET RL2 13–3 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol Conditions Min Typ Max Units – 2.9 5.0 mA 1.6 3.0 2.6 8.0 3.58 MHz 1.8 4.0 6.0 MHz 1.8 4.0 3.58 MHz 1.2 2.3 0.7 2.5 Run mode; VDD = 5 V ± 10% (2) (DTMF on) 3.58 MHz crystal oscillator, C1 = C2 = 22 pF IDD1 VDD = 3 V ± 10% IDD2 Run mode; VDD = 5 V ± 10% (DTMF off) crystal oscillator, C1 = C2 = 22 pF VDD = 3 V ± 10% IDD3 IDD4 6.0 MHz – Idle mode; = VDD = 5 V ± 10% 6.0 MHz crystal oscillator, C1 = C2 = 22 pF 3.58 MHz 0.6 1.8 VDD = 3 V ± 10% 6.0 MHz 0.3 1.5 3.58 MHz 0.2 1.0 0.01 3 0.01 2 Stop mode; VDD = 5 V ± 10% – – Stop mode; VDD = 3 V ± 10% Row tone level VROW VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2 V RL = 5kΩ Ratio of column to row tone dBCR VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2 V RL = 5kΩ 1 2 3 Distortion (Dual tone) THD VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2 V RL = 5kΩ, 1MHz band – – 5 – 16.0 – 14.0 – 11.0 mA mA µA dBV % NOTES 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers. 2. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 13–4 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA Table 13-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout C1 Crystal Oscillator Xin Test Condition Min Typ Max Units Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 2.0 V to 5.5 V 0.4 – 4.2 – – 4 ms MHz C2 Xout C1 Parameter Stabilization time (2) VDD = 3 V Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 2.0 V to 5.5 V 0.4 – 4.2 – – 10 ms VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 2.0 V to 5.5V 0.4 – 4.2 – 83.3 – 1250 C2 Stabilization time (2) External Clock Xin Xout Xin input frequency (1) Xin input high and low level width (tXH, tXL) VDD = 3 V ns NOTES 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 13–5 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 Table 13-4. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF COUT – – 15 pF CIO – – 15 pF Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 2.0 V to 5.5 V 0.95 VDD = 2.7 V to 5.5 V 0 – 1.5 MHz 1 MHz – – µs Input Capacitance Output Capacitance I/O Capacitance Table 13-5. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time (1) Symbol tCY TCL0, TCL1 Input f TI0, f TI1 Frequency Conditions VDD = 2.0 V to 5.5V TCL0, TCL1 Input tTIH0, tTIL0 High, Low Width tTIH1, tTIL1 VDD = 2.7 V to 5.5 V 0.48 VDD = 2.0 V to 5.5 V 1.8 Interrupt Input High, Low Width tINTH, tINTL INT0, INT1, INT2, INT4, KS0–KS7 10 – – µs RESET Input Low tRSL Input 10 – – µs Width 13–6 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA CPU CLOCK Main Osc. Freq. 1.5 MHz 6 MHz 1.05 MHz 4.2 MHz 15.625 kHz 1 2 3 4 5 6 7 2.7 V SUPPLY VOLTAGE (V) CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64) Figure 13-1. Standard Operating Voltage Range Table 13-6. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.5 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL – – µs tWAIT Released by RESET Released by interrupt – ms ms Oscillator stabilization wait time (1) VDDDR = 1.5 V 0 – – 17 2 /fx (2) NOTES 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 13–7 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 TIMING WAVEFORMS INTERNAL RESET OPERATION IDLE MODE OPERATING MODE STOP MODE DATA RETENTION MODE VDD EXECUTION OF STOP INSTRUCTION VDDDR RESET tWAIT t SREL Figure 13-2. Stop Mode Release Timing When Initiated By RESET IDLE MODE NORMAL OPERATING MODE STOP MODE DATA RETENTION MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION tSREL tWAIT POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request 13–8 S3C7524/C7528/P7528/C7534/C7538/P7538 ELECTRICAL DATA Timing Waveforms (continued) 0.8 VDD 0.8 VDD 0.2 VDD MEASUREMENT POINTS 0.2 VDD Figure 13-4. A.C. Timing Measurement Points (Except for Xin) 1/fx tXL tXH Xin VDD - 0.1 V 0.1 V Figure 13-5. Clock Timing Measurement at Xin 1 / f TI tTIL tTIH TCL 0.8 V DD 0.2 V DD Figure 13-6. TCL Timing 13–9 ELECTRICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 tRSL RESET 0.2 VDD Figure 13-7. Input Timing for RESET Signal tINTL INT0, 1, 2, 4 K0 to K7 t INTH 0.8 VDD 0.2 VDD Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts 13–10 S3C7524/C7528/P7528/C7534/C7538/P7538 14 MECHANICAL DATA MECHANICAL DATA This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram — Pad/pin coordinate data table #22 0.2 5 42-SDIP-600 +0 - 0 .10 .05 0-15 15.24 14.00 ± 0.20 #42 #21 NOTE: 0.10 1.00 ± 0.10 1.78 5.08 MAX (1.77) 0.50 ± 3.30 ± 0.30 39.10 ± 0.20 3.50 ± 39.50 MAX 0.51 MIN 0.20 #1 Dimensions are in millimeters. Figure 14-1. 42-SDIP-600 Package Dimensions 14–1 MECHANICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 13.20 ± 0.30 0-8 10.00 ± 0.20 10.00 ± 0.20 + 0.10 - 0.05 0.10 MAX 44-QFP-1010B 0.80 ± 0.20 13.20 ± 0.30 0.15 #44 #1 0.80 + 0.10 0.35 - 0.05 0.15 MAX 0.05 MIN (1.00) 2.05 ± 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 14-2. 44-QFP-1010B Package Dimensions 14–2 S3C7524/C7528/P7528/C7534/C7538/P7538 #16 0-15 0.2 5 30-SDIP-400 +0 - 0 .10 .05 10.16 8.94 ± 0.20 #30 MECHANICAL DATA (1.30) NOTE: 0.56 ± 0.10 1.12 ± 0.10 1.778 5.21 MAX 27.48 ± 0.20 3.30 ± 0.30 27.88 MAX 3.81 ± 0.20 #15 0.51 MIN #1 Dimensions are in millimeters. Figure 14-3. 30-SDIP-400 Package Dimensions 14–3 MECHANICAL DATA S3C7524/C7528/P7528/C7534/C7538/P7538 0-8 #17 19.90 ± 0.20 0.20 + 0.10 - 0.05 2.20 MAX 20.30 MAX 0.10 0.25 2.00 ± #16 0.90 ± 8.34 ± 32-SOP-450A #1 11.43 0.20 12.00 ± 0.30 #32 (0.43) 0.40 ± 0.10 NOTE: 1.27 0.05 MIN 0.10 MAX Dimensions are in millimeters. Figure 14-4. 32-SOP-450A Package Dimensions 14–4 S3C7524/C7528/P7528/C7534/C7538/P7538 15 S3P7528/P7538 OTP S3P7528/P7538 OTP OVERVIEW The S3P7528/P7538 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7524/C7528/C7534/C7538 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The S3P7528/P7538 is fully compatible with the S3C7528/C7538, both in function and in pin configuration. Because of its simple programming requirements, the S3P7528/P7538 is ideal for use as an evaluation chip for the S3C7528/C7538. S3P7528 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (42-SDIP-600) P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / INT4 P2.0 / TCLO0 P2.1 / TCLO1 P2.2 / CLO P2.3 / BUZ SDAT / P3.0 / TCL0 SCLK / P3.1 / TCL1 VDD / VDD VSS / VSS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P3.2 P3.3 P4.2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P9.2 P9.1 P9.0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 NOTE: The bold words indicate OTP pin names. Figure 15-1. S3P7528 Pin Assignments (42-SDIP) 15–1 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KS57P5308 (32-SOP-405A) VSS / V SS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD / VDD P3.1 / TCL1 / SCLK P3.0 / TCL0 / SDAT P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 NC DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 15-2. S3P7528 Pin Assignments (44-QFP) 15–2 S3C7524/C7528/P7528/C7534/C7538/P7538 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3C7538 (30-SDIP-400) VSS / V SS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 S3P7528/P7538 OTP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD / VDD P3.1 / TCL1 / SCLK P3.0 / TCL0 / SDAT P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 15-3. S3P7538 Pin Assignments (30-SDIP) 15–3 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3P7538 (32-SOP-405A) VSS / V SS XOUT XIN VPP / TEST P4.0 / BTCO P4.1 RESET / RESET P4.2 NC P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 / KS0 P6.1 / KS1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD / VDD P3.1 / TCL1 / SCLK P3.0 / TCL0 / SDAT P2.3 / BUZ P2.2 / CLO P2.1 / TCLO1 P2.0 / TCLO0 P1.0 / INT0 NC DTMF P7.3 / KS7 P7.2 / KS6 P7.1 / KS5 P7.0 / KS4 P6.3 / KS3 P6.2 / KS2 Figure 15-4. S3P7538 Pin Assignments (32-SOP) 15–4 S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP Table 15-1. S3P7528 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P3.0 SDAT 9 (3) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. P3.1 SCLK 10 (4) I/O Serial clock pin. Input only pin. TEST VPP (TEST) 15 (9) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 18 (12) I Chip initialization VDD / VSS VDD / VSS 11/12 (5/6) I Logic power supply pin. VDD should be tied to +5 V during programming. NOTE: Parentheses indicate pin numbers of 44 QFP package. Table 15-2. S3P7538 Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name During Programming Pin Name Pin No. I/O Function P3.0 SDAT 28 (30) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. P3.1 SCLK 29 (31) I/O Serial clock pin. Input only pin. TEST VPP (TEST) 4 (4) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 7 (7) I Chip initialization VDD / VSS VDD / VSS 30/1 (32/1) I Logic power supply pin. VDD should be tied to +5 V during programming. NOTE: Parentheses indicate pin numbers of 32 SDIP package. 15–5 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 Table 15-3. Comparison of S3P7528 and S3C7528 Features Characteristic S3P7528 S3C7528 Program Memory 8 K byte EPROM 8 K byte mask ROM Operating Voltage (VDD) 2.0 V to 5.5 V 2.0 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 42 SDIP / 44 QFP 42 SDIP / 44 QFP EPROM Programmability User Program 1 time Programmed at the factory – Table 15-4. Comparison of S3P7538 and S3C7538 Features Characteristic S3P7538 S3C7538 Program Memory 8 K byte EPROM 8 K byte mask ROM Operating Voltage (VDD) 2.0 V to 5.5 V 2.0 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 30 SOP / 32 SOP 30 SOP / 32 SOP EPROM Programmability User Program 1 time Programmed at the factory – OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7528, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-5. Operating Mode Selection Criteria VDD Vpp (TEST) REG/ MEM Address (A15-A0) R/W W 5V 5V 0 0000H 1 EPROM read 12.5V 0 0000H 0 EPROM program 12.5V 0 0000H 1 EPROM verify 12.5V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 15–6 Mode S3C7524/C7528/P7528/C7534/C7538/P7538 S3P7528/P7538 OTP START Address= First Location VDD =5V, V PP=12.5V x=0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte Last Address FAIL NO Increment Address VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 15-5. OTP Programming Algorithm 15–7 S3P7528/P7538 OTP S3C7524/C7528/P7528/C7534/C7538/P7538 NOTES 15–8