S3C9004/P9004/C9014/P9014 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM87RI PRODUCT FAMILY Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RI microcontrollers have an external interface that provides access to external memory and other peripheral devices. S3C9004/P9004/C9014/P9014 MICROCONTROLLER The S3C9004/P9004/C9014/P9014 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87RI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9004/P9004/C9014/P9014 has 4 K bytes of program memory on-chip. Using the SAM87RI design approach, the following peripherals were integrated with the SAM87RI core: — Five configurable I/O ports (32 pins) — 12 bit-programmable pins for external interrupts — 8-bit timer/counter with three operating modes The S3C9004/P9004/C9014/P9014 is a versatile microcontroller that can be used in a wide range of general purpose applications. It is especially suitable for use as a keyboard controller and is available in a 40-pin DIP and a 44-pin QFP package. OTP The S3C9004/C9014 microcontroller is also available in OTP (One Time Programmable) version, S3P9004/P9014. S3P9004/P9014 microcontroller has an on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P9004/P9014 is comparable to S3C9004/C9014, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014 FEATURES CPU • SAM87RI CPU core Memory • 4-Kbyte internal program memory (ROM) • 208-byte internal register file • 8-Kbyte external program memory • 8-Kbyte external data memory Instruction Set • 41 instructions • IDLE and STOP instructions added for powerdown modes Instruction Execution Time • 1.5 µs at 4 MHz fOSC Interrupts • 14 interrupt sources with one vector, Each source has its pending bit • One level, one vector interrupt structure Oscillation Circuit Options • 4 MHz RC oscillator with on chip capacitor for S3C9004/P9004 ( –10% RC accuracy at VDD ± 5% and Ta = 0°C–70°C, using 1% external precision resistor) • RC oscillator for S3C9004/P9004 • Crystal/ceramic oscillator for S3C9014/P9014 1-2 General I/O • Five ports (32 pins total) • Three bit-programmable ports (20 pins total) • Two bit-programmable ports with external interrupts (12 pins total) Timer/Counter • One 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function • One 8-bit timer/counter with PWM mode Operating Temperature Range • – 40°C to + 85°C Operating Voltage Range • 4.5 V to 5.5 V for S3C9004/P9004 • 2.7 V to 5.5 V for S3C9014/P9014 Package Types • 40-pin DIP S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW BLOCK DIAGRAM RESET VDD VSS1 XIN XOUT MAIN OSC P0.0-P0.4/A8-A12, P0.5-P0.7 P1.0-P1.7/ AD0-AD7 PORT PORT P2.0-P2.7/INT, AS, DS , R/ W, DM PORT EA (TEST) SAM87RI BUS I/O PORT AND INTERRUPT CONTROL VDD VSS1 PORT P3.0 P3.1 P3.2 P3.3/CLO PORT P4.0/INT P4.1/INT/T0CLK P4.2/INT P4.3/INT/T0OUT Basic Timer SAM87RI CPU Timer 0 4-KB ROM 208-BYTE REGISTER FILE Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014 PIN ASSIGNMENTS 40 P3.1 INT/P4.0 2 39 P3.2 T0CLK/INT/P4.1 3 38 P3.3/CLO INT/P4.2 4 37 VDD T0OUT/INT/P4.3 5 36 P0.0/A8 6 35 P0.1/A9 34 P0.2/A10 33 P0.3/A11 32 P0.4/A12 31 P0.5 30 P0.6 29 28 P0.7 XOUT 14 27 XIN 15 26 AS/INT/P2.0 DS /INT/P2.1 7 R/ W/INT/P2.4 8 DM /INT/P2.3 9 INT/P2.4 10 INT/P2.5 11 INT/P2.6 12 INT/P2.7 13 NC VSS1 AD7/P1.7 16 AD6/P1.6 17 S3C9004/P9004 S3C9014/P9014 1 P3.0 40-DIP 25 (Top View) RESET VSS2 24 EA P1.0/AD0 AD5/P1.5 18 23 AD4/P1.4 19 22 P1.1/AD1 20 21 P1.2/AD2 AD3/P1.3 Figure 1-2. Pin Assignment Diagram (40-Pin DIP Package) 1-4 S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C9004/P9004/C9014/P9014 Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0-P0.7 I/O Bit-programmable I/O port for Schmitt trigger input or open-drain output. Port0 can also be configured as external interface address lines A8A12. C 36-29 A8-A12 P1.0-P1.7 I/O Bit-programmable I/O port for Schmitt trigger input, push-pull, or open-drain output. Port1 can alternatively be used as external interface address/data lines AD0-AD7. C 23-16 AD0-AD7 P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Port2 can be individually configured as external interrupt inputs. Especially, P2.0-2.3 can be configured for external bus control signal. D 6-13 INT, AS, DS, R/W, DM P3.0-P3.3 I/O Same general characteristics as Port1. Port3 are designed for to drive LED directly. P3.3 can be used to system clock output (CLO) port. C 1, 40-38 P3.3/CLO P4.0-P4.3 I/O Bit-programmable I/O port. Input mode or nchannel open-drain output mode is software assignable. Port4 can be individually configured as external interrupt inputs. Pull-up resistors are also software assignable. Especially, P4.1 can be used T0CLK input and P4.3 also T0OUT for Timer 0. D 2-5 INT, T0CLK, T0OUT XIN, XOUT – System clock input and output pin (for RC oscillator, crystal/ceramic oscillator, or external clock source) – 27, 28 – INT I External interrupt for bit-programmable port2 and port4 pins when set to input mode. – 2-13 PORT2/ PORT4 RESET I RESET signal input pin. Schmitt trigger input with internal pull-up resistor. A 26 – EA I External Memory Access (EA) pin with 2 modes: 0V = Normal Operation Mode 5V = ROMLESS Operation Mode (Must be connected to VSS during normal operation mode) B 24 – VDD – Power input pin – 37 – VSS1, VSS2 – Vss1 is a ground power for CPU core. Vss2 is a ground power for I/O and OSC block – 15, 25 – NC – No connection (This pin would be better connecting to VSS) – 14 – 1-5 PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014 PIN CIRCUITS Table 1-2. Pin Circuit Assignments for the S3C9004/P9004/C9014/P9014 Circuit Number Circuit Type S3C9004/P9004/C9014/P9014 Assignments A I RESET signal input B I EA input C I/O Ports 0, 1, and 3 D I/O Ports 2 and 4 VDD IN PULL-UP RESISTOR IN 0 V = Internal ROM Access 5 V = External ROM Access Noise Filter Figure 1-3. Pin Circuit Type A (RESET RESET) Figure 1-4. Pin Circuit Type B (EA) VDD OUTPUT DATA OPEN DRAIN I/O OUTPUT DISABLE VSS INPUT DATA MUX D0 D1 MODE INPUT DATA OUTPUT D0 INPUT D1 Figure 1-5. Pin Circuit Type C (Ports 0, 1, and 3) 1-6 S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW VDD PULL-UP RESISTOR PULL-UP ENABLE VDD OUTPUT DATA OPEN DRAIN I/O OUTPUT DISABLE VSS INPUT DATA MUX D0 D1 MODE INPUT DATA OUTPUT D0 INPUT D1 Figure 1-6. Pin Circuit Type D (Ports 2 and 4) 1-7 PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014 APPLICATION CIRCUIT 5V 5V VDD PORT 3 0 PORT 0 1 2 PORT 1 3 EA 15 XIN R OSC S3C9004 S3P9004 0 XOUT 1 2 PORT 2 RESET CLK DATA 7 PORT 4 H O S T 3 VSS1 VSS2 KEYBOARD MATRIX Figure 1-7. Keyboard Control Application Circuit Diagram 1-8 S3C9004/P9004/C9014/P9014 12 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9004/P9004/C9014/P9014 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — I/O capacitance — A.C. electrical characteristics — Input timing for RESET — Input timing for external interrupts (ports 2 and 4, RESET, and EA) — Oscillator characteristics — Oscillation stabilization time — Clock timing measurement points at XIN — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a reset — Stop mode release timing when initiated by an external interrupt — External Memory timing characteristics (8 MHz) — External Memory Read and Write timing — Characteristic curves 12-1 ELECTRICAL DATA S3C9004/P9004/C9014/P9014 Table 12-1. Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Conditions Rating Unit Supply Voltage VDD – – 0.3 to + 6.5 V Input Voltage VIN All input ports – 0.3 to VDD + 0.3 V Output Voltage VO All output ports – 0.3 to VDD + 0.3 V Output Current I OH One I/O pin active – 18 mA All I/O pins active – 60 One I/O pin active + 25 Total pin current for ports 3 + 100 Total pin current for ports 0, 1, 2, 4 + 100 High Output Current Low I OL mA Operating Temperature TA – – 40 to + 85 °C Storage Temperature TSTG – – 65 to + 150 °C Table 12-2. D.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V (1)) Parameter Symbol Conditions Min Typ Max Unit 0.8 VDD – VDD V VIH1 All inputs except VIH2 VIH2 XIN VIL1 All inputs except VIL2 VIL2 XIN Output High Voltage VOH IOH = – 200 µA All outputs except P4.1, P4.3, and port0 VDD – 1.0 – – V Output Low Voltage VOL IOL = 2 mA All outputs except port3 – – 0.4 V Output Low Current IOL VOL= 3 V Port3 only 8 15 23 mA Input High Leakage Current ILIH1 VIN = VDD All inputs except ILIH2, P4.0 and P4.1 – – 3 µA ILIH2 VIN = VDD XIN, XOUT Input High Voltage Input Low Voltage 12-2 VDD – 0.5 VDD – 0.2 VDD V 0.4 20 S3C9004/P9004/C9014/P9014 ELECTRICAL DATA Table 12-2. D.C. Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V (1)) Parameter Symbol Conditions Min Typ Max Unit ILIL1 VIN = 0 V All inputs except ILIL2, P4.0 and P4.1 – – –3 µA ILIL2 VIN = 0 V XOUT, XIN Output High Leakage Current ILOH VOUT = VDD All outputs – – 3 µA Output Low Leakage Current ILOL VOUT = 0 V All outputs – – –3 µA Pull-up Resistors RL1 VIN = 0 V; Port 2 only 30 60 90 KΩ RL2 VIN = 0 V; Port 4 only 1.8 2.8 4.0 RL3 VIN = 0 V; RESET only 50 90 150 IDD1 Normal operation mode 4 MHz CPU clock – 4.5 10 mA IDD2 Idle mode; 4 MHz oscillator 0.9 3 mA IDD3 Stop mode 0.5 5 µA Input Low Leakage Current Supply Current (2) – 20 NOTES: 1. The operating voltage range of S3C9014/P9014 is from 2.7 V to 5.5 V according to oscillation frequency. 2. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 12-3 S3C9004/P9004/C9014/P9014 ELECTRICAL DATA Table 12-3. Input/Output Capacitance (TA = – 40°C to + 85°C, VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS – – 10 pF Output Capacitance COUT Min Typ Max Unit P2 and P4 – 200 – ns RESET – 1,000 – CIO I/O Capacitance Table 12-4. A.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V) Parameter Interrupt Input High, Low Width Symbol tINTH, tINTL RESET Input Low Width tRSL Conditions t RSL RESET 0.2 V DD Figure 12-1. Input Timing for RESET 12-5 ELECTRICAL DATA S3C9004/P9004/C9014/P9014 tINTL tINTH 0.8 VDD 0.2 VDD Figure 12-2. Input Timing Measurement Points for Port 2, Port 4, and RESET Table 12-5. Oscillator Characteristics (TA = – 40°C + 85°C, VDD = 4.5 V to 5.5 V) Oscillator RC Oscillator (with Internal Capacitor; for S3C9004/P9004) Clock Circuit XIN R Test Condition Min Typ Max Unit VDD = 4.75 to 5.25 V – 4 – MHz Crystal/Ceramic oscillation frequency 1.0 – 8.0 TA = 0°C + 70°C Tolerance: ± 10% (note) XOUT Crystal/Ceramic Oscillator (for S3C9014/P9014) XIN C1 C2 XOUT NOTE: The S3C9004/P9004 provides an internal capacitor to accommodate an RC oscillator configuration. A 1% precision resistor must be used to achieve an oscillation frequency with an acceptable tolerance. 12-6 S3C9004/P9004/C9014/P9014 ELECTRICAL DATA CPU CLOCK 8 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 3.5 4 5 5.5 6 7 SUPPLY VOLTAGE (V) Figure 12-3. Operating Voltage Range (S3C9014/P9014) 12-7 S3C9004/P9004/C9014/P9014 ELECTRICAL DATA Table 12-6. Oscillation Stabilization Time (TA = – 40°C + 85°C, VDD = 4.5 V to 5.5 V) Oscillator Main Crystal Main Ceramic Oscillator Stabilization Wait Time Test Condition Min Typ Max Unit f OSC = 4 MHz (Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.) – – 10 ms tWAIT stop mode release time by a reset – 216 / f OSC – tWAIT stop mode release time by an interrupt – (note) – NOTE: The oscillator stabilization wait time, tWAIT, is determined by the setting in the basic timer control register, BTCON. 1 / f OSC t XL t XH XIN VDD – 0.5 V 0.4 V Figure 12-4. Clock Timing Measurement Points at XIN Table 12-7. Data Retention Supply Voltage in Stop Mode (TA = – 40°C + 85°C) Parameter Symbol Conditions Data Retention Supply Voltage VDDDR Stop mode Data Retention Supply Current IDDDR Stop mode; VDDDR = 2.0 V Min Typ Max Unit 2.0 – 6 V – – 5 µA 12-9 ELECTRICAL DATA S3C9004/P9004/C9014/P9014 ~~ VDD STOP MODE ~~ INTERNAL RESET OPERATION DATA RETENTION MODE IDLE MODE (BASIC TIMER ACTIVE) NORMAL OPERATING MODE VDDDR EXECUTION OF STOP INSTRUCTION RESET 0.2 V DD 0.8 V DD t WAIT VDD ~ ~ ~ ~ Figure 12-5. Stop Mode Release Timing When Initiated by a Reset IDLE MODE (BASIC TIMER ACTIVE) STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE VDDDR EXECUTION OF STOP INSTRUCTION EXTERNAL INTERRUPT 0.2 V DD 0.8 V DD t WAIT Figure 12-6. Stop Mode Release Timing When Initiated by an External Interrupt 12-10 S3C9004/P9004/C9014/P9014 ELECTRICAL DATA Table 12-8. External Memory Timing Characteristics (4 MHz) (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V) Number Symbol Parameter Normal Timing (ns) Min Max 1 tdA (AS) Address valid to AS ↑ delay 10 – 2 tdAS (A) AS ↑ to address float delay 35 – 3 tdAS (DR) AS ↑ to read data required valid – 140 4 twAS AS Low width 88 – 5 tdA (DS) Address float to DS ↓ 0 – 6a twDS (read) DS (read) Low width 314 – 6b twDS (write) DS (write) Low width 164 – 7 tdDS (DR) DS ↓ to read data required valid – 80 8 thDS (DR) Read data to DS ↑ hold time 0 – 9 tdDS (A) DS ↑ to address active delay 20 – 10 tdDS (AS) DS ↑ to AS ↓ delay 30 – 11 tdDO (DS) Write data valid to DS (write) ↓ delay 10 – 12 tdRW (AS) R/W valid to AS ↑ delay 20 – 13 tdDS (DW) DS ↑ to write data not valid delay 20 – NOTES: 1. All times are in nano seconds (ns) and assume an 4 MHz input frequency. 2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7. 12-11 ELECTRICAL DATA S3C9004/P9004/C9014/P9014 R/ W (P2.2) 12 PORT0 DM (P2.3) A8−A12, DM 3 A0−A7 PORT1 1 AS (P2.0) 9 D0−D7 OUT 2 D0−D7 IN 11 OUT 10 5 8 4 7 DS (P2.1) 6 Figure 12-7. External Memory Read and Write Timing (See Table 12-8 for a description of each timing point.) 12-12 13 S3C9004/P9004/C9014/P9014 ELECTRICAL DATA CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. (TA = 25 C) 7 f OSC = 10 MHz 6 f OSC = 8 MHz 5 3 f OSC = 2 MHz 2 f OSC = 1 MHz 1 0 ~ ~ I DD1 (mA) f OSC = 5 MHz 4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) Figure 12-8. IDD1 vs. VDD 12-13 ELECTRICAL DATA S3C9004/P9004/C9014/P9014 (TA = 25 C) f OSC f OSC f OSC f OSC 1400 1200 1000 800 I DD2 (µA) 600 400 0 ~ ~ 200 2.5 3.0 3.5 4.0 4.5 VDD (V) Figure 12-9. IDD2 vs. VDD 12-14 5.0 5.5 6.0 = 10 MHz = 5,8 MHz = 1 MHz = 2 MHz S3C9004/P9004/C9014/P9014 ELECTRICAL DATA (TA = 25 C) 750 700 650 600 I DD3 (nA) 550 f OSC = 5 MHz 500 450 ~ ~ 400 0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 6.0 VDD (V) Figure 12-10. IDD3 vs. VDD 6 5 4 VOH (V) 3 VDD = 4.5V 2 VDD = 5.0V VDD = 5.5V 1 0 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 IOH (mA) Figure 12-11. IOH vs. VOH 12-15 ELECTRICAL DATA S3C9004/P9004/C9014/P9014 7 6 5 VOL (V) 4 3 VDD = 4.5V VDD = 5.0V VDD = 5.5V 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 IOL (mA) Figure 12-12. VOL vs. IOL (Port 0, 1, 2, and 4) 7 6 5 VOL (V) 4 VDD = 4.5V VDD = 5.0V 3 2 VDD = 5.5V 1 0 1 2 3 4 5 6 7 8 9 10 11 IOL (mA) Figure 12-13. VOL vs. IOL (Port 3) 12-16 12 13 14 15 16 17 S3C9004/P9004/C9014/P9014 13 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9004/P9004/C9014/P9014 is currently available in a 40-pin DIP package. #21 +0.1 – 0.05 0.25 40-DIP-600B 0.46 ± 0.1 1.27 ± 0.1 2.54 5.08MAX 52.42 ± 0.2 3.30 ± 0.3 52.82 MAX 3.95 ± 0.2 #20 0.51MIN #1 (2.00) 0-15 ° 15.24 13.85 ± 0.2 #40 NOTE: Dimensions are in millimeters. Figure 13-1. 40-Pin DIP Package Mechanical Data (40-DIP-600B) 13-1 MECHANICAL DATA S3C9004/P9004/C9014/P9014 NOTES 13-2