S3C9442/C9444/F9444/C9452/C9454/F9454 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. S3C9442/C9444/C9452/C9454 MICROCONTROLLER The S3C9442/C9444/C9452/C9454 single-chip 8-bit microcontroller is designed for useful A/D converter , SIO application field. The S3C9442/C9444/C9452/C9454 uses powerful SAM88RCRI CPU and S3C9442/C9444/C9452/C9454 architecture. The internal register file is logically expanded to increase the onchip register space. The S3C9442/C9444/C9452/C9454 has 2K/4K bytes of on-chip program ROM and 208 bytes of RAM. The S3C9442/C9444/C9452/C9454 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, PWM. In addition, the S3C9442/C9444/C9452/C9454’s advanced CMOS technology provides for low power consumption and wide operating voltage range. Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: — Three configurable I/O ports (18 pins) — Four interrupt sources with one vector and one interrupt level — One 8-bit timer/counter with time interval mode — Analog to digital converter with nine input channels and 10-bit resolution — One 8-bit PWM output The S3C9442/C9444/C9452/C9454 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC. S3C9452/C9454 is available in a 20/16-pin DIP and a 20-pin SOP package. S3C9452/C9454 is available in a 8-pin and a 8-pin SOP package. MTP The S3F9444/F9454 is an MTP (Multi Time Programmable) version of the S3C9442/C9444/C9452/C9454 microcontroller. The S3F9444/F9454 has on-chip 4-Kbyte multi-time programmable flash ROM instead of masked ROM. The S3F9444/F9454 is fully compatible with the S3C9442/C9444/C9452/C9454, in function, in D.C. electrical characteristics and in pin configuration. 1-1 PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 FEATURES CPU Timer/Counters • SAM88RCRI CPU core • One 8-bit basic timer for watchdog function • The SAM88RCRI core is low-end version of the current SAM87 core. • One 8-bit timer/counter with time interval modes A/D Converter Memory • 2/4-Kbyte internal program memory • 208-byte general purpose register area • Nine analog input pins • 10-bit conversion resolution Oscillation Frequency Instruction Set • 41 instructions • The SAM88RCRI core provides all the SAM87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. • 1 MHz to 10 MHz external crystal oscillator • Maximum 10 MHz CPU clock • Internal RC: 3.2 MHz (typ.), 0.5 MHz (typ.) in VDD = 5 V Operating Temperature Range Instruction Execution Time • • – 40°C to + 85°C 400 ns at 10 MHz fOSC (minimum) Operating Voltage Range Interrupts • 4 interrupt sources with one vector • One interrupt level General I/O • Three I/O ports (Max 18 pins) • Bit programmable ports 8-bit High-speed PWM • 8-bit PWM 1-ch (Max: 156 kHz) • 6-bit base + 2-bit extension Built-in reset Circuit • 1-2 Low voltage detector for safe reset • 2.0 V (LVR Level) to 5.5 V Smart Option Package Types • S3C9452/C9454: – 20-DIP-300A – 20-SOP-375 – 16-DIP-300A • S3C9442/C9444 – 8-DIP-300 – 8-SOP-225 S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW BLOCK DIAGRAM XIN XOUT OSC Port 0 P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 ... Port I/O and Interrupt Control P0.7/ADC7 Basic Timer P1.0 Timer 0 Port 1 88RCRI SAMRI CPU ADC0-ADC8 P1.1 P1.2 ADC P2.0/T0 PWM NOTE: 208 Byte Register file Port 2 P2.1 ... P0.6/PWM 2 KB ROM 4 KB ROM P2.6 P1.2 is used as input only Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 PIN ASSIGNMENTS VSS 1 20 VDD XIN/P1.0 2 19 P0.0/ADC0/INT0 XOUT/P1.1 3 18 P0.1/ADC1/INT1 RESET/P1.2 4 17 P0.2/ADC2 P2.0/T0 5 16 P0.3/ADC3 P2.1 6 15 P0.4/ADC4 P2.2 7 14 P0.5/ADC5 P2.3 8 13 P0.6/ADC6/PWM P2.4 9 12 P0.7/ADC7 P2.5 10 11 P2.6/ADC8/CLO S3C9452/C9454 (20-DIP-300A/ 20-SOP-375) Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP Package) 1-4 S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW VSS 1 16 VDD XIN/P1.0 2 15 P0.0/ADC0/INT0 XOUT/P1.1 3 14 P0.1/ADC1/INT1 RESET/P1.2 4 S3C9452/C9454 13 P0.2/ADC2 P2.0/T0 5 (16-DIP-300A) 12 P0.3/ADC3 P2.1 6 11 P0.4/ADC4 P2.2 7 10 P0.5/ADC5 P2.3 8 9 P0.6/ADC6/PWM Figure 1-3. Pin Assignment Diagram (16-Pin DIP Package) VSS 1 XIN/P1.0 2 XOUT/P1.1 3 RESET/P1.2 4 S3C9442/C9444 (8-DIP-300 8-SOP-225) 8 VDD 7 P0.0/ADC0/INT0 6 P0.1/ADC1/INT1 5 P0.2/ADC2 Figure 1-4. Pin Assignment Diagram (8-Pin DIP/SOP Package) 1-5 PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 PIN DESCRIPTIONS Table 1-1. S3C9452/C9454 Pin Descriptions Pin Name In/Out Pin Description Pin Type Share Pins P0.0–P0.7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port0 pins can also be used as A/D converter input, PWM output or external interrupt input. E-1 ADC0–ADC7 INT0/INT1 PWM P1.0–P1.1 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors or pull-down resistors are assignable by software. E-2 XIN, XOUT Schmitt trigger input port B RESET Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assignable by software. E – ADC8/CLO T0 P1.2 P2.0–P2.6 I I/O E-1 XIN, XOUT – Crystal/Ceramic, or RC oscillator signal for system clock. RESET I Internal LVR or External RESET VDD, VSS – Voltage input pin and ground CLO O System clock output port E-1 P2.6 INT0–INT1 I External interrupt input port E-1 P0.0, P0.1 PWM O 8-Bit high speed PWM output E-1 P0.6 T0 O Timer0 match output E-1 P2.0 ADC0–ADC8 I A/D converter input E-1 E P0.0–P0.7 P2.6 1-6 P1.0–P1.1 B P1.2 – S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW PIN CIRCUITS VDD P-channel IN IN N-channel Figure 1-5. Pin Circuit Type A Figure 1-6. Pin Circuit Type B VDD VDD Pull-up Enable Data Out Output DIsable Data Output Disable Circuit Type C I/O Digital Input Figure 1-7. Pin Circuit Type C Figure 1-8. Pin Circuit Type D 1-7 PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 VDD Open-drain Enable P2CONH P2CONL Pull-up enable VDD P-CH Alternative Output M U X P2.x Data I/O N-CH Output Disable (Input Mode) Digital Input Analog Input Enable ADC Figure 1-9. Pin Circuit Type E VDD P0CONH Alternative Output P0.x P-CH M U X Data I/O N-CH Output Disable (Input Mode) Digital Input Interrupt Input Analog Input Enable ADC Figure 1-10. Pin Circuit Type E-1 1-8 Pull-up enable VDD S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW VDD Open-drain Enable Pull-up enable VDD P1.x I/O Output Disable (Input Mode) Pull-down enable Digital Input XIN XOUT Figure 1-11. Pin Circuit Type E-2 1-9 S3C9442/C9444/F9444/C9452/C9454/F9454 13 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9442/C9444/C9452/C9454 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Input Timing Measurement Points — Oscillator characteristics — Oscillation stabilization time — Operating Voltage Range — Schmitt trigger input characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a RESET — A/D converter electrical characteristics — LVR circuit characteristics — LVR reset Timing 13-1 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 Table 13-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Symbol Conditions Rating Unit VDD – – 0.3 to + 6.5 V Input voltage VI All ports – 0.3 to VDD + 0.3 V Output voltage VO All output ports – 0.3 to VDD + 0.3 V Output current high IOH One I/O pin active – 25 mA All I/O pins active – 80 One I/O pin active + 30 All I/O pins active + 150 Output current low Operating temperature Storage temperature 13-2 IOL mA TA – – 40 to + 85 °C TSTG – – 65 to + 150 °C S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-2. DC Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Input high voltage Input low voltage Symbol VIH1 Conditions Ports 0, 1, 2 and VDD= 2.0 to 5.5 V Min Typ Max Unit 0.8 VDD – VDD V – 0.2 VDD V RESET VIH2 XIN and XOUT VIL1 Ports 0, 1, 2 and VDD- 0.1 VDD= 2.0 to 5.5 V – RESET VIL2 XIN and XOUT Output high voltage VOH VDD= 4.5 to 5.5 V VDD-1.5 VDD- 0.4 – V Output low voltage VOL VDD= 4.5 to 5.5 V – 0.4 2.0 V Input high leakage current ILIH1 IOH = – 10 mA ports 0, 1, 2 IOL = 25 mA port 0, 1, and 2 All input except ILIH2 VIN = VDD – – 1 uA ILIH2 XIN, XOUT VIN = VDD ILIL1 All input except ILIL2 and RESET VIN = 0 V ILIL2 XIN, XOUT VIN = 0 V Output high leakage current ILOH All output pins VOUT = VDD – – 2 uA Output low leakage current ILOL All output pins VOUT = 0 V – – –2 uA Pull-up resistors RP VDD = 5 V 25 50 100 kΩ Pull-down resistors RP VIN = 0 V Ports 0, 1, 2 VIN = 0 V Ports 1 Run mode 10 MHz CPU clock 3 MHz CPU clock VDD = 5 V 25 50 100 – 5 10 2 5 Idle mode 10 MHz CPU clock 3 MHz CPU clock VDD = 4.5 to 5.5 V 2 4 0.5 1.5 Stop mode VDD = 4.5 to 5.5 V (LVR disable) 0.1 5 VDD = 4.5 to 5.5 V (LVR enable) 100 200 VDD = 2.6 V (LVR enable) 30 60 Input low leakage current Supply current IDD1 IDD2 IDD3 0.1 VDD = 4.5 to 5.5 V 20 – – –1 uA –20 VDD = 2.0 V – VDD = 2.0 V – mA uA NOTE: In STOP (IDD3), IDLE (IDD2) current, current by ADC module is not included. 13-3 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 Table 13-3. AC Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input low width tINTL INT0, INT1 VDD = 5 V ± 10 % – 200 – ns RESET input tRSL Input VDD = 5 V ± 10 % – 1 – us low width tINTL XIN tINTH 0.8 VDD 0.2 VDD Figure 13-1. Input Timing Measurement Points 13-4 S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-4. Oscillator Characteristics (TA = – 40°C to + 85°C) Oscillator Main crystal or ceramic Clock Circuit C1 XIN C2 XOUT External clock (Main System) XIN Test Condition Min Typ Max Unit VDD = 4.5 to 5.5 V 1 – 10 MHz VDD = 2.7 to 4.5 V 1 – 6 MHz VDD = 2.0 to 2.7 V 1 – 3 MHz VDD = 4.5 to 5.5 V 1 – 10 MHz VDD = 2.7 to 4.5 V 1 – 6 MHz VDD = 2.0 to 2.7 V 1 – 3 MHz VDD = 4.75 to 5.25 V Tolerance:10 % – 4 – MHz XOUT External RC oscillator – VDD = 4.75 to 5.25 V Internal RC 3.2 Oscillator 0.5 Table 13-5. Oscillation Stabilization Time (TA = - 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Main crystal f OSC > 1.0 MHz – – 20 ms Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 10 ms External clock (main system) XIN input high and low width (tXH, tXL) 25 – 500 ns Oscillator stabilization tWAIT when released by a reset (1) – 216/fOSC – ms wait time tWAIT when released by an interrupt (2) – – – ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON. 13-5 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 CPU Clock 10 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 4 4.5 5 5.5 6 7 Supply Voltage (V) Figure 13-2. Operating Voltage Range VOUT VDD A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B 0.3 VDD C D VIN 0.7 VDD Figure 13-3. Schmitt Trigger Input Characteristics Diagram 13-6 S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-6. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Conditions Data retention supply voltage VDDDR Stop mode Data retention supply current IDDDR Stop mode; VDDDR = 2.0 V Min Typ Max Unit 2.0 – 5.5 V – 0.1 5 uA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. ~ ~ Stop Mode RESET Occurs Oscillation Stabilization Time Data Retention Mode RESET ~ ~ VDD Execution Of Stop Instrction Normal Operating Mode VDDDR tWAIT NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC Figure 13-4. Stop Mode Release Timing When Initiated by a RESET 13-7 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 Table 13-7. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions VDD = 5.12 V CPU clock = 10 MHz VSS = 0 V Min Typ Max Unit – – ±3 LSB Total accuracy – Integral linearity error ILE ″ – – ±2 Differential linearity error DLE ″ – – ±1 Offset error of top EOT ″ – ±1 ±3 Offset error of bottom EOB ″ – ±1 ±2 Conversion time (1) tCON f OSC = 10 MHz – 20 – µs Analog input voltage VIAN – VSS – VDD V Analog input impedance RAN – 2 – – MΩ Analog input current IADIN VDD = 5 V – – 10 µA Analog block current (2) IADC VDD = 5 V – 1 3 mA 0.5 1.5 100 500 VDD = 3 V VDD = 5 V power down mode – NOTES: 1. “Conversion time” is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 13-8 nA S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-8. LVR Circuit Characteristics (TA = 25 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Low voltage reset VLVR – – 2.3 3.0 3.9 LVR hysteresis voltage VHYS – 0.3 Power supply voltage rise time tR 10 Power supply voltage off time tOFF 0.5 Max Unit V – V (note) us s NOTE: 216/fx ( = 6.55 ms at fx = 10 MHz) tOFF tR VDD VLVR,MAX VHYS VLVR VHYS VLVR,MIN Figure 13-5. LVR Reset Timing 13-9 S3C9442/C9444/F9444/C9452/C9454/F9454 14 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9452/C9454 is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung: 20-SOP-375), a 16-pin DIP package (Samsung: 16-DIP-300A). Package dimensions are shown in Figure 15-1, 15-2, and 15-3. The S3C9442/C9444 is available in a 8-pin DIP package (SAMSUNG 8-DIP-300A), a 8-pin SOP package (SAMSUNG 8-SOP-225). Package dimensions are shown in figure 14-4 and 14-5. #11 0-15 0.2 5 20-DIP-300A +0 - 0 .10 .05 7.62 6.40 ± 0.20 #20 0.46 ± 0.10 (1.77) NOTE: 1.52 ± 0.10 2.54 5.08 MAX 26.40 ± 0.20 3.30 ± 0.30 26.80 MAX 3.25 ± 0.20 #10 0.51 MIN #1 Dimensions are in millimeters. Figure 14-1. 20-DIP-300A Package Dimensions 14-1 MECHANICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 0-8 #10 0.203 2.30 ± 0.10 #1 13.14 MAX 12.74 ± 0.20 + 0.10 - 0.05 1.27 (0.66) 0.40 NOTE: + 0.10 - 0.05 0.05 MIN 0.10 MAX Dimensions are in millimeters. Figure 14-2. 20-SOP-375 Package Dimensions 14-2 0.85 ± 0.20 20-SOP-375 9.53 7.50 ± 0.20 #11 2.50 MAX 10.30 ± 0.30 #20 S3C9442/C9444/F9444/C9452/C9454/F9454 MECHANICAL DATA #9 0-15 0.2 5 16-DIP-300A +0 - 0 .10 .05 7.62 6.40 ± 0.20 #16 0.46 ± 0.10 (0.81) NOTE: 1.50 ± 0.10 2.54 5.08 MAX 19.40 ± 0.20 3.30 ± 0.30 19.80 MAX 3.25 ± 0.20 #8 0.38 MIN #1 Dimensions are in millimeters. Figure 14-3. 16-DIP-300A Package Dimensions 14-3 MECHANICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 #5 0.2 5 8-DIP-300 +0 - 0 .10 .05 0-15 7.62 6.40 ± 0.20 #8 2.54 (0.79) 0.46 ± 0.10 5.08 MAX 9.20 ± 0.20 3.30 ± 0.30 9.60 MAX 3.40 ± 0.20 #4 0.33 MIN #1 1.52 ± 0.10 NOTE: Dimensions are in millimeters. Figure 14-4. 8-DIP-300 Package Dimensions 14-4 S3C9442/C9444/F9444/C9452/C9454/F9454 MECHANICAL DATA 0-8 #4 0.15 5.13 MAX 4.92 ± 0.20 + 0.10 - 0.05 1.80 MAX #1 0.50 ± 0.20 8-SOP-225 5.72 3.95 ± 0.20 #5 1.55 ± 0.20 6.00 ± 0.30 #8 1.27 (0.56) 0.41 ± 0.10 NOTE: 0.1-0.25 MIN 0.10 MAX Dimensions are in millimeters. Figure 14-5. 8-SOP-225 Package Dimensions 14-5 S3C9442/C9444/F9444/C9452/C9454/F9454 15 S3F9444/F9454 MTP S3F9444/F9454 MTP OVERVIEW The S3F9444/F9454 single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the S3C9442/C9444/C9452/C9454 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F9444/F9454 is fully compatible with the S3C9442/C9444/C9452/C9454, in function, in D.C. electrical characteristics, and in pin configuration. Because of its simple programming requirements, the S3F9444/F9454 is ideal for use as an evaluation chip for the S3C9442/C9444/C9452/C9454. VSS/VSS 1 20 VDD/VDD XIN/P1.0 2 19 P0.0/ADC0/INT0/SCL XOUT/P1.1 3 18 P0.1/ADC1/INT1/SDA VPP/RESET/P1.2 4 17 P0.2/ADC2 T0/P2.0 5 16 P0.3/ADC3 P2.1 6 15 P0.4/ADC4 P2.2 7 14 P0.5/ADC5 P2.3 8 13 P0.6/ADC6/PWM P2.4 9 12 P0.7/ADC7 P2.5 10 11 P2.6/ADC8/CLO NOTE: S3F9454 The bolds indicate MTP pin name. Figure 15-1. Pin Assignment Diagram (20-Pin Package) 15-1 S3F9444/F9454 MTP S3C9442/C9444/F9444/C9452/C9454/F9454 VSS/VSS 1 16 VDD/VDD XIN/P1.0 2 15 P0.0/ADC0/INT0/SCL XOUT/P1.1 3 14 P0.1/ADC1/INT1/SDA VPP/RESET/P1.2 4 13 P0.2/ADC2 T0/P2.0 5 12 P0.3/ADC3 P2.1 6 11 P0.4/ADC4 P2.2 7 10 P0.5/ADC5 P2.3 8 9 NOTE: S3F9454 P0.6/ADC6/PWM The bolds indicate MTP pin name. Figure 15-2. Pin Assignment Diagram (16-Pin Package) 8 VDD/VDD 7 P0.0/ADC0/INT0/SCL 3 6 P0.1/ADC1/INT1/SDA 4 5 P0.2/ADC2 VSS/VSS 1 XIN/P1.0 2 XOUT/P1.1 VPP/RESET/P1.2 NOTE: S3F9444 The bolds indicate MTP pin name. Figure 15-3. Pin Assignment Diagram (8-Pin Package) 15-2 S3C9442/C9444/F9444/C9452/C9454/F9454 S3F9444/F9454 MTP Table 15-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned P0.1 SDA 18 (20-pin) 14 (16-pin) I/O P0.0 SCL 19 (20-pin) 15 (16-pin) I Serial clock pin (input only pin) RESET, P1.2 VPP 4 I Power supply pin for flash ROM cell writing (indicates that MTP enters into the writing mode). When 12.5 V is applied, MTP is in writing mode and when 5 V is applied, MTP is in reading mode. (Option) 20 (20-pin), 16 (16-pin) 1 (20-pin), 1 (16-pin) I Logic power supply pin. VDD/VSS VDD/VSS Table 15-2. Comparison of S3F9444/F9454 and S3C9442/C9444/C9452/C9454 Features Characteristic S3F9444/F9454 S3C9442/C9444/C9452/C9454 4 Kbyte Flash ROM 2K/4K byte mask ROM Operating Voltage (VDD) 2.0 V to 5.5 V 2.0 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP = 12.5 V Program Memory Pin Configuration 20 DIP/20 SOP/16 DIP/8 DIP/8 SOP EPROM Programmability User Program multi time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP pin of the S3F9444/F9454 Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD VPP REG/MEM Address (A15–A0) R/W Mode 5V 5V 0 0000H 1 Flash ROM read 12.5 V 0 0000H 0 Flash ROM program 12.5 V 0 0000H 1 Flash ROM verify 12.5 V 1 0E3FH 0 Flash ROM read protection NOTE: "0" means Low level; "1" means High level. 15-3