S3C7559/P7559 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C7559/P7559 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P7559 is a microcontroller which has 32-kbyte one-time-programmable EPROM but its functions are same to S3C7559. With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the S3C7559/P7559 offers an excellent design solution for a wide variety of telecommunication applications. Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C7559/P7559's advanced CMOS technology provides for low power consumption and a wide operating voltage range. DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility. 1-1 PRODUCT OVERVIEW S3C7559/P7559 FEATURES SUMMARY Memory • 1 K × 4-bit RAM • 32 K × 8-bit ROM 55 I/O Pins • Input only: 4 pins • I/O: 43 pins • N-channel open-drain I/O (S/W): 8 pins Memory-Mapped I/O Structure • Data memory bank 15 DTMF Generator • Bit Sequential Carrier • Supports 8-bit serial data transfer in arbitrary format Interrupts • 3 external interrupt vectors • 4 internal interrupt vectors • 2 quasi-interrupts Power-Down Modes • Idle: Only CPU clock stops • Stop: Main system clock stops • Subsystem clock stop mode 16 dual-tone frequencies for tone dialing Oscillation Sources 8-bit Basic Timer • Crystal, ceramic for main system clock • Programmable internal timer • Crystal oscillator for subsystem clock • Watchdog timer • Main system clock frequency: 3.579545 MHz (typical) • Subsystem clock frequency: 32.768 kHz (typical) CPU clock divider circuit (by 4, 8, or 64) Two 8-bit Timer/Counters • Programmable interval timer • External event counter function • • Timer/counters clock outputs to TCLO0 and TCLO1 pins Instruction Execution Times • External clock signal divider • 0.67, 1.33, 10.7 µs at 6.0 MHz • Serial I/O interface clock generator • 1.12, 2.23, 17.88 µs at 3.579545 MHz • 122 µs at 32.768 kHz Watch Timer • • Time interval generation: 0.5 s, 3.9 ms at 32.768 kHz Operating Temperature • – 40 °C to 85 °C 4 frequency outputs to the BUZ pin Operating Voltage Range 8-bit Serial I/O Interface • 1.8 V to 5.5 V (at 3 MHz) • 8-bit transmit/receive mode • 2.7 V to 5.5 V (at 6 MHz) • 8-bit receive mode • LSB-first or MSB-first transmission selectable Package Types • 1-2 64 SDIP, 64 QFP S3C7559/P7559 PRODUCT OVERVIEW BLOCK DIAGRAM XIN INT0, INT1, INT2 INT4 8-BIT Timer/ Counter 0 RESET I/O Port 6 P7.0-P7.3/ KS4-KS7 I/O Port 7 P8.0-P8.3 I/O Port 8 Watch Timer Basic Timer Watch-Dog Timer XTIN XTOUT I/O Port 0 Interrupt Control Block Clock 8-BIT Timer/ Counter 1 P6.0-P6.3/ KS0-KS3 XOUT Internal Interrupts Instruction Decoder Stack Pointer P0.0/SCK P0.1/SO P0.2/SI P0.3/BTCO Serial I/O Port Program Counter Program Status Word Input Port1 I/O Port 2 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P10.0-P10.3 I/O Port 10 I/O Port 4 P3.0/TCLO0 P3.1/TCLO1 P3.2 P3.3 P4.0-P4.3 P11.0-P11.3 I/O Port 11 I/O Port 5 P5.0-P5.3 P12.0-P12.3 I/O Port 12 DTMF Generator DTMF P9.0-P9.3 P13.0-P13.2 I/O Port 9 Arithmetic and Logic Unit 1 K x 4-BIT Data Memory I/O Port 3 Flags 32 K Byte Program Memory I/O Port 13 Figure 1-1. S3C7559/P7559 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7559/P7559 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C7559 (64-SDIP-750) P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 P3.3 P3.2 TEST DTMF VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT RESET P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 Figure 1-2. S3C7559/P7559 Pin Assignment Diagrams (64-SDIP) 1-4 PRODUCT OVERVIEW 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT RESET P5.0 P5.1 P5.2 S3C7559/P7559 S3C7559 (64-QFP-1420F) 32 31 30 29 28 27 26 25 24 23 22 21 20 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 VDD DTMF TEST P3.2 P3.3 P12.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 52 53 54 55 56 57 58 59 60 61 62 63 64 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P8.0 P9.3 P9.2 P9.1 P9.0 VSS P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 Figure 1-3. S3C7559/P7559 Pin Assignment Diagrams (64-QFP) 1-5 PRODUCT OVERVIEW S3C7559/P7559 PIN DESCRIPTIONS Table 1-1. S3C7559/P7559 Pin Descriptions Pin Name Pin Type Description Number Share Pin P0.0 P0.1 P0.2 P0.3 I/O 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 15 (8) 14 (7) 13 (6) 12 (5) SCK SO SI BTCO P1.0 P1.1 P1.2 P1.3 I 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are assignable by software to port 1. 1 (61) 2 (60) 3 (59) 4 (58) INT0 INT1 INT2 INT4 P2.0 P2.1 P2.2 P2.3 I/O Same as port 0. 11 (4) 10 (3) 9 (2) 8 (1) TCLO0 TCLO1 CLO BUZ P3.0 P3.1 P3.2 P3.3 I/O Same as port 0. 34 (27) 33 (26) 29 (22) 28 (21) TCL0 TCL1 SCLK (1) SDAT (1) P4.0–P4.3 I/O 4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable to input pins and are automatically disable for output pins. N-channel open-drain or push-pull output can be selected by software. Port 4 and 5 can be paired to support 8-bit data transfer. 38–35 (31–28) 42–39 (35–32) – I/O 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Port 6 pins are individually software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. 51–48 (44–41) 55–52 (48–45) KS0–KS3 P5.0–P5.3 P6.0–P6.3 P7.0–P7.3 KS4–KS7 P8.0–P8.3 I/O Same as port 0. 59–56 (52–49) – P9.0–P9.3 I/O 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 63–60 (56–53) – NOTES: 1. SCLK and SDAT are used for S3P7559 only. 2. Parentheses indicate pin number for 64 QFP package. 1-6 S3C7559/P7559 PRODUCT OVERVIEW Table 1-1. S3C7559/P7559 Pin Descriptions (Continued) Pin Name P10.0–P10.3 Pin Type Description Number Share Pin I/O Same as port 9. Ports 10 and 11 can be paired to support 8-bit data transfer. 19–16 (12–9) 23–20 (16–13) – P12.0–P12.3 I/O 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-down resistors are software assignable; pull-down resistors are automatically disabled for output pins. 27–24 (20–17) – P13.0–P13.2 I/O 3-bit I/O port; characteristics are same as port 9. 7–5 (64–62) – DTMF O DTMF output. 31 (24) – SCK I/O Serial I/O interface clock signal 15 (8) P0.0 SO I/O Serial data output 14 (7) P0.1 SI I/O Serial data input 13 (6) P0.2 BTCO I/O Basic timer clock output 12 (5) P0.3 4, 3 (61, 60) P1.0, P1.1 P11.0–P11.3 INT0, INT1 I External interrupts. The triggering edge for INT0 and INT1 is selectable. INT0 is synchronized to system clock. INT2 I Quasi-interrupt with detection of rising edges 2 (59) P1.2 INT4 I External interrupt with detection of rising and falling edges. 1 (58) P1.3 TCLO0 I/O Timer/counter 0 clock output 11 (4) P2.0 TCLO1 I/O Timer/counter 1 clock output 10 (3) P2.1 CLO I/O Clock output 9 (2) P2.2 BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 32.768 kHz for buzzer sound 8 (1) P2.3 TCL0 I/O External clock input for timer/counter 0 34 (27) P3.0 TCL1 I/O External clock input for timer/counter 1 33 (26) P3.1 KS0–KS3 I/O Quasi-interrupt inputs with falling edge detection 51–48 (44–41) 55–52 (48–45) P6.0–P6.3 KS4–KS7 P7.0–P7.3 NOTE: Parentheses indicate pin number for 64 QFP package. 1-7 PRODUCT OVERVIEW S3C7559/P7559 Table 1-1. S3C7559/P7559Pin Descriptions (Concluded) Pin Name Pin Type Description Number Share Pin VDD – Power supply 32 (25) – VSS – Ground 64 (57) – RESET I Reset signal 43 (36) – XIN, XOUT – Crystal, ceramic, or R/C oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) 45, 44 (38, 37) – XTIN, XTOUT – Crystal oscillator signal for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) 46, 47 (39, 40) – TEST – Chip test input pin. Hold GND when the device is operating. 30 (23) – NOTE: Parentheses indicate pin number for 64 QFP package. 1-8 S3C7559/P7559 PRODUCT OVERVIEW Table 1-2. Overview of S3C7559/P7559 Pin Data Pin Names Share Pins I/O Type Reset Value Circuit Type I/O Input D-4 I Input A-1 P0.0–P0.3 SCK, SO, SI, BTCO P1.0–P1.3 INT0, INT1, INT2, INT4 P2.0–P2.3 TCLO0, TCLO1, CLO, BUZ I/O Input D-2 P3.0–P3.1 TCL0, TCL1 I/O Input D-4 P3.2–P3.3 – I/O Input D-2 P4.0–P4.3 P5.0–P5.3 – I/O Input E-2 I/O Input D-4 P6.0–P6.3 P7.0–P7.3 KS0–KS3 KS4–KS7 P8.0–P8.3 – I/O Input D-2 P9.0–P9.3 – I/O Input D-2 P10.0–P10.3 P11.0–P11.3 P12.0–P12.3 – I/O Input D-2 – I/O Input D-6 P13.0–P13.2 – I/O Input D-2 DTMF – O High impedence G-6 XIN, XOUT XTIN, XTOUT – – – – RESET – I – B NC – – – – VDD, VSS – – – – 1-9 PRODUCT OVERVIEW S3C7559/P7559 PIN CIRCUIT DIAGRAMS V DD VDD Pull-Up Resistor P-Channel In In N-Channel Schmitt Trigger Figure 1-4. Pin Circuit Type A Figure 1-6. Pin Circuit Type B VDD V DD Pull-Up Resistor Pull-Up Resistor Enable P-Channel Data Out Output DIsable In P-Channel N-Channel Schmitt Trigger Figure 1-5. Pin Circuit Type A-1 1-10 Figure 1-7. Pin Circuit Type C S3C7559/P7559 PRODUCT OVERVIEW Data VDD Output DIsable Pull-up Enable Data Output DIsable Circuit Type C P-Channel Circuit Type C I/O Pull-down Enable Figure 1-8. Pin Circuit Type D-2 Figure 1-10. Pin Circuit Type D-6 VDD VDD PNE Pull-up Enable Data Output Disable I/O VDD P-Channel Pull-up Enable I/O Data Circuit Type C I/O Output Disable Schmitt Trigger Figure 1-9. Pin Circuit Type D-4 Figure 1-11. Pin Circuit Type E-2 1-11 PRODUCT OVERVIEW S3C7559/P7559 DTMF Out + Disable 1-12 S3C7559/P7559 14 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on S3C7559 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — System clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — A.C timing measurement point — Clock timing measurement at XIN and XOUT — TCL timing — Input timing for RESET — Input timing for external interrupts — Serial data transfer timing Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA S3C7559/P7559 Table 14-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Units Supply Voltage VDD – – 0.3 to 6.5 V Input Voltage VI1 All I/O ports – 0.3 to VDD + 0.3 V Output Voltage VO – – 0.3 to VDD + 0.3 V Output Current High I OH One I/O port active – 15 mA All I/O ports active – 30 One I/O port active + 30 (Peak value) Output Current Low I OL mA + 15 (note) All I/O ports, total + 100 (Peak value) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty . Table 14-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Input Low Voltage 14-2 Symbol Conditions Min Typ Max Units – VDD V VIH1 All input pins except those specified below for VIH2–VIH4 0.7 VDD VIH2 Ports 0, 1, 3, 6, 7, and RESET 0.8 VDD VDD VIH3 Ports 4 and 5 with pull-up resistors assigned 0.7 VDD VDD VIH4 XIN, XOUT and XTIN VDD – 0.1 VDD VIL1 All input pins except those specified below for VIL2–VIL3 VIL2 Ports 0, 1, 3, 6, 7, and RESET VIL3 XIN, XOUT and XTIN – – 0.3 VDD 0.2 VDD 0.1 V S3C7559/P7559 ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Output High Voltage VOH IOH = – 1 mA Ports except 1 Output Low Voltage VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4,5 only Min Typ Max Units VDD – 1.0 – – V – – 2 V – 0.4 V 2 V 0.4 V 3 µA VDD = 1.8 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL = 4mA all out Ports except ports 4,5 VDD = 1.8 to 5.5 V, IOL = 1.6mA Input High Leakage Current ILIH1 VI = VDD All input pins except those specified below for ILIH2 ILIH2 VI = VDD – – 20 XIN, XOUT and XTIN ILIL1 VI = 0 V All input pins except below and RESET ILIL2 VI = 0 V XIN, XOUT and XTIN Output High Leakage Current ILOH VO = VDD All output pins – – 3 Output Low Leakage Current ILOL VO = 0 V All output pins – – -3 Pull-Up Resistor RL1 VDD = 5 V; VI = 0 V 25 45 100 VDD = 3 V 50 89 200 VDD = 5 V; VI = 0 V; RESET 100 212 400 VDD = 3 V 200 441 800 VDD = 5 V; VI = VDD; Port 12 25 46 100 VDD = 3 V 50 95 200 Input Low Leakage Current – -3 µA - 20 µA kΩ except RESET RL3 Pull-Down Resistor – RL4 14-3 ELECTRICAL DATA S3C7559/P7559 Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Supply Current (1) IDD1 (DTMF ON) Conditions Min Typ Max Units – 3.0 5.0 mA 1.6 3.0 6.0 MHz 2.7 8.0 3.58 MHz 2.0 4.0 6.0 MHz 1.3 4.0 3.58 MHz 0.9 2.3 6.0 MHz 0.8 2.5 3.58 MHz 0.7 1.8 6.0 MHz 0.3 1.5 3.58 MHz 0.2 1.0 12.5 30 4.5 15 1.9 5 0.6 3 0.2 3 0.1 2 – 16 – 14 – 11 dBV Run mode; VDD = 5.0 V ± 10% 3.58 MHz Crystal oscillator; C1 = C2 = 22 pF VDD = 3 V ± 10% IDD2 Run mode; VDD = 5.0 V ± 10% (DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF VDD = 3 V ± 10% IDD3 Idle mode; VDD = 5 V ± 10% VDD = 3 V ± 10% IDD4 Run mode; VDD = 3.0 V ± 10% 32 kHz Crystal oscillator IDD5 Idle mode; VDD = 3.0 V ± 10% 32 kHz Crystal oscillator IDD6 Stop mode; VDD = 5 V ± 10% Stop mode; VDD = 3 V ± 10% Stop mode; VDD = 5 V ± 10% – SCMOD = 0000B XT = 0V – SCMOD = 0100B Stop mode; VDD = 3 V ± 10% µA Row Tone Level (2) VROW VDD = 2.0 V to 5.5 V RL =12 KΩ; Temp = – 30 to 60 °C Ratio of Column to Row Tone (2) dBCR VDD = 2.0 V to 5.5 V RL = 12 KΩ; Temp = – 30 to 60 °C 1 2 3 dB Distortion (2) (Dual tone) THD VDD = 2.0 V to 5.5 V 1 MHz band, RL = 12 KΩ Temp = – 30 to 60 °C – – 5 % NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. 3. DTMF electrical characteristics. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 14-4 S3C7559/P7559 ELECTRICAL DATA Table 14-3. Main System Clock Oscillator Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Parameter Min Typ Max Units Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – – 4 ms Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3 – – 10 ms MHz C2 Stabilization time (2) Crystal Oscillator XIN XOUT C1 External Clock XIN Test Condition VDD = 3 V C2 XOUT Stabilization time (2) VDD = 3 V XIN input frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3 – 83.3 – 1250 XIN input high and low level width (tXH, tXL) ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA S3C7559/P7559 Table 14-4. Recommended Oscillator Constants (TA = – 40 °C to + 85 °C) Manufacturer TDK Series Number (1) Frequency Range Oscillator Voltage Range (V) C1 C2 MIN MAX Remarks FCR M5 3.58 MHz–6.0 MHz 33 33 2.0 5.5 Leaded Type FCR MC5 3.58 MHz–6.0 MHz (2) (2) 2.0 5.5 On-chip C Leaded Type CCR MC3 3.58 MHz–6.0 MHz (3) (3) 2.0 5.5 On-chip C SMD Type NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. 14-6 Load Cap (pF) S3C7559/P7559 ELECTRICAL DATA Table 14-5. Subsystem Clock Oscillator Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Oscillato r Clock Configuration Crystal Oscillator XTI XTOUT Parameter Test Condition Min Typ Max Units – 32 32.76 8 35 kHz VDD = 2.7 V to 5.5 V – 1.0 2 s VDD = 1.8 V to 5.5 V – – 10 s XTIN input frequency (1) – 32 – 100 kHz XTIN input high and low level width (tXH, tXL) – 5 – 15 µs Oscillation frequency (1) N C1 C2 Stabilization time (2) External Clock XTI XTOUT N NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is terminated. Table 14-6. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT – – 15 pF CIO – – 15 pF I/O Capacitance 14-7 ELECTRICAL DATA S3C7559/P7559 Table 14-7. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (1) TCL0, TCL1 Input Frequency Symbol tCY f TI0, f TI1 Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 1.8 V to 5.5 V 1.33 VDD = 2.7 V to 5.5 V 0 – 1.5 MHz 1 MHz – – µs – – ns – – ns – – ns – – ns VDD = 1.8 V to 5.5 V TCL0, TCL1 Input High, Low Width SCK Cycle Time tTIH0, tTIL0 tTIH1, tTIL1 tKCY VDD = 2.7 V to 5.5 V 0.48 VDD = 1.8 V to 5.5 V 1.8 VDD = 2.7 V to 5.5 V 800 External SCK source Internal SCK source 670 VDD = 1.8 V to 5.5 V 3200 External SCK source SCK High, Low Width tKH, tKL Internal SCK source 3800 VDD = 2.7 V to 5.5 V 335 External SCK source Internal SCK source VDD = 1.8 V to 5.5 V tKCY–250 1600 External SCK source Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V tKCY–2150 100 External SCK source Internal SCK source 150 VDD = 1.8 V to 5.5 V 150 External SCK source SI Hold Time to SCK High tKSI Internal SCK source 500 VDD = 2.7 V to 5.5 V 400 External SCK source Internal SCK source 400 VDD = 1.8 V to 5.5 V 600 External SCK source Internal SCK source 14-8 500 S3C7559/P7559 ELECTRICAL DATA Table 14-7. A.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output Delay for SCK to SO tKSO (note) Conditions VDD = 2.7 V to 5.5 V Min Typ Max Units – – 300 ns External SCK source Internal SCK source 250 VDD = 1.8 V to 5.5 V 1000 External SCK source Internal SCK source Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL 1000 INT0, INT1, INT2, INT4, KS0–KS7 10 – – µs Input 10 – – µs NOTE: R (1 kΩ) and C (100 pF) are the load resistance and load capacitance of the SO output line. Main Oscillator Frequency (Divided by 4) CPU Clock 6 MHz 1.5 MHz 1.05 MHz 4.2 MHz 3 MHz 0.75 MHz 15.625 kHz 1 2 3 1.8 2.7 4 5 6 7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 14-1. Standard Operating Voltage Range 14-9 ELECTRICAL DATA S3C7559/P7559 Table 14-8. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 1.8 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL 0 – – µs Oscillator stabilization wait time (1) tWAIT Released by RESET – 217/fx – ms Released by interrupt – (2) – ms VDDDR = 1.5 V – NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 14-10 S3C7559/P7559 ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation ~ ~ Idle Mode Stop Mode Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT tSREL Figure 14-2. Stop Mode Release Timing When Initiated by RESET Idle Mode ~ ~ Normal Operating Mode Stop Mode Data Retention ~ ~ VDD VDDDR Execution of STOP Instrction tSREL tWAIT Power-down Mode Terminating (Interrupt Request) Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request 14-11 ELECTRICAL DATA S3C7559/P7559 0.8 VDD 0.8 VDD Measurement Points 0.2 VDD 0.2 VDD Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 14-5. Clock Timing Measurement at XIN (XTIN) 1/fTI tTIL tTIH TCL 0.8 VDD 0.2 VDD Figure 14-6. TCL0/1 Timing 14-12 S3C7559/P7559 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 14-7. Input Timing for RESET Signal tINTL INT0, 1, 2, 4, KS0 to KS7 tINTH 0.8 VDD 0.2 VDD Figure 14-8. Input Timing for External Interrupts and Quasi-Interrupts 14-13 ELECTRICAL DATA S3C7559/P7559 tKCY tKL tKH SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKS O SO Output Data Figure 14-9. Serial Data Transfer Timing 14-14 S3C7559/P7559 MECHANICAL DATA 15 MECHANICAL DATA This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram 23.90 ± 0.3 0-8 14.00 ± 0.2 ± 0.2 0.15 64-QFP-1420F 0.80 ± 0.20 #64 #1 1.00 0.40+0.10 -0.05 +0.10 -0.05 0.10 MAX (1.00) 17.90 ± 0.3 20.00 (1.00) 0.05-0.25 0.15 MAX 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 15-1. 64-QFP-1420F Package Dimensions 15-1 MECHANICAL DATA S3C7559/P7559 #33 0-15 0.2 5 17.00 64-SDIP-750 +0 - 0 .1 .05 19.05 ± 0.2 #64 NOTE: 1.00 ± 0.1 5.08 MAX 0.45± 0.1 1.778 ± 0.3 57.80 ± 0.2 (1.34) 3.30 ± 0.2 58.20 MAX 4.10 #32 0.51 MIN #1 Dimensions are in millimeters. Figure 15-2. 64-SDIP-750C Package Dimensions 15-2 S3C7559/P7559 16 S3P7559 OTP S3P7559OTP OVERVIEW The S3P7559 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7559 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7559 is fully compatible with the S3C7559, both in function and in pin configuration. Because of its simple programming requirements, the S3P7559 is ideal for use as an evaluation chip for the S3C7559. 16-1 S3P7559 OTP S3C7559/P7559 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NOTE: S3P7559 (64-SDIP-750) P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 SDAT/P3.3 SCLK/P3.2 VPP/TEST DTMF VDD/VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS/VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT RESET/RESET RESET P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 The bold indicate a OTP pin name. Figure 16-1. S3P7559 Pin Assignments (64-SDIP) 16-2 S3P7559 OTP 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT RESET/RESET RESET P5.0 P5.1 P5.2 S3C7559/P7559 52 53 54 55 56 57 58 59 60 61 62 63 64 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 VDD/VDD DTMF TEST/VPP P3.2/SCLK P3.3/SDAT P12.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3P7559 (64-QFP-1420F) 32 31 30 29 28 27 26 25 24 23 22 21 20 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P8.0 P9.3 P9.2 P9.1 P9.0 VSS/VSS P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 NOTE: The bold indicate a OTP pin name. Figure 16-2. S3P7559 Pin Assignments (64-QFP) 16-3 S3P7559 OTP S3C7559/P7559 Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Pin Name During Programming Pin No. I/O Function SDAT 28 (21) I/O SCLK 29 (22) I Serial clock pin. Input only pin. VPP (TEST) 30 (23) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OTP is operating. RESET 43 (36) I Chip initialization VDD/VSS 32 (25) / 64 (57) I Logic power supply pin. VDD should be tied to + 5 V during programming. Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. NOTE: Parentheses indicate pin number for 64 QFP package. Table 16-2. Comparison of S3P7559 and S3C7559 Features Characteristic S3P7559 S3C7559 Program Memory 32 K byte EPROM 32 K byte mask ROM Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5V Pin Configuration 64 SDIP/QFP 64 SDIP/QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7559, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/MEM MEM Address (A15–A0) R/W W 5V 5V 0 0000H 1 EPROM read 12.5V 0 0000H 0 EPROM program 12.5V 0 0000H 1 EPROM verify 12.5V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 16-4 Mode S3C7559/P7559 S3P7559 OTP Table 16-4. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Units Supply Voltage VDD – – 0.3 to 6.5 V Input Voltage VI1 All I/O ports – 0.3 to VDD + 0.3 V Output Voltage VO – – 0.3 to VDD + 0.3 V Output Current High I OH One I/O port active – 15 mA All I/O ports active – 30 One I/O port active + 30 (Peak value) Output Current Low I OL mA + 15 (note) All I/O ports, total + 100 (Peak value) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × Duty . Table 16-5. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Input Low Voltage Symbol Conditions Min Typ Max Units – VDD V VIH1 All input pins except those specified below for VIH2–VIH4 0.7 VDD VIH2 Ports 0, 1, 3, 6, 7, and RESET 0.8 VDD VDD VIH3 Ports 4 and 5 with pull-up resistors assigned 0.7 VDD VDD VIH4 XIN, XOUT and XTIN VDD – 0.1 VDD VIL1 All input pins except those specified below for VIL2–VIL3 VIL2 Ports 0, 1, 3, 6, 7, and RESET VIL3 XIN, XOUT and XTIN – – 0.3 VDD V 0.2 VDD 0.1 16-5 S3P7559 OTP S3C7559/P7559 Table 16-5. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Output High Voltage VOH IOH = – 1 mA Ports except 1 Output Low Voltage VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4,5 only Min Typ Max Units VDD – 1.0 – – V – – 2 V – 0.4 V 2 V 0.4 V 3 µA VDD = 2.0 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL = 4mA all out Ports except ports 4,5 VDD = 2.0 to 5.5 V, IOL = 1.6mA Input High Leakage Current ILIH1 VI = VDD All input pins except those specified below for ILIH2 ILIH2 VI = VDD – – 20 XIN, XOUT and XTIN Input Low Leakage Current ILIL1 VI = 0 V – – -3 µA All input pins except below and RESET ILIL2 VI = 0 V – 20 XIN, XOUT and XTIN Output High Leakage Current ILOH VO = VDD All output pins – – 3 Output Low Leakage Current ILOL VO = 0 V All output pins – – –3 Pull-up Resistor RL1 VDD = 5 V; VI = 0 V 25 45 100 VDD = 3 V 50 89 200 VDD = 5 V; VI = 0 V; RESET 100 212 400 VDD = 3 V 200 441 800 VDD = 5 V ; VI = VDD; Port 12 25 46 100 VDD = 3 V 50 95 200 except RESET RL3 Pull-Down Resistor 16-6 RL4 µA kΩ S3C7559/P7559 S3P7559 OTP Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Supply Current (1) IDD1 (DTMF ON) Conditions Min Typ Max Units – 3.0 5.0 mA 1.6 3.0 6.0 MHz 2.7 8.0 3.58 MHz 2.0 4.0 6.0 MHz 1.3 4.0 3.58 MHz 0.9 2.3 6.0 MHz 0.8 2.5 3.58 MHz 0.7 1.8 6.0 MHz 0.3 1.5 3.58 MHz 0.2 1.0 12.5 30 4.5 15 1.9 5 0.6 3 Run mode; VDD = 5.0 V ± 10% 3.58 MHz Crystal oscillator; C1 = C2 = 22 pF VDD = 3 V ± 10% IDD2 Run mode; VDD = 5.0 V ± 10% (DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF VDD = 3 V ± 10% IDD3 Idle mode; VDD = 5 V ± 10% VDD = 3 V ± 10% IDD4 Run mode; VDD = 3.0 V ± 10% 32 kHz Crystal oscillator IDD5 Idle mode; VDD = 3.0 V ± 10% 32 kHz Crystal oscillator IDD6 Stop mode; VDD = 5 V ± 10% – – Stop mode; VDD = 3 V ± 10% SCMOD = 0000B XT = 0 V Stop mode; VDD = 5 V ± 10% SCMOD = 0.2 3 Stop mode; VDD = 3 V ± 10% 0100B 0.1 2 µA Row Tone Level (2) VROW VDD = 2.0 V to 5.5 V RL =12 KΩ; Temp = – 30 to 60 °C – 16 – 14 – 11 dBV Ratio of Column to Row Tone (2) dBCR VDD = 2.0 V to 5.5 V RL =12 KΩ; Temp = – 30 to 60 °C 1 2 3 dB Distortion (2) (Dual tone) THD VDD = 2.0 V to 5.5 V 1 MHz band, RL = 12 KΩ Temp = – 30 to 60 °C – – 5 % NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. 3. DTMF electrical characteristics. For D.C. electrical values, the power control register (PCON) must be set to 0011B. 16-7 S3P7559 OTP S3C7559/P7559 Table 16-6. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Parameter Min Typ Max Units Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3.0 – – 4 ms Oscillation frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz VDD = 1.8 V to 5.5 V 0.4 – 3.0 – – 10 ms MHz C2 Stabilization time (2) Crystal Oscillator XIN XOUT C1 External Clock XIN Test Condition VDD = 3 V C2 XOUT Stabilization time (2) VDD = 3 V XIN input frequency (1) VDD = 2.7 V to 5.5 V 0.4 – 6.0 VDD = 1.8 V to 5.5 V 0.4 – 3.0 – 83.3 – 1250 Xin input high and low level width (tXH, tXL) NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 16-8 ns S3C7559/P7559 S3P7559 OTP Table 16-7. Recommended Oscillator Constants (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) TDK Frequency Range Load Cap (pF) Oscillator Voltage Range (V) C1 C2 MIN MAX Remarks FCR M5 3.58 MHz–6.0 MHz 33 33 2.0 5.5 Leaded Type FCR MC5 3.58 MHz–6.0 MHz (2) (2) 2.0 5.5 On-chip C Leaded Type CCR MC3 3.58 MHz–6.0 MHz (3) (3) 2.0 5.5 On-chip C SMD Type NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. Table 16-8. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration XTI XTOUT Parameter Test Condition Min Typ Max Units Oscillation frequency (1) – 32 32.768 35 kHz VDD = 2.7 V to 5.5 V – 1.0 2 s VDD = 1.8 V to 5.5 V – – 10 s XTIN input frequency (1) – 32 – 100 kHz XTIN input high and low level width (tXH, tXL) – 5 – 15 µs N C1 C2 Stabilization time (2) External Clock XTI XTOUT N NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is terminated. 16-9 S3P7559 OTP S3C7559/P7559 Table 16-9. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT – – 15 pF CIO – – 15 pF I/O Capacitance Main Oscillator Frequency (Divided by 4) CPU Clock 1.5 MHz 6 MHz 1.05 MHz 4.2 MHz 0.75 MHz 3 MHz 15.625 kHz 1 2 3 1.8 2.7 4 5 6 7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 16-3. Standard Operating Voltage Range 16-10