S3C9404/P9404/C9414/P9414 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM87RI PRODUCT FAMILY Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. S3C9404/C9414 MICROCONTROLLER The S3C9404/C9414 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87Ri CPU core. The S3C9404/C9414 is a versatile microcontroller, with its A/D converter and a zero-crossing detection capability it can be used in a wide range of general purpose applications. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9404/C9414 has 4-Kbytes of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM. Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: — Four configurable I/O ports (S3C9404: 22 pins, S3C9414: 16 pins) — Six interrupt sources with one vector and one interrupt level — Two 8-bit timer/counter with various operating modes — Analog to digital converter (S3C9404: 8-bit, 8-channel, S3C9414: 10-bit, 5-channel) — One zero cross detection module The S3C9404/C9414 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC, ZCD and capture functions. S3C9404 is available in a 30-pin SDIP and a 32-pin SOP package. S3C9414 is available in a 24-pin SDIP and a 24-pin SOP package. OTP The S3P9404/P9414 is an OTP (one time programmable) version of the S3C9404/C9414 microcontroller. The S3P9404/P9414 has on-chip 4-Kbyte one-time programmable EEPROM instead of masked ROM. The S3P9404/P9414 is fully compatible with the S3C9404/C9414, in function, in D.C. electrical characteristics and in pin configuration. 1-1 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 FEATURES CPU Timer/Counter • • One 8-bit basic timer for watchdog function • One 8-bit timer/counter with three operating modes (10-bit PWM 1ch) • One 8-bit timer/counter for the zero-crossing detection circuit SAM87Ri CPU core Memory • 4-Kbyte internal program memory (ROM) • 208-byte general purpose register area (RAM) Instruction Set Zero-Crossing Detection Circuit • 41 instructions • • IDLE and STOP instructions added for power-down modes. Instruction Execution Time • 600 ns at 10 MHz fOSC (minimum) Zero-crossing detection circuit that generates a digital signal in synchronism with an AC signal input Buzzer Frequency Range • 200 Hz to 20 kHz signal can be generated Operating Temperature Range Interrupts • 6 interrupt sources with one vector and one level interrupt structure • – 40°C to + 85°C Operating Voltage Range Oscillation Frequency • • 1 MHz to 10 MHz external crystal oscillator OTP Interface Protocol Spec • Maximum 10 MHz CPU clock • • 4 MHz RC oscillator 2.7 V to 5.5 V Serial OTP Package Types General I/O • 30-pin SDIP, 32-pin SOP for S3C9404/P9404 • Four I/O ports (22 pins for S3C9404, 16 pins for S3C9414) • 24-pin SDIP, 24-pin SOP for S3C9414/P9414 • Bit programmable ports A/D Converter • Eight analog input pins • 8-bit conversion resolution (S3C9404) • 10-bit conversion resolution (S3C9414) 1-2 S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 BASIC TIMER XIN XOUT PORT 0 P1.0-P1.3 /ZCD,BUZ,T0,CLO PORT 1 OSC I/O PORT I/O and INTERRUPT CONTROL T0(PWM) TIMER 0 P1.1/BUZ TIMER 1 PORT 2 P2.0-P2.3 /INT0-INT1 /ADC6-ADC7 SAM87RI CPU ADC0 -ADC7 ADC P1.0/ ZCD ZCD PORT 3 4-KB ROM P3.0-P3.5 /ADC0-ADC5 208-BYTE REGISTER FILE Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 PIN ASSIGNMENTS VSS XIN XOUT TEST P0.1 P0.0 RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3C9404 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 Figure 1-2. Pin Assignment Diagram (30-Pin SDIP Package) VSS XIN XOUT TEST P0.1 P0.0 RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3C9404 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 NC P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package) 1-4 S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW VSS XIN XOUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 S3C9414 24-SDIP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AVref AVSS Figure 1-4. Pin Assignment Diagram (24-Pin SDIP Package) VSS XIN XOUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 KS86C4104 24-SOP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AVref AVSS Figure 1-5. Pin Assignment Diagram (24-Pin SOP Package) 1-5 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 PIN DESCRIPTIONS Table 1-1. S3C9404/C9414 Pin Descriptions Pin Names Pin Type Pin Description Circuit Type P0.0-P0.7 I/O Bit-programmable I/O port for normal input or push-pull, open-drain output. Pull-up resistors are assignable by software. E-2 P1.0-P1.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 1 pins can also be used as alternative functions. F D D D ZCD BUZ T0(PWM) CLO P2.0-P2.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull, open drain output. Pull up resistors are assignable by software. Port 2 can also be used as external interrupt, A/D input. E E-1 INT0–INT1 ADC6–ADC7 P3.0-P3.5 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 3 pins can also be used as A/D converter input. F ADC0–ADC5 XIN, XOUT – Crystal/ceramic, or RC oscillator signal for system clock. – – INT0–INT1 I External interrupt input. E P2.0–P2.1 RESET I System RESET signal input pin. B – TEST I Test signal input pin (for factory use only: must be connected to VSS) – – VDD, VSS – Voltage input pin and ground – – AVREF, AVSS – A/D converter reference voltage input and ground – – ZCD I Zero crossing detector input F P1.0 BUZ O 200 Hz–20 kHz frequency output for buzzer sound D P1.1 T0 I/O Timer 0 capture input or 10-bit PWM output D P1.2 CLO O System clock output port D P1.3 ADC0–ADC7 I A/D converter input F E-1 P3.0–P3.5 P2.2–P2.3 NOTE: Port 0.7, P1.3, P2.1–P2.3 and P3.5 is not available in S3C9414/P4104 . 1-6 Share Pins S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW PIN CIRCUITS VDD VDD P-CHANNEL P-CHANNEL DATA OUT IN N-CHANNEL N-CHANNEL OUTPUT DISABLE Figure 1-6. Pin Circuit Type A Figure 1-8. Pin Circuit Type C VDD PULL-UP RESISTOR VDD PULL-UP RESISTOR RESISTOR ENABLE DATA IN OUTPUT DISABLE P-CHANNEL CIRCUIT TYPE C IN/OUT DATA Figure 1-7. Pin Circuit Type B Figure 1-9. Pin Circuit Type D 1-7 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 VDD VDD VDD VDD PULL-UP RESISTOR PNE P-CH PULL-UP RESISTOR PNE PULL-UP ENABLE DATA IN/OUT P-CH PULL-UP ENABLE DATA IN/OUT N-CH N-CH OUTPUT DISABLE OUTPUT DISABLE INPUT INPUT Figure 1-10. Pin Circuit Type E Figure 1-10. Pin Circuit Type E-2 VDD VDD VDD PULL-UP RESISTOR PNE P-CH PULL-UP ENABLE PULL-UP RESISTOR PULL-UP ENABLE VDD DATA DATA IN/OUT N-CH OUTPUT DISABLE OUTPUT DISABLE CIRCUIT TYPE C DIGITAL INPUT DIGITAL INPUT ANALOG INPUT ANALOG INPUT Figure 1-11. Pin Circuit Type E-1 1-8 Figure 1-12. Pin Circuit Type F IN/OUT S3C9404/P9404/C9414/P9414 13 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9404/C9414 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Oscillator characteristics — Oscillation stabilization time — Operating Voltage Range — Schmitt trigger input characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a RESET — A/D converter electrical characteristics — Zero-crossing detector — Zero Crossing Waveform Diagram 13-1 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Conditions VDD – Rating Unit – 0.3 to + 6.5 V Input voltage VI All input ports – 0.3 to VDD + 0.3 V Output voltage VO All output ports – 0.3 to VDD + 0.3 V Output current I OH One I/O pin active – 18 All I/O pins active – 60 One I/O pin active + 30 Total pin current for ports 1, 2, 3 + 100 Total pin current for ports 0 + 200 high Output current I OL low mA mA Operating temperature TA – – 40 to + 85 °C Storage temperature TSTG – – 65 to + 150 °C Table 13-2. DC Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Typ Max Unit 0.8 VDD – VDD V – 0.2 VDD V VIH1 Ports 1,2,3, and VIH2 Port 0 0.7 VDD VIH3 XIN and XOUT VDD –0.1 VIL1 Ports 1,2,3, and VIL2 Port 0 VIL3 XIN and XOUT Output high voltage VOH IOH = – 1 mA ports 0, 1, 2, 3 VDD= 4.5 to 5.5 V VDD – 1.0 – – V Output low voltage VOL1 IOL = 15 mA port 0 VDD= 4.5 to 5.5 V – 0.4 2.0 V VOL2 IOL = 4 mA port 1,2,3 VDD= 4.5 to 5.5 V 0.4 2.0 Input high voltage Input low voltage 13-2 RESET RESET VDD= 2.7 to 5.5 V Min VDD= 2.7 to 5.5 V – 0.3 VDD 0.1 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-2. DC Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Symbol Input high leakage current ILIH1 All inputs except ILIH2 VIN = VDD ILIH2 XIN, XOUT VIN = VDD ILIL1 All inputs except ILIL2 and RESET VIN = 0 V ILIL2 XIN, XOUT VIN = 0 V Output high leakage current ILOH All outputs VOUT = VDD – – 2 µA Output low leakage current ILOL All outputs VOUT = 0 V – – –2 µA Pull-up resistors RP VIN = 0 V VDD = 5 V 30 47 70 kΩ RESET VDD = 3 V 30 280 350 Run mode 10 MHz CPU clock VDD = 5 V ± 10% – 7.5 15 8 MHz CPU clock VDD = 3 V ± 10% 3 6 Idle mode 10 MHz CPU clock VDD = 5 V ± 10% 2 5 8 MHz CPU clock VDD = 3 V ± 10% 0.7 2.5 Stop mode VDD = 5 V ± 10% 0.1 5 Input low leakage current Supply current IDD1 IDD2 IDD3 Conditions Ports 0–3 and Min Typ Max Unit – – 1 µA 20 – – –1 µA – 20 mA µA VDD = 3 V ± 10% NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resisters, output port drive current, ZCD and ADC. 13-3 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-3. AC Electrical Characteristics (TA = –20°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width tINTH, tINTL Port 2 VDD = 5V ± 10% – 200 – ns RESET input low width ZCD noise filter tRSL Input VDD = 5V ± 10% – 1 – µs – 1 tCPU tNF1L t NF1H tRSL tNF2 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 13-1. Input Timing Measurement Points 13-4 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-4. Oscillator Characteristics (TA = – 40°C to + 85°C) Oscillator Clock Circuit Main crystal or ceramic XIN C1 Test Condition Min Typ Max Unit VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V 1 1 – – 10 8 MHz VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V 1 1 – – 10 8 VDD = 4.75 to 5.25 V – XOUT C2 External clock XIN XOUT RC oscillator XIN R R = 8.2K 4 (P1.3/ CLO) – XOUT Table 13-5. Oscillation Stabilization Time (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit ms Main crystal f OSC > 1.0 MHz – – 20 Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 10 External clock (main system) XIN input high and low width (tXH, tXL) 25 – 500 ns Oscillator stabilization tWAIT when released by a reset (1) – 216/fOSC – ms wait time tWAIT when released by an interrupt (2) – – – NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON. 13-5 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 CPU CLOCK 10 MHz 8 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 4 5 5.5 6 SUPPLY VOLTAGE (V) Figure 13-2. Operating Voltage Range Vout VDD A = 0.2 V DD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B 0.3 V DD C D Vin 0.7 V DD Figure 13-3. Schmitt Trigger Input Characteristics Diagram 13-6 7 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-6. Data Retention Supply Voltage in Stop Mode (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5V) Parameter Symbol Conditions Data retention supply voltage VDDDR Stop mode Data retention supply current IDDDR Stop mode; VDDDR = 2.0 V Min Typ Max Unit 2.0 – 5.5 V – 0.1 5 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. ∼ VDD STOP MODE ∼ INTERNAL RESET DATA RETENTION MODE IDLE MODE (BASIC TIMER ACTIVE) NORMAL OPERATING MODE VDDDR RESET EXECUTION OF STOP 0.8 V DD 0.2 V DD t WAIT NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC Figure 13-4. Stop Mode Release Timing When Initiated by a RESET 13-7 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-7. A/D Converter Electrical Characteristics (S3C9404) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions VDD = 5.12 V Total accuracy S3C9404: 8-bit ADC Min Typ Max Unit – – ±2 LSB Integral linearity error ILE CPU clock = 10 MHz AVREF = 5.12 V – ± 1.5 Differential linearity error DLE AVSS = 0 V – ±1 Offset error of top EOT –1 ±2 Offset error of bottom EOB –1 ±2 Conversion time(1) tCON 5 – – µs Analog input voltage VIAN – AVSS – AVREF V Analog input impedance RAN – 2 – – MΩ ADC reference voltage AVREF – 2.5 – VDD V ADC reference ground AVSS – VSS – VSS + 0.3 V Analog input current IADIN AVREF = VDD = 5 V conversion time = 5 µs – – 10 µA ADC block current (2) IADC AVREF = VDD = 5 V conversion time = 5 µs – 1 3 mA 0.5 1.5 100 500 fcpu = 10 MHz AVREF = VDD = 3 V conversion time = 5 µs AVREF = VDD = 5 V Power down mode – NOTES: 1. “Conversion time” is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 13-8 nA S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-8. A/D Converter Electrical Characteristics (S3C9414) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions Resolution VDD = 5.12 V Total accuracy S3C9414: 10-bit ADC Min Typ Max Unit – 10 – bit – – ±3 LSB Integral linearity error ILE CPU clock = 10 MHz AVREF = 5.12 V – ±2 Differential linearity error DLE AVSS = 0 V – ±1 Offset error of top EOT ±1 ±3 Offset error of bottom EOB ± 0.5 ±2 Conversion time tCON 10-bit conversion 50 x 4/ fOSC (3) 20 – – µs Analog input voltage VIAN – AVSS – AVREF V Analog input impedance RAN – 2 – – MΩ Analog reference voltage AVREF – 2.5 – VDD V Analog ground AVSS – VSS – VSS + 0.3 V Analog input current IADIN AVREF = VDD = 5 V conversion time = 20 µs – – 10 µA Analog block current (2) IADC AVREF = VDD = 5 V conversion time = 20 µs 1 3 mA AVREF = VDD = 3 V conversion time = 20 µs 0.5 1.5 mA AVREF = VDD = 5 V when power down mode 100 500 nA (1) NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock. 13-9 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-9. Zero Crossing Detector (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Zero-crossing detection input voltage Zero-crossing detection accuracy Zero-crossing detection input frequency Symbol VZC VAZC Test Conditions AC connection c = 0.1 µF f ZC = 60 Hz Min 1.0 Typ – Max 3.0 Unit Vp-p – – ± 150 mV 40 – 200 Hz (sine wave) VDD = 5 V f OSC = 10 MHz – f ZC 1/fZC AC Input VAZC ZCINT Figure 13-5. Zero Crossing Waveform Diagram 13-10 VAZ(P-P) S3C9404/P9404/C9414/P9414 ELECTRICAL DATA 70 VDD = 5.5 V 60 VDD = 5.0 V 50 VDD = 4.5 V 40 I OL (mA) 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOL (V) Figure 13-6. IOL vs. VOL (P0, TA = 25 °C) 13-11 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 50 VDD = 5.5 V 40 VDD = 5.0 V I OL (mA) VDD = 4.5 V 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOL (V) Figure 13-7. IOL vs. VOL (P1–P3, TA = 25 °C) 13-12 4.5 5.0 5.5 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA − 36 − 32 − 28 − 24 20 I OH − (mA) − 16 VDD = 5.5 V − 12 VDD = 5.0 V −8 VDD = 4.5 V −4 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOH (V) Figure 13-8. IOH vs. VOH (P0, TA = 25 °C) 13-13 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 − 24 20 I OH − (mA) − 16 − 12 VDD = 5.5 V −8 VDD = 5.0 V −4 VDD = 4.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOH (V) Figure 13-9. IOH vs. VOH (P1–P3, TA = 25 °C) 13-14 5.0 5.5 S3C9404/P9404/C9414/P9414 14 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9404/C9414 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package (32-SOP-450A), a 24-pin SDIP package (24-SDIP-300) and a 24-pin SOP package (24-SOP-375). Package dimensions are shown in Figures 14-1, 14-2, 14-3, and 14-4. #16 – 0.05 0.25 +0.1 30-SDIP-400 0.56 ± 0.1 (1.30) 1.12 ± 0.1 1.778 5.08MAX 27.48 ± 0.2 3.30 ± 0.3 27.88 MAX 3.81 ± 0.2 #15 0.51MIN #1 0-15 ° 10.16 8.94 ± 0.2 #30 NOTE: Dimensions are in millimeters. Figure 14-1. 30-Pin SDIP Package Dimensions 14-1 MECHANICAL DATA S3C9404/P9404/C9414/P9414 0~8° #16 (0.43) ± 0.2 0.40 ± 0.1 1.27 0.0MIN 19.90 0.20 2.00 ± 0.2 #1 +0.10 - 0.05 0.10 MAX NOTE: Dimensions are in millimeters. Figure 14-2. 32-SOP-450A Package Dimensions 14-2 ± 0.2 0.78 32-SOP-450A 11.43 8.34 ± 0.2 #17 2.40MAX 12.00 ± 0.3 #32 S3C9404/P9404/C9414/P9414 MECHANICAL DATA #13 0.89 ± 0.1 1.778 – 0.05 5.08MAX 0.46 ± 0.1 3.30 ± 0.3 22.95 ± 0.2 3.25 ± 0.2 #12 23.35 MAX (1.69) 0.25 +0.1 7.62 24-SDIP-300 #1 0-15 ° 0.51MIN 6.40 ± 0.2 #24 NOTE: Dimensions are in millimeters. Figure 14-3. 24-SDIP-300 Package Dimensions 14-3 MECHANICAL DATA S3C9404/P9404/C9414/P9414 0-8° #12 15.34 ± 0.2 0.38 ± 0.1 1.27 0.05MIN 15.74 MAX (0.69) +0.10 0.15 - 0.05 2.30 ± 0.2 #1 0.10 MAX NOTE: Dimensions are in millimeters. Figure 14-4. 24-SOP-375 Package Dimensions 14-4 0.85 ±0.20 24-SOP-375 9.53 7.50 ± 0.2 #13 2.70MAX 10.30 ± 0.3 #24 S3C9404/P9404/C9414/P9414 15 S3P9404/P9414 OTP S3P9404/P9414 OTP OVERVIEW The S3P9404/P9414 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9404/C9414 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9404/P9414 is fully compatible with the S3C9404/C9414 , both in function and in pin configuration. Because of its simple programming requirements, the S3P9404/P9414 is ideal for use as an evaluation chip for the S3C9404/C9414 . VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3P9404 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD/ VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 NOTE: The bolds indicate an OTP pin name. Figure 15-1. Pin Assignment Diagram (30-Pin SDIP Package) 15-1 S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3P9404 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD/ VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 NC P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 NOTE: The bolds indicate an OTP pin name. Figure 15-2. Pin Assignment Diagram (32-Pin SOP Package) 15-2 S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP VSS/V SS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 S3P9414 24-SDIP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD/ VDD P0.2/ SCLK P0.3/ SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS NOTE: The bolds indicate an OTP pin name. Figure 15-3. Pin Assignment Diagram (24-Pin SDIP Package) 15-3 S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414 VSS/V SS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 S3P9414 24-SOP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD/ VDD P0.2/ SCLK P0.3/ SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS NOTE: The bolds indicate an OTP pin name. Figure 15-4. Pin Assignment Diagram (24-Pin SOP Package) 15-4 S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P0.3 SDAT S3P9404: 28 (30) S3P9414: 22 (22) I/O Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned P0.2 SCLK S3P9404: 29 (31) S3P9414: 23 (23) I/O Serial clock pin (input only pin) TEST VPP (TEST) 4 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 7 I Chip Initialization VDD/VSS VDD/VSS I Logic power supply pin. S3P9404: 30 (32) / 1 S3P9414: 24 (24) / 1 NOTE: ( ) means the SOP OTP pin number. Table 15-2. Comparison of S3P9404/P9414and S3C9404/C9414 Features Characteristic S3P9404/P9414 S3C9404/C9414 4-Kbyte EPROM 4-Kbyte mask ROM Operating Voltage (VDD) 2.7 V to 5.5 V 2.7 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Program Memory Pin Configuration 30 SDIP/32 SOP/24 SDIP/24 SOP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P9404/P9414, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD VPP REG/MEM MEM (TEST) 5V ADDRESS R/W MODE (A15-A0) 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 15-5 S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414 NOTES 15-6