STS8C5H30L N-CHANNEL 30V - 0.018Ω - 8A SO-8 P-CHANNEL 30V - 0.045Ω - 5A SO-8 LOW GATE CHARGE StripFET™ III MOSFET Figure 1: Package Table 1: General Features TYPE VDSS RDS(on) ID STS8C5H30L (N-Channel) STS8C5H30L (P-Channel) 30 V 30 V < 0.022 Ω < 0.055 Ω 8A 5A ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) (N-Channel) = 0.018 Ω TYPICAL RDS(on) (P-Channel) = 0.045 Ω CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DRIVE STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY DESCRIPTION This MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. SO-8 Figure 2: Internal Schematic Diagram APPLICATIONS ■ DC/DC CONVERTERS ■ BATTERY MANAGEMENT IN NOMADIC EQUIPMENT ■ POWER MANAGEMENT IN CELLULAR PHONES ■ DC MOTOR DRIVE Table 2: Order Codes PART NUMBER MARKING PACKAGE PACKAGING STS8C5H30L S8C5H30L SO-8 TAPE & REEL Rev. 2 September 2004 1/11 STS8C5H30L Table 3: Absolute Maximum ratings Symbol Parameter Value N-CHANNEL VDS VDGR VGS Drain-source Voltage (VGS = 0) Unit P-CHANNEL 30 Drain-gate Voltage (RGS = 20 kΩ) V 30 Gate- source Voltage V ± 16 ± 16 V ID Drain Current (continuous) at TC = 25°C Single Operating 8 4.2 A ID Drain Current (continuous) at TC = 100°C Single Operating 6.4 3.1 A Drain Current (pulsed) 32 16.8 IDM () 1.6 2 150 -55 to 150 °C °C Rthj-case Thermal Resistance Junction-case Single Operating Dual Operating 62.5 78 °C/W °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tj Tstg Total Dissipation at TC = 25°C Dual Operating Total Dissipation at TC = 25°C Single Operating A W W PTOT Operating Junction Temperature Storage Temperature () Pulse width limited by safe operating area Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed Table 4: Thermal Data Tl ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 n-ch p-ch IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS= Max Rating VDS= Max Rating, TC= 125°C n-ch p-ch 1 10 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS= ± 16V VGS= ± 16V n-ch p-ch ±100 ±100 nA nA Gate Threshold Voltage VDS = VGS, ID= 250 µA n-ch p-ch 1.6 2.5 V V 0.018 0.045 0.020 0.070 0.022 0.055 0.025 0.075 Ω Ω Ω Ω Typ. Max. Unit V(BR)DSS VGS(th) RDS(on) Static Drain-source On Resistance VGS= VGS= VGS= VGS= 10 V, ID= 4 A 10 V, ID= 2.5 A 4.5 V, ID= 4 A 4.5 V, ID= 2.5 A 30 30 Unit 1 1 n-ch p-ch n-ch p-ch V Table 6: Dynamic Symbol Parameter Test Conditions Min. gfs (1) Forward Transconductance VDS = 15 V, ID= 4 A VDS = 15 V, ID= 2.5 A n-ch p-ch 8.5 10 S S Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 n-ch p-ch 857 1350 pF pF Coss Output Capacitance n-ch p-ch 147 490 pF pF Crss Reverse Transfer Capacitance n-ch p-ch 20 130 pF pF (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 2/11 STS8C5H30L ELECTRICAL CHARACTERISTICS(CONTINUED) Table 7: Switching On Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. Typ. Max. Unit VDD = 15 V, ID = 4 A, RG= 4.7 Ω, VGS = 4.5 V n-ch p-ch 12 25 ns ns P-CHANNEL VDD = 15 V, ID = 2 A, RG= 4.7 Ω, VGS = 4.5 V (Resistive Load see, Figure 28) n-ch p-ch 14.5 35 ns ns VDD= 24 V, ID= 8 A, VGS= 5 V n-ch p-ch 7 12.5 n-ch p-ch 2.5 5 nC nC n-ch p-ch 2.3 3 nC nC P-CHANNEL VDD = 24 V, ID = 4 A, VGS = 5 V (see, Figure 31) 10 16 nC nC Table 8: Switching Off Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. Typ. Max. Unit VDD = 15 V, ID = 4 A, RG= 4.7 Ω, VGS = 4.5 V n-ch p-ch 23 125 ns ns P-CHANNEL VDD = 15 V, ID = 2.5 A, RG= 4.7 Ω, VGS = 4.5 V (Resistive Load see, Figure 28) n-ch p-ch 8 35 ns ns Table 9: Source-Drain Diodef Symbol Max. Unit Source-drain Current n-ch p-ch 8 5 A A ISDM (2) Source-drain Current (pulsed) n-ch p-ch 32 20 A A VSD (1) Forward On Voltage ISD = 8 A, VGS = 0 ISD = 5 A, VGS = 0 n-ch p-ch 1.5 1.2 V V trr Reverse Recovery Time ISD = 8 A, di/dt = 100 A/µs VDD = 15V, Tj = 150°C n-ch p-ch 15 45 ns ns Qrr Reverse Recovery Charge n-ch p-ch 5.7 36 nC nC IRRM Reverse Recovery Current n-ch p-ch 0.76 1.6 A A ISD Parameter Test Conditions P-CHANNEL ISD = 5 A, di/dt = 100 A/µs VDD = 15V, Tj = 150°C (see test circuit, Figure 29) Min. Typ. (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. (3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 3/11 STS8C5H30L Figure 3: .Safe Operating n-channel Figure 6: Thermal Impedance For Complementary Pair Figure 4: Output Characteristics n-channel Figure 7: Transfer Characteristics n-channel Figure 5: Transconductance n-channel Figure 8: Static Drain-Source On Resistance nchannel 4/11 STS8C5H30L Figure 9: Gate Charge vs Gate-Source Voltage n-channel Figure 12: Capacitance Variations n-channel Figure 10: Normalized Gate Thereshold Voltage vs Temperature n-channel Figure 13: Normalized On Resistance vs Temperature n-channel Figure 11: Source-Drain Forward Characteristics n-channel Figure 14: Normalized BVdss vs Temperature n-channel 5/11 STS8C5H30L Figure 15: Safe Operating p-channel Figure 18: Thermal Impedance for Complementary Pair Figure 16: Output Characteristics p-channel Figure 19: Transfer Characteristics p-channel Figure 17: Transconductance p-channel Figure 20: Static Drain-Source On Resistance p-channel 6/11 STS8C5H30L Figure 21: Gate Charge vs Gate-Source Voltage p-channel Figure 24: Capacitances Variations p-channel Figure 22: Normalized Gate Thereshlod Voltage vs Temperature p-channel Figure 25: Normalized On Resistance vs Temperature p-channel Figure 23: Source-Drain Diode Forward Characteristics p-channel Figure 26: Normalized BVdss vs Temperature p-channel 7/11 STS8C5H30L Figure 27: Unclamped Inductive Load Test Circuit Figure 30: Unclamped Inductive Wafeform Figure 28: Switching Times Test Circuit For Resistive Load Figure 31: Gate Charge Test Circuit Figure 29: Test Circuit For Inductive Load Switching and Diode Recovery Times 8/11 STS8C5H30L SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.25 a2 MAX. 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 c1 45 (typ.) 1.27 e e3 3.81 0.150 F 3.8 4.0 0.14 L 0.4 1.27 0.015 M S 0.244 0.050 0.6 0.157 0.050 0.023 8 (max.) 9/11 STS8C5H30L Table 10: Revision History Date Revision 10-Aug-2004 10-Sep-2004 1 2 10/11 Description of Changes First Revision Complete Version STS8C5H30L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 11/11