NEC UPA2711GR

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA2711GR
SWITCHING
P-CHANNEL POWER MOS FET
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µ PA2711GR is P-Channel MOS Field Effect Transistor
designed for power management applications of notebook
computers and Li-ion battery protection circuit.
8
5
1, 2, 3
: Source
4
: Gate
5, 6, 7, 8 : Drain
FEATURES
• Low on-state resistance
RDS(on)1 = 9 mΩ MAX. (VGS = −10 V, ID = −6.5 A)
RDS(on)2 = 15 mΩ MAX. (VGS = −4.5 V, ID = −6.5 A)
RDS(on)3 = 20 mΩ MAX. (VGS = −4.0 V, ID = −6.5 A)
• Low Ciss: Ciss = 2450 pF TYP.
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
µ PA2711GR
Power SOP8
6.0 ±0.3
4
4.4
5.37 MAX.
0.8
0.15
+0.10
–0.05
1.44
0.05 MIN.
1.8 MAX.
1
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
–30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
m20
V
Drain Current (DC)
ID(DC)
m13
A
Drain Current (pulse)
Note1
ID(pulse)
m52
A
Total Power Dissipation
Note2
PT1
2
W
Total Power Dissipation
Note3
PT2
2
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to + 150
°C
Single Avalanche Current
Note4
IAS
−13
A
Single Avalanche Energy
Note4
EAS
16.9
mJ
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Source
Notes 1.
2.
3.
4.
PW ≤ 10 µs, Duty Cycle ≤ 1%
2
Mounted on ceramic substrate of 1200 mm x 2.2 mm
Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec
Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V
Remark
Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G15979EJ1V0DS00 (1st edition)
Date Published March 2004 NS CP(K)
Printed in Japan
2004
µ PA2711GR
ELECTRICAL CHARACTERISTICS (TA = 25°C, Unless otherwise noted, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = −30 V, VGS = 0 V
–1
µA
Gate Leakage Current
IGSS
VGS = m20 V, VDS = 0 V
m100
µA
–2.5
V
Gate Cut-off Voltage
Forward Transfer Admittance
Note
Drain to Source On-state Resistance
Note
VGS(off)
VDS = −10 V, ID = −1 mA
–1.0
| yfs |
VDS = −10 V, ID = −6.5 A
10
RDS(on)1
VGS = −10 V, ID = −6.5 A
7.4
9
mΩ
RDS(on)2
VGS = −4.5 V, ID = −6.5 A
10
15
mΩ
RDS(on)3
VGS = −4.0 V, ID = −6.5 A
12
20
mΩ
22
S
Input Capacitance
Ciss
VDS = −10 V
2450
pF
Output Capacitance
Coss
VGS = 0 V
740
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
410
pF
Turn-on Delay Time
td(on)
VDD = −15 V, ID = −6.5 A
10
ns
VGS = −10 V
15
ns
RG = 10 Ω
230
ns
130
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = −24 V
57
nC
Gate to Source Charge
QGS
VGS = −10 V
6.3
nC
QGD
ID = −13 A
19
nC
Gate to Drain Charge
Body Diode Forward Voltage
Note
VF(S-D)
IF = 13 A, VGS = 0 V
0.81
V
Reverse Recovery Time
trr
IF = 13 A, VGS = 0 V
62
ns
Reverse Recovery Charge
Qrr
di/dt = 50 A/µs
31
nC
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
50 Ω
PG.
VGS = −20 → 0 V
VDD
RG
PG.
VGS(−)
VGS
Wave Form
0
VGS
10%
90%
VDD
VDS(−)
−
IAS
BVDSS
VDS
ID
VGS(−)
0
VDS
Wave Form
τ
VDD
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
2
IG = −2 mA
RL
50 Ω
VDD
Data Sheet G15979EJ1V0DS
VDS
90%
90%
10% 10%
0
td(on)
tr td(off)
ton
tf
toff
µ PA2711GR
ELECTRICAL CHARACTERISTICS (TA = 25°C)
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
120
2.8
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
Mounted on ceramic
substrate of
1200 mm2 x 2.2 mm
2.4
2
1.6
1.2
0.8
0.4
0
0
0
25
50
75
100
125
150
175
0
25
TA - Ambient Temperature - °C
50
75
100
125
150
175
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
-100
ID(pulse)
PW = 100 µ s
ID(DC)
-10
1 ms
DC
-1
10 ms
Power Dissipation Limited
100 ms
-0.1
Single pulse, TA = 25°C
Mounted on ceramic substrate of
1200 mm2 x 2.2 mm, 1unit
-0.01
-0.01
-0.1
-1
-10
-100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
rth(t) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
RDS(on) Limited
(at VGS = −10 V)
Rth(ch-A) = 62.5°C/W
100
10
1
0.1
Single pulse, TA = 25°C
Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
0.01
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G15979EJ1V0DS
3
µ PA2711GR
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
-60
-1000
−4.5 V
VGS = −10 V
ID - Drain Current - A
ID - Drain Current - A
-50
−4.0 V
-40
-30
-20
-100
Tch = −55°C
25°C
75°C
150°C
-10
-1
-0.1
-10
Pulsed
VDS = −10 V
Pulsed
0
-0.01
0
-0.4
-0.8
-1.2
0
-1
VDS - Drain to Source Voltage - V
-
-1.5
-1
Pulsed
VDS = −10 V
0
0
50
100
| yfs | - Forward Transfer Admittance - S
VGS(off) - Gate Cut-off Voltage - V
-2.5
-50
Tch = −55°C
25°C
75°C
150°C
10
1
Pulsed
VDS = −10 V
0.1
-0.1
150
Pulsed
25
VGS = −4.0 V
−4.5 V
−10 V
10
5
-1
-10
-100
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance - mΩ
30
0
-0.1
-10
-100
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
ID - Drain Current - A
4
-1
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
15
-5
100
Tch - Channel Temperature - °C
20
-4
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
-3
-0.5
-3
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
-2
-2
40
Pulsed
ID = −6.5 A
30
20
10
0
0
-5
-10
-15
VGS - Gate to Source Voltage - V
Data Sheet G15979EJ1V0DS
-20
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
30
10000
25
V GS = −4.0 V
−4.5 V
−10 V
15
10
5
Pulsed
ID = −6.5 A
0
-50
0
50
100
Ciss
Coss
1000
Crss
100
VGS = 0 V
f = 1 MHz
10
-0.01
150
SWITCHING CHARACTERISTICS
-10
-100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
-30
td(off)
100
tf
tr
10
td(on)
1
-0.1
-1
VDD = −15 V
VGS = −10 V
RG = 10 Ω
-10
VDS - Drain to Source Voltage - V
1000
td(on), tr, td(off), tf - Switching Time - ns
-1
VDS - Drain to Source Voltage - V
Tch - Channel Temperature - °C
-15
ID = −13 A
VDD = −24 V
−15 V
−6 V
-20
-10
-10
-5
VGS
VDS
0
-100
0
0
ID - Drain Current - A
10
20
30
40
50
60
QG - Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
100
trr - Reverse Recovery Time - ns
1000
IF - Diode Forward Current - A
-0.1
0V
VGS = −10 V
10
1
0.1
100
10
di/dt = 50 A/µs
VGS = 0 V
Pulsed
1
0.01
0
0.2
0.4
0.6
0.8
1
1.2
0.1
1
10
100
IF - Diode Forward Current - A
VF(S-D) - Source to Drain Voltage - V
Data Sheet G15979EJ1V0DS
5
VGS - Gate to Source Voltage - V
20
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
µ PA2711GR
µ PA2711GR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
120
Energy Derating Factor - %
IAS - Single Avalanche Current - A
-100
IAS = −13 A
-10
-1
EAS = 16.9 mJ
VDD = −15 V
VGS = −20 → 0 V
RG = 25 Ω
Starting Tch = 25°C
100
80
60
40
20
-0.1
10 m
0
100 m
1
10
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - °C
L - Inductive Load - H
6
VDD = −15 V
RG = 25 Ω
VGS = −20 → 0 V
IAS ≤ −13 A
Data Sheet G15979EJ1V0DS
µ PA2711GR
• The information in this document is current as of March, 2004. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
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M8E 02. 11-1