DATA SHEET MOS INTEGRATED CIRCUIT µPD17201A, 17207 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND A/D CONVERTER FOR INFRARED REMOTE CONTROL TRANSMITTERS DESCRIPTION The µPD17201A, 17207 is a 4-bit single-chip microcontroller, used for infrared remote control transmitters, which in-tegrates an LCD controller/driver, A/D converter, and remote controller carrier generator circuit on a single chip. For the CPU, this microcontroller employs the 17K architecture of the general-purpose register method, and it can directly execute operations between data memory addresses which would have been conventionally executed by an accumulator. In addition, all the instructions are 16-bit, 1-word instructions, enabling efficient programming. A one-time PROM model, µPD17P207, to which data can be written only once is also available. This one-time PROM model is useful for program evaluation of the µPD17201A or 17207. Detalied functionins are described in the following manual. Be sure to read this manual when designing your system. µPD172xx Subseries User’s Manual: IEU-1317 FEATURES • 17K architecture : General-purpose register method • Program memory (ROM) : 3072 x 16 bits (µPD17201A) • Data memory (RAM) : 336 x 4 bits (including LCD register 36 × 4 bits) 4096 x 16 bits (µPD17207) • Infrared remote controller carrier generator (REM output) • LCD controller/driver : Up to 136 segments can be displayed · Common pins : 4 (2 can be used as segment pins) · Segment pins : 34 · Voltage booster circuit for driving LCD : LCD drive voltage can be adjusted from 2.4 to 5.4 V with external resistor • 8-bit A/D converter : 4 channels (successive approximation method in software) • 8-bit timer : 1 channel • Watch timer/watchdog timer : 1 channel (WDOUT output) • 3-line serial interface : 1 channel • External interrupt pin (INT) : 1 • I/O pin : 20 (including INT) • Instruction execution time : 4 µs (main clock: fX = 4 MHz) 488 µs (subclock: fXT = 32.768 kHz) • Supply voltage : VDD = 2.2 to 5.5 V (main clock : f X = 4 MHz) : VDD = 2.0 to 5.5 V (subclock : fXT = 32.768 kHz) Unless otherwise specified, the µPD17207 is treated as the representative model throughout this documents. The information in this document is subject to change without notice. Document No. U11778EJ5V0DS00 (5th edition) (Previous No. IC-2773) Date Published November 1996 P Printed in Japan The mark shows major revised points. © 1991 µPD17201A, 17207 APPLICATIONS • Infrared remote controller for air conditioner • Infrared remote controller with LCD display ORDERING INFORMATION Part Number Pakcage µPD17201AGF-xxx-3B9 µPD17207GF-xxx-3B9 80-pin plastic QFP (14 mm x 20 mm) 80-pin plastic QFP (14 mm x 20 mm) Remark xxx indicates the ROM code number. 2 µPD17201A, 17207 TABLE OF CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ............................................................................................. 6 2. BLOCK DIAGRAM ......................................................................................................................... 8 3. PINS FUNCTIONS .......................................................................................................................... 9 3.1 PIN IDENTIFICATION ........................................................................................................................... 9 3.2 EQUIVALENT CIRCUITS OF PINS ..................................................................................................... 11 3.3 PROCESSING OF UNUSED PINS ...................................................................................................... 12 3.4 NOTES ON USING RESET AND INT PINS ........................................................................................ 13 4. MEMORY SPACE ........................................................................................................................... 14 4.1 5. 6. 7. 8. PROGRAM COUNTER (PC) ................................................................................................................ 14 4.2 PROGRAM MEMORY (ROM) .............................................................................................................. 14 4.3 STACK ................................................................................................................................................... 15 4.4 DATA MEMORY (RAM) ........................................................................................................................ 17 4.5 REGISTER FILE (RF) ........................................................................................................................... 25 PORTS ............................................................................................................................................ 28 5.1 PORT 0A ............................................................................................................................................... 28 5.2 PORT 0B ............................................................................................................................................... 28 5.3 PORT 0C ............................................................................................................................................... 28 5.4 PORT 0D ............................................................................................................................................... 28 5.5 PORT 1A ............................................................................................................................................... 29 5.6 INT PIN .................................................................................................................................................. 29 5.7 PORT CONTROL REGISTER .............................................................................................................. 30 CLOCK GENERATOR CIRCUIT .................................................................................................... 33 6.1 SWITCHING SYSTEM CLOCK ............................................................................................................ 34 6.2 MAIN CLOCK OSCILLATION CONTROL FUNCTION ....................................................................... 34 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT .................... 35 7.1 CONFIGURATION OF THE 8-BIT TIMER (WITH MODULO FUNCTION) ......................................... 35 7.2 FUNCTION OF THE 8-BIT TIMER (WITH MODULO FUNCTION) .................................................... 37 7.3 REMOTE CONTROLLER CARRIER GENERATOR ........................................................................... 38 WATCH TIMER/WATCHDOG TIMER ............................................................................................ 43 8.1 CONFIGURATION OF WATCH TIMER/WATCHDOG TIMER ............................................................ 43 8.2 FUNCTION OF WATCH TIMER/WATCHDOG TIMER ........................................................................ 44 8.3 WATCHDOG TIMER OPERATION TIMING ........................................................................................ 45 3 µPD17201A, 17207 9. A/D CONVERTER .......................................................................................................................... 46 9.1 CONFIGURATION OF A/D CONVERTER ........................................................................................... 46 9.2 FUNCTION OF A/D CONVERTER ...................................................................................................... 47 9.3 CONTROL REGISTERS OF A/D CONVERTER ................................................................................. 48 9.4 OPERATION IN A/D CONVERSION MODE ........................................................................................ 50 9.5 OPERATION IN COMPARE MODE ..................................................................................................... 52 10. SERIAL INTERFACE ..................................................................................................................... 54 10.1 SERIAL INTERFACE FUNCTION ........................................................................................................ 54 10.2 SERIAL INTERFACE OPERATION ...................................................................................................... 54 11. LCD CONTROLLER/DRIVER ........................................................................................................ 58 12. 11.1 CONFIGURATION OF LCD CONTROLLER/DRIVER ........................................................................ 58 11.2 FUNCTIONS OF LCD CONTROLLER/DRIVER .................................................................................. 59 11.3 DISPLAY MODE REGISTER ................................................................................................................ 59 11.4 LCD REGISTER .................................................................................................................................... 63 11.5 SEGMENT SIGNALS AND COMMON SIGNALS ................................................................................ 67 11.6 VOLTAGE BOOSTER CIRCUIT FOR LCD DRIVER .......................................................................... 70 INTERRUPT FUNCTIONS ............................................................................................................ 72 12.1 INTERRUPT SOURCES ....................................................................................................................... 72 12.2 HARDWARE OF INTERRUPT CONTROL CIRCUIT .......................................................................... 72 12.3 INTERRUPT SEQUENCE .................................................................................................................... 77 13. STANDBY FUNCTIONS ................................................................................................................. 78 13.1 HALT MODE .......................................................................................................................................... 78 13.2 CONDITIONS OF EXECUTING AN HALT INSTRUCTION ................................................................ 80 13.3 STOP MODE ......................................................................................................................................... 81 13.4 CONDITIONS OF EXECUTING AN HALT INSTRUCTION ................................................................ 82 14. RESET ............................................................................................................................................. 83 14.1 RESET BY RESET SIGNAL INPUT .................................................................................................... 83 14.2 RESET BY WATCHDOG TIMER (RESET AND WDOUT PINS CONNECTED) ................................ 83 14.3 RESET BY STACK POINTER (RESET AND WDOUT PINS CONNECTED) .................................... 83 15. ASSEMBLER RESERVED WORDS .............................................................................................. 85 15.1 MASK OPTION DIRECTIVES .............................................................................................................. 85 15.2 RESERVED SYMBOLS ........................................................................................................................ 86 16. INSTRUCTION SET ........................................................................................................................ 94 16.1 OUTLINE OF INSTRUCTION SETS .................................................................................................... 94 16.2 LEGEND ................................................................................................................................................ 95 16.3 LIST OF INSTRUCTION SETS ............................................................................................................ 96 16.4 ASSEMBLER (AS17K) EMBEDDED MACROINSTRUCTIONS ......................................................... 98 17. ELECTRICAL SPECIFICATIONS .................................................................................................. 99 18. PERFORMANCE CURVE (REFERENCE VALUE) ...................................................................... 106 4 µPD17201A, 17207 19. EXAMPLE OF APPLICATION CIRCUIT ....................................................................................... 110 20. PACKAGE DRAWINGS .................................................................................................................. 111 21. RECOMMENDED SOLDERING CONDITIONS............................................................................ 113 APPENDIX A. DIFFERENCES BETWEEN µPD17P207 AND µPD17201A/17207 .......................... 114 APPENDIX B. FUNCTIONAL COMPARISON OF µPD17201A/17207 RELATED PRODUCTS ...... 115 APPENDIX C. DEVELOPMENT TOOLS ............................................................................................. 116 5 µPD17201A, 17207 RESET VREG WDOUT XTIN XTOUT VLCD0 VLCDC VLCD1 VLCD2 CAPH CAPL COM0 COM1 LCD35/COM2 LCD32 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 1 LCD31 2 63 XIN LCD30 3 62 VDD LCD29 4 61 REM LCD28 5 60 P1A2/SI LCD27 6 59 P1A1/SO LCD26 7 58 P1A0/SCK LCD25 8 57 P0D3 LCD24 9 56 P0D2 LCD23 10 55 P0D1/TMOUT LCD22 11 54 P0D0/LED 53 P0C3 52 P0C2 51 P0C1 50 P0C0 49 P0B3 48 P0B2 LCD21 12 LCD20 13 LCD19 14 LCD18 15 LCD17 16 µ PD17201AGF-xxx-3B9 µ PD17207GF-xxx-3B9 XOUT 43 P0A1 23 42 P0A0 LCD9 41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GNDADC 22 LCD10 ADC3 LCD11 ADC2 P0A2 ADC1 21 44 ADC0 P0A3 LCD12 VADC 45 LCD0 20 GND P0B0 LCD13 LCD1 P0B1 46 LCD2 47 19 LCD3 18 LCD14 LCD4 LCD15 LCD5 17 LCD6 LCD16 LCD8 6 LCD34/COM3 LCD33 PIN CONFIGURATION (TOP VIEW) LCD7 1. INT µPD17201A, 17207 Pin Name ADC0-ADC3 : A/D converter input REM : Remote controller transfer output RESET : Reset signal input CAPH, CAPL : Booster capacitor connection SCK : Serial clock I/O COM0-COM3 SI : Serial data input GND, GNDADC : Ground SO : Serial data output INT : External interrupt request signal input TMOUT : Timer output LCD0-LCD35 : LCD segment signal output VADC : A/D converter power supply LED : Remote controller transfer display output VDD : Power supply P0A0-P0A3 : I/O port VLCD0-VLCD2 : LCD driver voltage output P0B0-P0B3 : I/O port VLCDC P0C0-P0C3 : I/O port VREG : Voltage regulator output P0D0-P0D3 : I/O port WDOUT : Overrun detection output P1A0-P1A2 : I/O port XIN, XOUT : Main clock oscillator circuit : LCD common signal output : LCD driver reference voltage adjustment XTIN, XTOUT : Subclock oscillator circuit 7 µPD17201A, 17207 2. BLOCK DIAGRAM VREG P1A VDD CAPH CAPL VLCD0 VLCD1 VLCD2 VLCDC GMD Serial interface LCD0 LCD1 LCD2 LCD3 LCD4 Power Supply Circuit P1A 0 /SCK P1A 1 /SO P1A 2 /SI RF RAM 336 × 4 bits LCD Controller LCD33 COM3/LCD34 COM2/LCD35 COM1 COM0 SYSTEM REG. P0A0 P0A1 P0A2 P0A3 P0A P0B0 P0B1 P0B2 P0B3 P0B ALU Interrupt Controller ROM P0C0 P0C1 P0C2 P0C3 Instruction Decoder VADC 3072 × 16 bits ( µ PD17201A) P0C INT ADC0 4096 × 16 bits ( µ PD17207) A/D Converter ADC1 ADC2 P0D0/LED P0D1/TMOUT P0D2 P0D3 ADC3 P0D GNDADC Program Counter RESET Stack 5 × 12 bits REM WDOUT Carrier Generator CPU Clock Clock Stop X IN Main clock Timer/ Counter X OUT Watch Timer Divider CPU Clock XT IN Subclock XT OUT 8 µPD17201A, 17207 3. PINS FUNCTIONS 3.1 PIN IDENTIFICATION Pin No. Symbol Function Output Type On Reset CMOS, – 76 COM0 Common/segment signal outputs of the LCD driver. These 77 COM1 common and segment signal outputs are selected by LCDMD3 to 78 LCD35/COM2 LCDMD0 of the register file. 79 LCD34/COM3 • 80 LCD33 1 LCD32 | | 32 LCD1 34 LCD0 33 GND Device ground – – 35 VADC Positive power supply of the A/D converter (VADC should be equal – – Analog inputs of the A/D converter (8-bit resolution) – – Ground of the A/D converter – – External interrupt request signal (Input). – Input CMOS, Input COM0 to COM3 • • push-pull Common signal outputs of the LCD driver LCD35 to LCD0 • Segment signal outputs of the LCD driver to VDD.) 36 ADC0 | | 39 ADC3 40 GNDADC 41 INT The interrupt request is generated at the rising edge of this signal. 42 P0A0 | | 45 P0A3 Each of these pins has a pull-up resistor. 46 P0B0 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units). N-channel, | | (Grouped I/O). open-drain 49 P0B3 50 P0C0 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units). N-channel, (Grouped I/O). open-drain | | 53 P0C3 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O). 54 P0D0/LED 55 P0D1/TMOUT P0D0 and LED outputs are switched by NRZEN of the register file. 56 P0D2 P0D1 and 8-bit timer outputs are switched by TMOE of the register 57 P0D3 file. Port 0D/LED output or port 0D/8-bit timer output. • • push-pull CMOS, Input Input Input push-pull P0D0 to P0D3 • 4-bit I/O port • Enabling setting of inputs or outputs of each bit (Bitwise I/O) LED • Outputs NRZ signal in synchronization with infrared remote controller signal (REM) • Outputs high level while remote controller carrier is output from REM pin • TMOUT • Output of the 8-bit timer (to be cont’d) 9 µPD17201A, 17207 (cont’d) Pin No. Symbol Function 58 P1A0/SCK Port 1A or serial interface. 59 P1A1/SO Port 1A and serial interface are switched by SIOEN of the register file. 60 P1A2/SI • Output Type On Reset CMOS, Input push-pull P1A0 to P1A2 • 3-bit I/O port • Enabling setting of inputs or outputs of 3 bits (Grouped I/O). • 61 REM SCK, SO, SI • SCK : Serial clock I/O • SO : Serial data output • SI : Serial data input Signal output to an infrared remote controller. Active-high output. CMOS, Low-level push-pull output 62 VDD Positive power supply – – 63 XIN These pins are connected to a 4-MHz ceramic or crystal oscillator – (Oscillation 64 XOUT 65 RESET for main clock oscillation. System reset input. stops) – Input – – N-ch High- open drain impedance – (Oscillates) System is reset when low level is input to this pin. While this pin is low, oscillation of main clock is stopped. A pull-up resistor can be connected by mask option. 66 VREG Output of the voltage regulator for the subclock oscillation circuit. Connect external 0.1-µF capacitor to this pin when using the subclock. 67 WDOUT Output for detection of a program overrun. This pin outputs a low level when an overflow in the watchdog timer or an overflow/underflow in the stack is detected. Connect this pin to the RESET pin 68 XTIN These pins are connected to a 32.768-kHz crystal oscillator for 69 XTOUT subclock oscillation. 71 VLCDC Input to regulate the reference voltage to LCD driver. – – 70 VLCD0 Reference voltage outputs to LCD driver. – – 72 VLCD1 • VLCD0: Reference voltage output 73 VLCD2 • VLCD1: Doubler output (Two times the reference voltage) – – • VLCD2: Tripler output (Three times the reference voltage) 10 74 CAPH These pins are connected to a capacitor to boost the LCD drive 75 CAPL voltage. µPD17201A, 17207 3.2 EQUIVALENT CIRCUITS OF PINS The followings are equivalent circuits (partially simplified) of the respective pins of the µPD17207. (1) P0A (4) P0D, P1A VDD data Output latch P-ch N-ch output disable VDD VDD data P-ch N-ch output disable Selector Selector Input buffer Input buffer (2) P0B data Output latch (5) RESET VDD Output latch (Mask option) N-ch output disable Input buffer Schmitt trigger input with hysteresis characteristics Input buffer (3) P0C data (6) INT Output latch N-ch output disable Input buffer Schmitt trigger input with hysteresis characteristics Selector Input buffer 11 µPD17201A, 17207 3.3 PROCESSING OF UNUSED PINS Process unused pins as follows: Table 3-1 Processing of Unused Pins (a) Port pins Pin Name Recommended Processing of Unused Pins Internally Input mode Output mode (Connect pull-up resistor.) P0C – Directly connect to GND. P0D, P1A – Connect each pin to VDD or GND via resistorNote. P0A (CMOS port) Outputs high level. P0D, P1A (CMOS port) Open. Open. – P0B, P0C (N-ch open-drain port) Note Externally P0A Outputs low level. When pulling this pin up (connecting the pin to VDD via resistor) or down (connect the pin to GND via resistor), exercise care not to decrease the drive capability or increase the power consumption of the port. When a high resistance is used for pulling up or down, make sure that noise is not superimposed on the pin. (b) Pins other than port pins Pin Name ADC0-ADC3 I/O Format Input Recommended Processing of Unused Pin Directly connect to GND. CAPH, CAPL Output Open COM0, COM1, COM2/LCD35, COM3/LCD34 Output Open INT Note Input Directly connect to GND. LCD0-LCD33 Output Open REM Output Open VADC – VLCD0-VLCD2 Output VLCDC – Directly connect to VDD. Open Directly connect to VDD or VLCD0. WDOUT Output Directly connect to GND. XIN, XTIN Input Directly connect to GND. XOUT – Directly connect to VDD. XTOUT – Directly connect to VREG. Note Because the INT pin is also used as a test mode setting pin, directly connect this pin to GND when it is not used. Cautions 1. It is recommended to fix the input or output mode and the output level of the pin by repeatedly setting them in each loop of the program. 2. Stop the voltage booster circuit by using the display mode register when the LCD driver/ controller is not in use. 12 µPD17201A, 17207 3.4 NOTES ON USING RESET AND INT PINS In addition to the functions shown in 3.1 PIN IDENTIFICATION, the RESET and INT pins also have a function to set a test mode (for IC testing) in which the internal operations of the µPD17207are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the µPD17207 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between VDD and RESET/INT pin • Connect capacitor between VDD and RESET/INT pin VDD VDD Diode with low VF VDD RESET, INT VDD RESET, INT 13 µPD17201A, 17207 4. 4.1 MEMORY SPACE PROGRAM COUNTER (PC) The program counter (PC) specifies an address of the program memory (ROM). The program counter is a 12-bit binary counter as shown in Fig. 4-1. Its contents are initialized to address 0000H at reset. Fig. 4-1 Configuration of Program Counter Page PC MSB LSB PC11 PC10 4.2 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PROGRAM MEMORY (ROM) The configuration of the program memory of the µPD17201A/17207 is as follows: Part Number Capacity Address µPD17201A 3072 x 16 bits 0000H-0BFFH µPD17207 4096 x 16 bits 0000H-0FFFH The program memory stores a program, interrupt vector table, and fixed data table. The program memory is addressed by the program counter. Fig. 4-2 shows the program memory map. The entire range of the program memory can be addressed by the BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry addresses that can be specified by the CALL addr instruction are from 0000H to 07FFH. Fig. 4-2 Program Memory Map Address 16 bits 0000H Reset start address 0001H Serial interface interrupt vector 0002H Watch timer interrupt vector 0003H External input (INT) interrupt vector 0004H 8-bit timer interrupt vector Branch addresses for BR addr instruction Page 0 Branch addresses for BR @AR instruction Subroutine entry addresses for CALL @AR instruction 07FFH 0BFFH ( µ PD17201A) 0FFFH ( µ PD17207) 14 Subroutine entry addresses for CALL addr instruction Page 1 Table reference addresses for MOVT DBF, @AR instruction µPD17201A, 17207 4.3 STACK A stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 4.3.1 Stack Configuration A stack consists of a stack pointer (a 3-bit binary counter), five 12-bit address stack registers (ASR), and three 7-bit interrupt stack registers (INTSK). Refer to Fig. 4-3. The stack pointer specifies the addresses of the address stack registers. The value of this pointer is initialized to 5H at reset. When the value of the stack pointer is 6H or 7H, the WDOUT pin goes low. Fig. 4-3 Stack Configuration Stack Pointer (SP) b2 b1 b0 SPb 2 SPb 1 SPb 0 WDOUT pin goes low when the contents of the stack pointer are 6H-7H. Address Stack Registers (ASR) b 11 b 10 b9 b8 b7 b6 b5 b4 b3 0H Address stack register 0 1H Address stack register 1 2H Address stack register 2 3H Address stack register 3 4H Address stack register 4 5H Undefined 6H Undefined 7H Undefined b2 b1 b0 Interrupt Stack Registers (INTSK) 0H BANKSK0 BCDSK0 CMPSK0 CYSK0 ZSK0 IXESK0 1H BANKSK1 BCDSK1 CMPSK1 CYSK1 ZSK1 IXESK1 2H BANKSK2 BCDSK2 CMPSK2 CYSK2 ZSK2 IXESK2 Fig. 4-4 Stack Pointer RF: address 01 Bit 3 Bit 2 Bit 1 0 SP Read/write Initial value at reset Bit 0 R/W 0 1 Read = R, Write = W 0 1 15 µPD17201A, 17207 4.3.2 Function of Stack The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. It also stores the contents of the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed. The WDOUT pin goes low if a subroutine call or interrupt exceeding 5 levels is executed. The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word (PSWORD) when an interrupt is accepted. The saved contents are restored when an interrupt return (RETI) instruction is executed. INTSK saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur. 4.3.3 Stack Pointer (SP) and Interrupt Stack Pointer Table 4-1 shows the operations of the stack pointer (SP). The stack pointer can take eight values, 0H-07. Because there are only five stack registers available, however, the WDOUT pin goes low if the value of SP is 6 or greater. Table 4-1 Operations of Stack Pointer Instruction Value of Stack Pointer (SP) Counter of Interrupt Stack Register –1 0 –1 –1 +1 0 +1 +1 CALL addr CALL @AR MOVT DBF, @AR (1st Instruction Cycle) PUSH AR When Interrupt Is Accepted RET RETSK MOVT DBF, @AR (2nd Instruction Cycle) POP AR RETI 16 µPD17201A, 17207 4.4. DATA MEMORY (RAM) Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by instructions. 4.4.1 Memory Configuration Figure 4-4 shows the configuration of the data memory (RAM). The data memory consists of three “banks”: BANK0, BANK1, and BANK2. In each bank, every 4 bits of data is assigned an address. The higher 3 bits of the address indicate a “row address” and the lower 4 bits of the address indicate a “column address”. For example, a data memory location indicated by row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data of 4 bits (= a “nibble”). In addition, the data memory is divided into following six functional blocks: (1) System register (SYSREG) A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles long) of each bank. In other nibbles, each bank has a system register at its addresses 74H to 7FH. (2) Data buffer (DBF) A data buffer is resident on addresses 0CH to 0FH (4 nibbles long) of bank 0 of data memory. The reset value is 0320H. (3) General register (GR) A general register is resident on any row (16 nibbles long) of any bank of data memory. The row address of the general register is indicated by the general pointer (RP) in the system register (SYSREG). (4) LCD segment data register (LCD register) A register sets the segment output data of LCD. Refer to 11. LCD CONTROLLER/DRIVER. An LCD segment data register is resident on addresses 40H to 63H (36 nibbles long) of BANK0 of data memory. (5) Port register A port data register is resident on addresses 70H to 73H (12 nibbles) of each bank of data memory. However, addresses 71H to 73H of BANK1 and addresses 70H to 73H of BANK2 are assigned nothing. Therefore, a port data register is substantially 4 nibbles long. The reset value is 0. 17 µPD17201A, 17207 (6) General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, the LCD register area, and the port register area. This memory area has a total of 300 nibbles (76 nibbles in BANK0 and 224 nibbles in BANK1 and BANK2). Fig. 4-5 Configuration of Data Memory BANK 0 Column address 0 1 2 3 4 5 6 7 8 9 A B Row address 0 C D E F Data buffer (DBF) 1 Example: Address 1AH in BANK 0 2 3 4 LCD register 5 6 7 P0A P0B P0C P0D System register (SYSREG) 0 1 2 3 4 5 6 7 BANK 1 8 9 A B C D E F D E F Row address 0 1 2 3 4 5 6 7 P1A System register (SYSREG) 0 1 2 3 4 5 6 7 BANK 2 8 9 A B C Row address 0 1 2 3 4 5 6 7 System register (SYSREG) 18 µPD17201A, 17207 4.4.2 System Registers (SYSREG) The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H-7FH on the data memory and can be referenced regardless of bank specification. The system registers include the following registers: Address registers (AR0-AR3) Window register (WR) Bank register (BANK) Memory pointer enable flag (MPE) Memory pointers (MPH, MPL) Index registers (IXH, IXM, IXL) General register pointers (RPH, RPL) Program status word (PSWORD) Fig. 4-6 Configuration of System Register Address 74H Bit 76H AR 3 AR 2 AR 1 Initial Value At Reset 78H 79H Window Bank register register (WR) (BANK) AR 0 WR BANK 7AH 7BH 7CH 7DH Index register (IX) General register pointer (RP) Data memory row address pointer (MP) IXH IXM MPH MPL 7EH IXL RPH 7FH Program status word (PSWORD) RPL PSW b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 (AR) Data 77H Address register (AR) Name Symbol 75H 0 0 0 0 (BANK) 0 0 M P 0 0 E (IX) 0 0 (MP) (RP) I B CC CM Y Z X E D P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 µPD17201A, 17207 4.4.3 General Register (GR) A general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 4-7 shows the configuration of the general register. A general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory. The row address is selected by the general register pointer (RP) of the system register. The RP having five significant bits can point to any row address in the range of 0H to 7H of each bank (BANK0 to BANK2). (2) Functions of the general register The general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. As a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. Similarly, the general register can be accessed by a Data Memory Manipulation instruction as it is a part of the data memory. 20 µPD17201A, 17207 Fig. 4-7 Configuration of General Registers General register pointer (RP) RPH RPL Column address BANK0 b3 b2 b1 b0 b3 b2 b1 b0 0 F i x e d F i x e d 0 0 0 0 0 →0 0 0 0 0 1 →1 0 0 0 1 0 →2 t o t o 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 A s s i g n e d 1 2 3 4 5 6 7 8 9 A B C D E F ← Example: General registers when RP = 0000010B General registers (16 nibbles) →3 →4 →5 →6 → 7 Port register BANK1 t → o → B C → D → 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 f →4 l →5 a g →6 0 1 1 1 1 →7 System registers RP General register settable range 0 1 2 Same system registers exist 3 Port register System registers BANK2 1 0 0 0 0 →0 1 0 0 0 1 →1 1 0 0 1 0 →2 1 0 0 1 1 →3 1 0 1 0 0 →4 1 0 1 0 1 →5 1 0 1 1 0 →6 1 0 1 1 1 →7 System registers 21 µPD17201A, 17207 4.4.4 Data Buffer (DBF) The data buffer on the data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) Functions of the Data Buffer The data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). Figure 4-8 shows the relationship between the data buffer and peripheral hardware. Fig. 4-8 Data Buffer and Peripheral Hardware Data buffer (DBF) Peripheral address Internal bus Program memory (ROM) 01 H Peripheral hardware Serial interface (SIOSFR) 02 H 8-bit timer (TMC, TMM) 03 H/04 H Carrier generator for remote controller 05H A/D converter (ADCR) 40H Address register (AR) Constant data 22 µPD17201A, 17207 Table 4-2 Relations between Peripheral Hardware and Data Buffer Peripheral Registers Transferring Data with Data Buffer Peripheral Hardware Name Symbol Peripheral Address Data Buffer Used Execution of Put/Get Serial Interface Shift Register SIOSFR 01H DBF0, DBF1 Both PUT & GET 8-bit Timer 8-bit counter TMC 02H DBF0, DBF1 Only GET 8-bit modulo register TMM 02H DBF0, DBF1 Only PUT Remote Controller Carrier Generator NRZ low-level period setting modulo register NRZLTMM 03H DBF0, DBF1 Both PUT & GET Circuit NRZ high-level period setting modulo register NRZHTMM 04H DBF0, DBF1 PUT (Clears bits 2 and 3 of DBF1 to 0.) GET (Always clears bits 2 and 3 of DBF1 to 0.) A/D Converter A/D converter internal reference voltage setting register ADCR 05H DBF0, DBF1 Both PUT & GET Address Register Address register AR 40H DBF0-DBF3 PUT (Bits 0-3 of AR3 are don’t care.) GET (Always clears bits 0-3 of AR3 to 0.) (2) Table reference A MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets it in the data buffer. The function of the MOVT instruction is explained below. MOVT DBF,@AR: Reads data from a program memory location pointed to by the address register (AR) and sets it in the data buffer (DBF). Data buffer DBF 3 DBF 2 DBF 1 DBF 0 Program memory (ROM) MOVT DBF, @ AR 16 bits b15 b0 23 µPD17201A, 17207 (3) Note on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as follows: • When device operates Nothing changes even if data is written to the read-only register. If the unused address is read, an undefined value is read. Nothing changes even if data is written to that address. • Using 17K Series assembler An error occurs if an instruction is executed to read a write-only register. Again, an error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. • If an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur. 24 µPD17201A, 17207 4.5 REGISTER FILE (RF) The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of AS17K, SETn, CLRn, and INITFLG. 4.5.1 Configuration of Register File Fig. 4-9 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE instructions. The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are assigned to addresses 00H-3FH regardless of the bank, the addresses 00H-3FH of the general-purpose data memory cannot be accessed when the PEEK or POKE instruction is used. The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH of the control registers and 40H-7FH of the general-purpose data memory. The register file consists of these addresses. The control registers are assigned to addresses 80H-BFH on the IE-17K to facilitate debugging. Fig. 4-9 Configuration of Register File and Accessing Register File by PEEK and POKE Instructions BANK0 Column address 0 1 2 3 4 5 6 0 7 9 8 A B C D E F Data memory 1 R o w 2 a d d r e s s 4 LD M030, WR 5 POKE PEEK RF73, WR WR, RF70 ST 3 WR, M032 6 7 WR System registers 0 1 PEEK WR, RF11 2 3 POKE RF33, WR Control registers Register file 25 µPD17201A, 17207 4.5.2 Control Registers The control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00H-3FH of the register file. Of these, however, only 20 nibbles are actually used. The remaining 44 nibbles are unused registers that are inhibited from being read or written. When the “PEEK WR, rf” instruction is executed, the contents of the register file addressed by “rf” are read to the window register. When the “POKE rf, WR” instruction is executed, the contents of the window register are written to the register file addressed by “rf”. When using the 17K series assembler, the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated in bit units. For the configuration of the control register, refer to Fig. 15-1 Register File List. SETn : Sets flag to “1” CLRn : Sets flag to “0” SKTn : Skips if all flags are “1” SKFn : Skips if all flags are “0” NOTn : Complements flag INITFLG : Initializes flag 4.5.3 Notes on Using Register Files When using the register files, bear in mind the points described below. For details, refer to µPD172xx Subseries User’s Manual. (1) When manipulating control registers (read-only and unused registers) When manipulating the read-only (R) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: • When device operates Nothing changes even if data is written to the read-only register. If the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. • Using 17K series assembler An error occurs if an instruction is executed to write data to the read-only register. An error also occurs if an instruction is executed to read or write the unused address. • When an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) Nothing changes even if data is written to the read-only register, and an error does not occur. An undefined value is read if the unused address is read; nothing changes even if data is written to this address. An error does not occur. 26 µPD17201A, 17207 (2) Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand “rf” of the “PEEK WR, rf” or “POKE rf, WR” instruction if the 17K Series Assembler is being used. Therefore, the addresses of the register file must be defined in advance as symbols. To define the addresses of the control registers as symbols, define them as the addresses 80H-BFH of BANK0. The portion of the register file overlapping the data memory (40H-7FH), however, can be defined as symbols as is. 27 µPD17201A, 17207 5. PORTS 5.1 PORT 0A This port is a 4-bit I/O port. The four bits of this port are assigned all inputs or all outputs. This assignment is performed by P0AGIO of the register file. Transferring data from and to this port is performed via the P0A port register (address 70H of BANK0). This port is set in the input mode at reset. This port can release the standby mode when the standby mode has been set and if all the bits of the port are not set at high level. This port is connected to the pull-up resistor regardless of whether the input or output mode is specified. 5.2 PORT 0B This port is a 4-bit I/O port. The four bits of this port are assigned all inputs or all outputs. This assignment is performed by P0BGIO of the register file. Transferring data from and to this port is performed via the P0B port register (address 71H of BANK0). This port is set in the input mode at reset. This port can release the standby mode when the standby mode has been set and if all the bits of the port are not at low level. In the output mode, this port requires an external pull-up resistor because it works as an N-ch open-drain output. 5.3 PORT 0C This port is a 4-bit I/O port. The four bits of this port are assigned all inputs or all outputs. This assignment is performed by P0CGIO of the register file. Transferring data from and to this port is performed via the P0C port register (address 72H of BANK0). This port is set in the input mode at reset. In the output mode, this port requires an external pull-up resistor because it works as an N-ch open-drain output. 5.4 PORT 0D This port works as a 4-bit I/O port, an LED output, and an external signal output for the 8-bit timer. One of these functions is selected by NRZEN and TMOE of the register file. (1) Using the whole port as a 4-bit I/O port The pins of this port can be individually assigned input or output. This assignment is performed by P0DBIO3 to P0DBIO0 of the register file. Transferring data from and to this port is performed via the P0D (address 73H of BANK0). (2) Using the P0D0 pin as an LED output The LED output pin and the I/O port (P0D0) pins are selected by NRZEN. The LED output pin outputs an NRZ signal in synchronization with the REM output. (3) Using the P0D1 pin as an external signal output for the 8-bit timer The external signal output pin for the 8-bit timer and the I/O port (P0D1) pins are selected by TMOE. 28 µPD17201A, 17207 5.5 PORT 1A This port works as a 3-bit general I/O port and as serial interface. The I/O port or serial interface is selected by SIOEN of the register file. (1) Using the port 1A as a 3-bit I/O port The three bits of the port 1A can be assigned all inputs or all outputs. This assignment is performed by P1AGIO of the register file. Transferring data from and to this port is performed via the P1A (address 70H of BANK1). (2) Using port 1A as serial interface Serial interface or the I/O port (P1A0, P1A1, and P1A2) is selected by SION. 5.6 INT PIN This pin inputs an external interrupt request signal. At the rising edge of the signal input to this pin, the IRQ flag (RF: address 3DH, bit 1) is set. The status of the pin can be read by using the INT flag (RF: address 0FH, bit 0). When a high level is input to the INT pin, the INT flag is set to “1”; when a low level is input, the INT flag is reset to “0” (refer to Fig. 12-1 INT Flag). Table 5-1 Relations between Port Registers and Pins Bank Address 70H 71H Port Port 0A Port 0B 0 72H 73H 1 70H Port 0C Port 0D Port 1A b3 P0A3 b2 P0A2 CMOS b1 P0A1 push-pull b0 P0A0 b3 P0B3 b2 P0B2 N-ch b1 P0B1 open-drain b0 P0B0 b3 P0C3 b2 P0C2 N-ch b1 P0C1 open-drain b0 P0C0 b3 P0D3 b2 P0D2 Note1 b1 P0D1 b0 P0D0Note1 b3 – b2 P1A2Note2 b1 P1A1 Note2 P1A0 Note2 b0 Notes 1. Output Format Bit Read Contents Input mode Output mode Written Contents Input mode At Reset Output mode Input mode (w/pull-up resistor) Output latch Pin status Pin status Output latch Input mode CMOS Output latch push-pull CMOS push-pull When the NRZEN and TMOE flags are set to 1, the output latch is accessed both when these port pins are read and when they are written, regardless of whether the input or output mode is set. 2. When the SIOEN flag is set to 1, these pins serve as serial interface pins. In this case, the statuses of the pins are read when the pins are read, regardless of the input or output mode. Data written to these pins is invalid. 29 µPD17201A, 17207 5.7 PORT CONTROL REGISTER 5.7.1 Switching between Input and Output of Grouped I/O Port A grouped I/O port is a port whose four bits are assigned all inputs or all outputs at a time. Grouped I/O ports are P0A, P0B, P0C, P0D, and P1A. Their selection of inputs or outputs is performed by the following I/O control register. When the bits of each port are assigned from inputs to outputs, its output latch is output to the port. Fig. 5-1 I/O Control Register for Grouped I/O Ports RF: Address 37H Read/write Default at reset Bit 3 Bit 2 Bit 1 Bit 0 P1AGIO P0CGIO P0BGIO P0AGIO R/W R/W R/W R/W 0 0 0 0 R: Read, W: Write P0AGIO Function 0 Places port 0A in input mode 1 Places port 0A in output mode P0BGIO Function 0 Places port 0B in input mode 1 Places port 0B in output mode P0CGIO Function 0 Places port 0C in input mode 1 Places port 0C in output mode P1AGIO Function 30 0 Places port 1A in input mode 1 Places port 1A in output mode µPD17201A, 17207 5.7.2 Switching between Input and Output of Bitwise I/O Port A bitwise I/O port is a port whose four bits are individually assigned inputs or output. The µPD17207 supports only one bitwise I/O port: P0D. The bitwise input/output selection is performed by the following I/O control register. When the bits of this port are assigned from inputs to outputs, output latches of P0A, P0B, P0C, P0D, and P1A are output to the corresponding ports. Fig. 5-2 I/O Control Register for Bitwise I/O Ports RF: Address 27H Read/write Default at reset Bit 3 Bit 2 Bit 1 Bit 0 P0DBIO 3 P0DBIO 2 P0DBIO 1 P0DBIO 0 R/W R/W R/W R/W 0 0 0 0 R: Read, W: Write P0DBIO0 Function 0 Places P0D0 in input mode 1 Places P0D0 in output mode P0DBIO1 Function 0 Places P0D1 in input mode 1 Places P0D1 in output mode P0DBIO2 Function 0 Places P0D2 in input mode 1 Places P0D2 in output mode P0DBIO3 Function 0 Places P0D3 in input mode 1 Places P0D3 in output mode 31 µPD17201A, 17207 5.7.3 Switching among Port, Timer Output, and LED Output The functions of port 0D (port, timer output, and LED output) are selected by settings of the TMOE and NRZEN bits of register file (TMOE for P0D1 and NRZEN for P0D0). Refer to Fig. 5-3. 5.7.4 Switching between Port and Serial Interface The functions of port 1A (port and serial interface) are selected by settings of the SIOEN bit of register file. Refer to Fig. 5-3. The mode of serial interface is controlled by SIOTS (bit 3 of address 22H), SIOHIZ (bit 2 of address 22H), SIOCK1 (bit 1 of address 22H), and SIOCK0 (bit 0 of address 22H) of register file. Fig. 5-3 Input/Output Control Register for Selection of Port, Timer Output, LED Output, and Serial Interface Bit 3 Bit 2 Bit 1 Bit 0 0 NRZEN TMOE SIOEN Read/write R R/W R/W R/W Default at reset 0 0 0 0 RF: Address 23H R: Read, W: Write SIOEN Function 0 Uses port 1A as I / O port 1 Uses port 1A as serial interface TMOE Function 0 Uses P0D1 as I / O port 1 Uses P0D1 external signel output for 8-bit timer’s NRZEN Function 32 0 Uses P0D0 as I / O port 1 Uses P0D0 as LED output µPD17201A, 17207 6. CLOCK GENERATOR CIRCUIT The µPD17207 contains two types of oscillator circuits: the main clock (X) and the subclock (XT) oscillator circuits. The clock oscillated by either of the circuits can be used as the system clock. Figure 6-1 shows the configuration of the system clock control register. Whether the main or subclock is used as the system clock is specified by the SYSCK flag (RF: address 02H, bit 1). By resetting the XEN flag (RF: address 02H, bit 0), oscillation of the main clock can be stopped to reduce current dissipation. To use the subclock, be sure to connect a 0.1-µF capacitor to the VREG pin to stabilize the oscillation of the subclock. When the subclock is not used (which is specified by mask option), connect the XTIN pin to GND, and XTOUT pin to VREG pin. Fig. 6-1 System Clock Control Register RF: Address 02H Bit 3 Bit 2 Bit 1 Bit 0 0 0 SYSCK XEN Read/write R: Read, W: Write R/W Default at reset 0 0 Refer to the table below. (by mask option) Function XEN 0 Stops main clock 1 Oscillates main clock Function SYSCK Specifies mask option Main clock Used (USEX) Not used (NOX) Note Subclock 0 Selects subclock as system clock 1 Selects main clock as system clock Initial value at reset Remark SYSCK XEN Used (USEXT) 1 1 Value can be changedNote Not used (NOXT) 1 1 Fixed value (cannot be Used (USEXT) 0 0 changed in software) SYSCK cannot be changed to 1 and XEN cannot be changed to 0. 33 µPD17201A, 17207 6.1 SWITCHING SYSTEM CLOCK The system clock can be switched between the main clock and subclock by using the SYSCK flag (RF: address 02H, bit 1) as shown in Fig. 6-1. (1) Switching from main clock to subclock The system clock can be changed from the main clock to subclock by resetting the SYSCK flag to “0”. When NOXT is set by mask option, however, the subclock cannot be selected (SYSCK and XEN cannot be reset to “0”). Caution When turning on the power, make sure that a sufficient time elapses to stabilize the oscillation of the subclock (confirm that the IRQWTM flag (RF: address 3CH, bit 2) is set by the program at a specific cycle). (2) Switching from subclock to main clock The system clock can be changed from the subclock to the main clock by setting the SYSCK flag to “1”. When NOX is set by mask option, however, the main clock cannot be selected (SYSCK and XEN cannot be set to “1”). Caution Before setting the SYSCK flag, make sure that at least 10 ms elapses after the XEN flag has been set to “1” so that the oscillation stabilizes. 6.2 MAIN CLOCK OSCILLATION CONTROL FUNCTION When the subclock is used as the system clock, oscillation of the main clock can be controlled by manipulating the XEN flag (RF: address 02H, bit 0). If the system clock is changed from the subclock to main clock (by setting the SYSCK flag) after the main clock is started (by setting the XEN flag), make sure that an oscillation stabilization time of about 10 ms elapses. Caution Do not manipulate the XEN and SYSCK flags simultaneously (execute the POKE instruction twice). 34 µPD17201A, 17207 7. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT The 8-bit timer is mainly used to generate the leader pulse of the remote controller signal, and to output codes. Operations of timers are controlled by the GET instruction, the PUT instruction, and registers on the register file. 7.1 CONFIGURATION OF THE 8-BIT TIMER (WITH MODULO FUNCTION) Figure 7-1 shows the functional block diagram of the 8-bit timer. The 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a comparator which compares the contents of the timer with the contents of the modulo register, and a selector which selects a count clock of the 8-bit timer. Starting/stopping of the 8-bit timer and resetting of the 8-bit counter are controlled by TMEN (bit 3 of address 33H) and TMRES (bit 2 of address 33H) of the register file. The count clock of the 8-bit timer is selected by TMCK1 (bit 1 of address 33H) and TMCK0 (bit 0 of address 33H) of the register file. The contents of the 8-bit counter are read via the data buffer (DBF) by the GET instruction. The user cannot write any value in the 8-bit counter. The user can set a value in the modulo register by the PUT instruction via the data buffer (DBF). The user cannot read the contents of the modulo register. As the 8-bit counter (TMC) and the modulo register (TMM) use an identical address, the CPU accesses the 8-bit counter to read and the 8-bit modulo register to write. When the current count value of the counter and the value of the modulo register coincide with each other, the interrupt request flag (IRQTM: address 3EH, bit 0) is set, reflecting the output of the POD1/TMOUT pin. TMOUT is initialized and outputs a high level when TMRES is set. TMC 7 6 5 4 3 2 1 0 Address Peripheral register: 02H 8-bit counter At reset R/W 00H R At reset R/W FFH W TMM 7 6 5 4 3 2 8-bit modulo register 1 0 Address Peripheral register: 02H Caution Do not clear TMM to 0 (IRQTM cannot be set.) 35 µPD17201A, 17207 Fig. 7-1 Configuration of 8-Bit Timer and Remote Controller Carrier Generator Circuit Data buffer Internal bus 8-bit timer RF: 33H TMEN TMRES TMCK1 IRQTM 8-bit modulo register TMM fsys/32 Selector fsys/64 fsys//256 R TMCK0 P0D1/ TMOUT pin TOUT F/F Comparator Q 8-bit counter TMC S Remote controller carrier generator circuit fsys/2 SW 6-bit counter RF: 11H Comparator NRZBF RF: 12H 6-bit modulo register NRZLTMM 6-bit counter Comparator 6-bit modulo register NRZHTMM Remarks 1. 2. 36 fSYS (system clock frequency): fX or fXT TMM, TMC, NRZLTMM and NRZHTMM are peripheral register. NRZ LED REM µPD17201A, 17207 7.2 FUNCTION OF THE 8-BIT TIMER (WITH MODULO FUNCTION) Fig. 7-2 8-Bit Timer Control Register Bit 3 Bit 2 Bit 1 Bit 0 TMEN TMRES TMCK1 TMCK0 Read/write R/W W R/W R/W Default at reset 1Note 0 0 0 RF: Address 33H R: Read, W: Write TMCK 1, TMCK 0 Bit 1 Bit 0 0 0 0 1 1 0 1 1 ( Remarks Count clock : fsys/32 (Test time range : 8 µ s to 2.048 ms) Count clock : fsys/64 (Test time range : 16 µ s to 4.096 ms) Count clock : fsys/256 (Test time range : 64 µ s to 16.384 ms) Output of the remote controller carrier generator ) : Value at fsys (system clock) = 4 MHz TMRES 0 Read data is always 0. 1 Resets 8-bit timer and IRQTM. TMEN Note 0 Stops 8-bit timer. 1 Starts 8-bit timer. (Falling edge) This bit is always set to 1 when the STOP mode is released. 37 µPD17201A, 17207 7.3 REMOTE CONTROLLER CARRIER GENERATOR The µPD17207 is equipped with a circuit to generate carriers for the remote controller. This circuit consists of a 6-bit counter, a modulo register (NRZHTMM) to determine an NRZ high-level period, a modulo register (NRZLTMM) to determine an NRZ low-level period, and a comparator. A carrier duty factor and a carrier frequency are determined by the contents of these modulo registers. The values of the high- and low-level periods are set in the corresponding modulo registers via the data buffers (DBF). A clock signal input to the 6-bit counter is obtained by dividing the frequency of the system clock signal by two (e.g, 2 MHz with a system clock of 4 MHzfX or 16.384 kHz with a system clock of fXT = 32.768 kHz). Modulo registers NRZHTMM and NRZLTMM are respectively resident on peripheral addresses 04H and 03H. These registers can be written by the PUT instruction and read by the GET instruction 7.3.1 Remote Controller Signal Output Control The output of the REM pin which outputs carriers is controlled by NRZ (bit 0, address 12H of the register file), NRZBF (bit 0, address 11H of the register file), and an 8-bit timer. While NRZ is “1”, the REM pin outputs a carrier signal generated by the remote controller carrier generator. While NRZ is “0”, the output of the REM pin is low. The contents of the NRZBF are automatically set in the NRZ flag by an interrupt signal generated by the 8-bit timer. When data is set in the NRZBF flag in advance, the status of the output of the REM pin varies in synchronization with the counting operation of the 8-bit timer. The content of the NRZ flag is output to the LED pin. Namely, the LED pin outputs a high-level signal when NRZ is “1” and a low-level signal when NRZ is “0”. If the 8-bit timer generates an interrupt signal when the output of the REM pin is high, that is, when NRZ is “1” and a carrier signal is high, the output of the REM pin does not match the contents of NRZ until the carrier signal goes low. This operation is required to hold the pulse width of high carrier pulses constant. (See Fig. 7-3.) When NRZ is “0”, the carrier generation circuit stops. In a system using the output of the remote controller carrier generator as a clock signal for the 8-bit timer, clock pulses are continuously supplied even after NRZ has become “0”. Fig. 7-3 Remote Controller Carrier Output LED(NRZ) REM DelayNote Note The REM pin does not go low before the carrier signal goes low even when NRZ is “0”. This is the value when (TMCK1, TMCK0) ≠ (1,1). The value when (TMCK1, TMCK0) = (1, 1) differs depending on the manipulation of NRZ. If NRZ is set to 1 by an instruction, the width of the first high-level pulse may be narrowed. If NRZ is set by means of transfer from NRZBF, the delay in the above chart is equivalent to the low-level pulse width of the carrier clock. 38 µPD17201A, 17207 Fig. 7-4 Register to Control Output Signals of the Remote Controller RF: Address 12H Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 NRZ Read / write R R R R/W Default at reset 0 0 0 0 R: Read, W: Write NRZ RF: Address 11H Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 NRZBF Read / write R R R R/W Default at reset 0 0 0 0 0 Outputs low-level signal to REM pin and low-level signal to LED pin. 1 Outputs carrier signal to REM pin and high-level signal to LED pin. R: Read, W: Write NRZBF 0 1 NRZ buffer bit. Contents of this bit are transferred to NRZ by interrupt signal generated by 8-bit timer. 39 µPD17201A, 17207 Fig. 7-5 Input/Output Control Register for Port/Timer Output, LED Output, and Serial Interface RF: address 23H Bit 3 Bit 2 Bit 1 Bit 0 0 N R Z E N T M O E S I O E N Read/write R R/W R/W R/W Initial value at reset 0 0 0 0 Read = R, Write = W TMOE Function 0 Uses P0D1 as I/O port pin 1 Uses P0D1 as external signal output pin of 8-bit timer NRZEN Function 7.3.2 0 Uses P0D0 as I/O port pin 1 Uses P0D0 as LED output pin Setting a Carrier Frequency and a Duty Factor Frequency division ratio necessary for obtaining carrier frequency fC can be calculated by the following expression where the frequency of main clock (X) is fX. = fX/(2 x fC). Set the following values to the modulo register to divide High-level period setting value (NRZHTMM) = Low-level period setting value (NRZLTMM) = into duty factors m: n. x m/(m + n) – 1 x n/(m + n) – 1 Example: Where fX = 4 MHz, fC = 38 kHz, and duty factor = 1/3 (m:n = 1:2) . = 4 MHz/(2 x 38 kHz) =. 52.6 Therefore, the values of the modulo registers are as follows: . High-level period (NRZHTMM) =. 17 (11H) . Low-level period (NRZLTMM) =. 34 (22H) Calculating the carrier frequency with these values, . fC = fX/(2 x ) = 4 MHz/(2 x 53) =. 37.74 kHz (where = (17 + 1) + (34 + 1) = 53) 40 µPD17201A, 17207 Table 7-1 Example of Carrier Frequency (fX = fSYS = 4 MHz) Set Value tH (µs) tL (µs) 1/fC (µs) fC (kHz) Duty 00H 0.5 0.5 1.0 1000 1/2 01H 02H 1.0 1.5 2.5 400 2/5 04H 04H 2.5 2.5 5.0 200 1/2 09H 09H 5.0 5.0 10.0 100 1/2 0FH 10H 8.0 8.5 16.5 60.6 1/2 0FH 21H 8.0 17.0 25.0 40.0 1/3 11H 21H 9.0 17.0 26.0 38.5 1/3 11H 22H 9.0 17.5 26.5 37.7 1/3 19H 35H 13.0 27.0 40.0 25.0 1/3 3FH 3FH 32.0 32.0 64.0 15.6 1/2 NRZHTMM NRZLTMM 00H tH tL REM (f C) 1/fC 41 µPD17201A, 17207 7.3.3 Countermeasures against Noise during Transmission (Carrier Output) When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through the infrared LED. Since two batteries are usually used as the power source of the transmitter, several Ω of equivalent resistance (r) exists in the power source as shown in Fig. 7-6. This resistance increases from 10 to 20 Ω if the supply voltage drops to 2 V. While the carrier is output from the REM pin (while the infrared LED lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. To minimize the influence on the microcontroller of this high-frequency noise, take the following measures: 1 Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals of the batteries at the center. Use thick power lines and keep the wiring short. 2 Locate the oscillator as close as possible to the microcontroller and shield it with GND lines (as indicated by the portion inside the dotted line in the figure below). 3 Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. Also, use a capacitor to eliminate high-frequency noise. 4 To prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the CALL/RET instruction, while the carrier is output. 5 To improve the reliability in case of program hang-up, use the watchdog timer (connect the WDOUT and RESET pins). Fig. 7-6 Example of Countermeasures against Noise 0.5 to 1 A Infrared LED REM VDD Microcontroller r + _ Batteries RESET WDOUT VSS Remarks 1. The INT and RESET pins are multiplexed with test pins (refer to 3.4 NOTES ON USING RESET AND INT PINS). 2. 42 In this figure, the RESET pin is connected to a pull-up resistor by mask option. µPD17201A, 17207 8. WATCH TIMER/WATCHDOG TIMER The watch timer is used to generate a watch interrupt signal and a signal to reset the watchdog timer. 8.1 CONFIGURATION OF WATCH TIMER/WATCHDOG TIMER Figure 8-1 shows the functional block diagram of the watch timer/watchdog timer. As shown in Fig. 8-1, the watch timer consists of two selectors, A and B, and a frequency divider. Selector A selects 7 the divided output (fX/2 ) of the 32.768-kHz subclock oscillator (XT) output or of the main clock oscillator (X) output as the source clock by using mask option. Selector B selects a frequency to be used as an interrupt signal. The divider creates a frequency of the source clock. Resetting the watch timer and the operation of selector B is controlled by WTMRES (address 03H, bit 1) and WTMMD (address 03H, bit 2) of the register file. The watchdog timer is reset by WDTRES (address 03H, bit 3) of the register file. If the subclock (fXT) is the source clock, the watch timer count cannot be stopped. Therefore, the subclock does not stop but continues to oscillate even when the CPU is in the STOP mode. If the divided output of the main clock (fX/27) is the source clock (when the subclock is not used), the watch timer stops when the CPU is set in the STOP mode. Fig. 8-1 Configuration of Watch Timer/Watchdog Timer LCD controller / driver fW/213 (4 Hz) Main clock fx fw (32.768 kHz) 1/211 division 1/27 division Sub clock fXT (32.768 kHz) 1/2 division 1/2 division f w /211 (16 Hz) 1/2 division Selector B Selector ANote Frequency divider IRQWTM RF : Bit 2 Address 3FH fw/214 (2 Hz) WDOUT fw/213 (4 Hz) W T M R E S W D T R E S W T M M D Remark ( ) indicates the value when the subclock is used. Note The source clock of the watch timer/watchdog timer is fixed as follows by mask option: 1 When subclock is selected by mask option The source clock is fixed to the subclock. 2 When subclock is not selected by mask option The source clock is fixed to fX/2 7 43 µPD17201A, 17207 8.2 FUNCTION OF WATCH TIMER/WATCHDOG TIMER Fig. 8-2 Watch Timer/Watchdog Timer Control Register RF: Address 03H Bit 3 Bit 2 Bit 1 Bit 0 WDTRES WTMMD WTMRES 0 Read/write W R/W W R Default at reset 0 0 0 0 R: Read, W: Write WTMRES Function 0 Read data is always “0”. 1 Resets watch timer when “1” is written. WTMMD 0 Turns on (“1”) IRQWTM for each fw/213 (4 Hz). 1 Turns on (“1”) IRQWTM for each fw/211 (16 Hz). ( ) indicates the value when the subclock is used. Remark WDTRES 44 0 Read data is always “0”. 1 Resets watchdog timer when “1” is written. µPD17201A, 17207 8.3 WATCHDOG TIMER OPERATION TIMING Unless the watchdog timer is reset in a fixed time, the WDOUT pin outputs a low level. By connecting the WDOUT pin to the RESET pin, a program hang-up can be detected by the watchdog timer. To reset the watchdog timer, set WDTRES (WDTRES = 1). To disable hang-up detection by the watchdog timer when the subclock is used, program so that WDTRES is set at intervals of approximately 340 ms or less. Cautions 1. The watchdog timer cannot be reset in the shaded range in Fig. 8-3. Therefore, set the watchdog timer before both the fW/213 and fW/214 signals go high. 2. For further information on the WDOUT pin, also refer to 14. RESET. Fig. 8-3 Watchdog Timer Operation Timing fw/211 (16Hz) fw/212 (8Hz) fw/213 (4Hz) fw/214 (2Hz) INTWTM (at 4Hz) INTWTM (at 16Hz) WDTRES Watchdog timer reset signal WDOUT WDOUT output goes low if WDTRES is not set Setting WDTRES is invalid during this period Remark Figures in the parentheses indicate the value when using the subclock. 45 µPD17201A, 17207 9. A/D CONVERTER The µPD17207 has an 8-bit successive approximation A/D converter. This A/D converter can be used in the following two modes. Mode 9.1 Description A/D conversion mode Converts analog voltage input to one pin into digital signal Compare mode Compares analog voltages input to two pins CONFIGURATION OF A/D CONVERTER The 8-bit A/D converter consists of a selector that selects an input pin, analog switch, control circuit, 8-bit resistor string D/A converter, and comparator. Fig. 9-1 Block Diagram of A/D Converter Register file ADCCH0 ADCCH1 ADCEN VREFEN Control circuit Comparator ADC0 Register file + ADC1 ADCCMP Selector – ADC2 Analog switch ADC3 8-bit D/A converter VADC Power supply to A/D converter block ADCR Peripheral hardware 46 µPD17201A, 17207 9.2 FUNCTION OF A/D CONVERTER 9.2.1 Function in A/D Conversion Mode In the A/D conversion mode, the A/D converter compares an analog voltage input to one of the pins ADC3 through AD0 with an internal reference voltage and outputs the result to ADCCMP on the register file. The pin from which an analog voltage is to be input is selected by the operation mode register (refer to Figure 9-2). Two or more pins cannot be selected for A/D conversion at the same time. The internal reference voltage is created by the 8-bit D/A converter based on the data set by the internal reference voltage setting register (ADCR). The 8-bit D/A converter can create 256 values of the internal reference voltage. By selecting an internal reference voltage and executing successive approximation in software, the input analog voltage can be converted into a digital value. Operation Mode Register VREFEN ADCEN 1 1 9.2.2 Selected Input Pin ADCCH1 ADCCH0 Function 0 0 ADC0 Compares analog voltage input to ADC0 pin with internal reference voltage 0 1 ADC1 Compares analog voltage input to ADC1 pin with internal reference voltage 1 0 ADC2 Compares analog voltage input to ADC2 pin with internal reference voltage 1 1 ADC3 Compares analog voltage input to ADC3 pin with internal reference voltage Function in Compare Mode In the compare mode, analog voltages input two of the pins ADC3 through ADC0 are compared with each other and the result is output to ADCCMP in the register file. The two pins from which analog voltages are to be input are selected by the operation mode register (refer to Figure 9-2). Two pairs of pins can be selected: pins ADC2 and ADC0, pins or ADC3 and ADC1. Both pairs of pins cannot be selected at the same time. Operation Mode Register VREFEN ADCEN 0 0 Selected ADCCH1 ADCCH0 Input Pin Function 1 0 ADC2 ADC0 Compares analog voltages input to ADC2 and ADC0 pins 1 1 ADC3 ADC1 Compares analog voltages input to ADC3 and ADC1 pins 47 µPD17201A, 17207 9.3 CONTROL REGISTERS OF A/D CONVERTER 9.3.1 Operation Mode Register The operation mode register selects the operation mode and analog input pin(s) of the A/D converter by using the flags in the register file as illustrated below. Fig. 9-2 Operation Mode Register RF: address 21H Bit 3 Bit 2 Bit 1 Bit 0 V R E F E N A D C E N A D C C H 1 A D C C H 0 Read/write Read = R, write = W R/W Initial value at reset VREFEN 0 0 ADCEN 0 ADCCH1 0 ADCCH0 Operation mode Selected analog input pin +side of internal comparator —side of internal comparator 0 0 1 0 Compare ADC2 pin ADC0 pin 0 0 1 1 Compare ADC3 pin ADC1 pin 1 1 0 0 A/D conversion ADC0 pin (Internal reference voltage) 1 1 0 1 A/D conversion ADC1 pin (Internal reference voltage) 1 1 1 0 A/D conversion ADC2 pin (Internal reference voltage) 1 1 1 1 A/D conversion ADC3 pin (Internal reference voltage) 0 0 0 Others Don Care Operation stops None Setting prohibited Undefined Caution Set the operation stop mode to reduce the current consumption when the A/D converter is not used. 48 µPD17201A, 17207 9.3.2 Internal Reference Voltage Setting Register (ADCR) The internal reference voltage setting register (ADCR) is an 8-bit register that sets the reference voltage of the converter. This register is allocated to the peripheral hardware. Data is written to the ADCR via data buffer (DBF). The 8-bit data set to DBF0 and DBF1 is written to the ADCR by using the “PUT ADCR, DBF” instruction. 9.3.3 Compare Result Register The result of comparison by the converter is stored to the ADCCMP flag in the register file. Fig. 9-3 Compare Result Register RF: address 20H Bit 3 0 Bit 2 0 Read/write Initial value at reset Bit 1 Bit 0 0 A D C C M P R 0 0 Read = R 0 0 ADCCMP [In compare mode] ADCCMP Result of comparison ADC2 voltage < ADC0 voltage 0 1 ADC3 voltage < ADC1 voltage ADC2 voltage ≥ ADC0 voltage ADC3 voltage ≥ ADC1 voltage [In A/D conversion mode] ADCCMP Result of comparison 0 ADCn voltage < internal reference voltage 1 ADCn voltage ≥ internal reference voltage (n = 0 to 3) 49 µPD17201A, 17207 9.4 OPERATION IN A/D CONVERSION MODE The timing necessary for A/D conversion differs depending on whether the main clock or subclock is selected as the system clock. (1) When main clock is selected as system clock The following wait times must be set in software in the A/D conversion mode. Wait time <1>: Time of transition from operation stop mode to A/D conversion mode (8 instruction cycles) Wait time <2>: Wait time until value can be set to ADCR (3 instruction cycles) Wait time <3>: Wait time until compare result register can be read (4 instruction cycles) Sets A/D conversion mode (VREFEN, ADCEN, ADCCH1, ADCCH0) Wait time < 1 > + wait time < 2 > (11 instruction cycles) Sets ADCR (80H) (Set + compare) Wait time < 3 > (4 instruction cycles) Reads ADCCMP Wait time < 2 > (3 instruction cycles) Sets ADCR (40H or 0C0H) (Set + compare) Wait time < 3 > (4 instruction cycles) Reads ADCCMP Wait time < 2 > (3 instruction cycles) An example of a program for A/D conversion when the main clock is selected is shown below. 50 µPD17201A, 17207 CMPVAL DAT 80H ; Reference voltage =VADC × CMPVAL/256 ADCNV: BANK0 INITFLG VREFEN,ADCEN,NOT ADCCH1,NOT ADCCH0 ; Starts sampling of input to ADC0 MOV DBF0, #CMPVAL AND 0FH MOV DBF1, #CMPVAL SHR 4 and 0FH REPT 9 Waits for at least 11 instruction cycles until ADCR is set NOP ENDR PUT ADCR,DBF ; Holds input and starts comparison NOP NOP Waits for at least 4 instruction cycles until NOP ADCCMP is checked NOP PEEK WR,.MF.ADCCMP SHR 4 AND 0FFFH MOV DBF0, #CMPVAL AND 0FH MOV DBF1, #CMPVAL SHR 4 AND 0FH ; Reads result of comparison (starts sampling) NOP PUT ADCR, DBF Waits for at least 3 instruction cycles until ADCR is set ; Holds input and starts comparison NOP NOP Waits for at least 4 instruction cycles until NOP ADCCMP is checked NOP PEEK WR,.MF.ADCCMP SHR 4 AND 0FFFH ; Reads result of comparison (starts sampling) (2) When subclock is being selected as system clock Unlike when the main clock is selected, the wait times do not need to be set in software when the subclock is selected. Setting the A/D conversion mode, ADCR, and reading ADCCMP are completed in one instruction cycle, respectively. An example of a program for A/D conversion when the subclock is selected is shown below. CMPVAL DAT 80H ; Reference voltage = VADC × CMPVAL/256 ADCNV: BANK0 INITFLG VREFEN,ADCEN,NOT ADCCH1,NOT ADCCH0 ; Starts sampling a voltage input to the ADC0 pin. MOV DBF0,#CMPVAL AND 0FH MOV DBF1,#CMPVAL SHR 4 AND 0FH PUT ADCR,DBF ; Holds the Input and starts comparison PEEK WR,.MF.ADCCMP SHR 4 AND 0FFFH ; Reads the result of comparison (and starts sampling). 51 µPD17201A, 17207 9.5 OPERATION IN COMPARE MODE In the compare mode, the result of comparison stored to ADCCMP is read and then the next comparison is immediately performed. Therefore, comparison is executed successively and the ADCCMP flag is rewritten accordingly. The timing necessary for compare mode differs depending on whether the main clock or subclock is selected as the system clock. (1) When main clock is selected as system clock The following wait times must be set in software in the compare mode. Wait time <1>: Time of transition from operation stop mode to compare mode (10 instruction cycles) Wait time <2>: Wait time until compare result register can be read (first time only) (3 instruction cycles) Wait time <3>: Wait time until compare result register can be read (second time and onward) (7 instruction cycles) Sets compare mode or changes pin (VREFEN, ADCEN, ADCCH1, ADCCH0) (Set + compare) Wait time < 1 > + wait time < 2 > (13 instruction cycles) Reads ADCCMP (Compare) Wait time < 3 > (7 instruction cycles) Reads ADCCMP (Compare) Wait time < 3 > (7 instruction cycles) Reads ADCCMP (Compare) Wait time < 3 > (7 instruction cycles) An example of a program in the compare mode when the main clock is selected is shown below. COMPARE: INITFLG NOT VREFEN,NOT ADCEN,ADCCH1,ADCCH0 ; Starts comparing voltages of ADC3 REPT 13 and ADC1 NOP or more until comparison ends ENDR PEEK WR,.MF.ADCCMP SHR 4 AND 0FFFH REPT 7 NOP 52 ; Reads result of comparison Waits for duration of 7 instruction cycles or more until comparison ends ENDR PEEK Waits for duration of 13 instruction cycles WR,.MF.ADCCMP SHR 4 AND 0FFFH ; Reads result of comparison µPD17201A, 17207 (2) When subclock is selected as system clock The following wait times must be set in software during compare operation. Wait time: Time of transition from operation stop mode to compare mode (2 instruction cycles) Sets compare mode (VREFEN, ADCEN, ADCCH1, ADCCH0) (Set + compare) Wait time (2 instruction cycles) Reads ADCCMP (Compare) Wait time: Not necessary Reads ADCCMP (Compare) Wait time: Not necessary An example of a program in the compare mode when the subclock is selected is shown below. COMPARE: INITFLG NOT VREFEN,NOT ADCEN,ADCCH1,ADCCH0 ; Starts comparing voltages on ADC3 and ADC1 NOP Waits for duration of 2 instruction cycles NOP or more until comparison ends PEEK WR,.MF.ADCCMP SHR 4 AND 0FFFH ; Reads result of comparison PEEK WR,.MF.ADCCMP SHR 4 AND 0FFFH ; Reads result of comparison 53 µPD17201A, 17207 10. SERIAL INTERFACE Serial interface consists of an 8-bit shift register, a 4-bit shift mode register, and a 3-bit counter, and transmits data in series to and from the bus. 10.1 SERIAL INTERFACE FUNCTION 10.1.1 8-bit Data Transfer in Synchronization with Clocks (Simultaneous transmission and reception) Input and output of serial data on serial interface is controlled by the serial clock (SCK) signal. At the falling edge of the SCK signal, the most significant bit of the shift register is output from the SO pin (pin 59; also used as P1A1). At the rising edge of the SCK signal, the contents of the shift register are shifted left by one bit and, at the same time, data input via the SI pin (pin 60; also used as P1A2) is set in the least significant bit of the shift register. The 3-bit counter counts serial clock pulses. Each time the counter counts eight clock pulses (each time serial data of 8 bits is transferred), the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”) to make an interrupt request. 10.1.2 8-bit Data Reception in Synchronism with Clocks (High-impedance SO output) This operation is basically the same as the above operation except that the SI pin (pin 59; also used as P1A1) goes into a high-impedance state and does not output serial data. Therefore, the SO pin can be used as a port (P1A1). 10.2 SERIAL INTERFACE OPERATION 10.2.1 Serial Interface Operation Modes P1A2/SI (pin 60), P1A1/SO (pin 59), and P1A0/SCK (pin 58) are placed in Serial Interface mode when the SIOEN flag (bit 0, address 23H) of the register file is turned on (“1”). These pins can be used as port pins when the SIOEN flag is off (“0”). As this operation mode disables transfer of serial data, the shift register can be used as an 8-bit register. 10.2.2 Serial Operation Mode The serial operation mode is determined by the status of the SIOHIZ flag (bit 2, address 22H) of the register file. When this flag is off (“0”), a clock-synchronous 8-bit transmission/reception mode is set. When this flag is on (“1”), a clock-synchronous 8-bit reception mode is set. Figure 10-1 shows shift timing waveforms. The only difference between these two modes is whether the SO pin (pin 59; also used as P1A1) goes into a high-impedance state. In transmission of serial data, data to be transmitted is set in the shift register SIOSFR (peripheral address 01H) via the data buffer (DBF) by an PUT instruction, and the SIOTS flag (bit3, address 22H) of the register file is turned on (“1”). Thus serial data trasfer starts. When 8 bits of data are transferred, the SIOTS flag is automatically turned off (“0”) and the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”) to generate an interrupt. If generation of an interrupt is disabled, the end of transfer can be indicated by the SIOTS and IRQSIO flags. Reception of serial data is basically the same as the transmission of serial data except that data is output from the SO pin. The µPD17207 supports four kinds of clock signals (three internal clocks and one external clock) to be selected as the serial clock source. These clock signals are selected by SIOCK1 (bit 1, address 22H) and SIOCK0 (bit 0, address 22H) of the register file. If one of the three internal clock signals is selected as the serial clock source, it is supplied to serial interface when the SIOTS flag turns on (“1”). The clock controls input/output of serial data and is output from the SCK pin (pin 58; also used as P1A0). When eight clock pulses are supplied to the serial interface, the SIOTS flag is automatically turned off (“0”) and the supply of clock pulses to the serial interface is stopped. Then, the SCK pin is held high. At this time, the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”). 54 µPD17201A, 17207 If the external clock is selected, the clock pulses supplied from the SCK pin are supplied to serial interface when the SIOTS flag is turned on (“1”). Similarly, when eight clock pulses are supplied to the serial interface, the SIOTS flag is automatically turned off (“0”) and the supply of clock pulses to the serial interface is stopped. At this time, the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”). The IRQSIO flag is automatically reset to “0” when the SIOTS flag is turned on (“1”). To forcibly stop transfer of serial data, turn on the SIOTS flag manually. Note, however, that data transfer cannot be resumed from the point at which the transfer has been forcibly stopped. Fig. 10-1 Shift Timing Waveforms SCK pin 1 SI pin SO pin (SIOHIZ=0) 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 High-impedance SO pin (SIOHIZ=1) IRQSIO Turns on SIOTS (1). Turns off SIOTS (0). (End of transfer) Remark DI : Serial data input DO : Serial data output 55 µPD17201A, 17207 Fig. 10-2 Input/Output Control Register for Selection of Port, Timer Output, LED Output, and Serial Interface Bit 3 Bit 2 Bit 1 Bit 0 0 NRZEN TMOE SIOEN Read/write R R/W R/W R/W Default at reset 0 0 0 0 RF: Address 23H R: Read, W: Write SIOEN Function 56 0 Uses Port 1A as I / O port. 1 Uses Port 1A as serial interface. µPD17201A, 17207 Fig. 10-3 Serial Interface Control Register RF: Address 22H Bit 3 Bit 2 Bit 1 Bit 0 SIOTS SIOHIZ SIOCK1 SIOCK0 R/W Read/write Default at reset 0 0 R: Read, W: Write 0 0 SIOCK1, SIOCK0 SIOCK1, Selects Serial Clock SIOCK0 0 0 External clock 0 1 fsys/16 1 0 fsys/128 1 fsys/1024 1 (fsys: system clock. fX or fXT) SIOHIZ SO Pin Status 0 Serial data output 1 High-impedance status SIOTS [Read] Function 0 Inhibits contents of shift register from being shifted. Pin status can be read by instruction input from port. 1 Shifts contents of shift register by serial clock pulses. Pin status can be read by instrucrtion input from port. [Write] Function 0 Forcibly stops transfer of serial data. Data transfer cannot be resumed from where it has been stopped. 3-bit counter is cleared. 1 Can be set by PUT instruction only. Transfer of serial data starts. Resets IRQSIO flag (to “0”). This bit is automatically reset to “0” after transfer of data ends. Caution Be sure to select a serial clock signal before starting transfer of serial data. Never set them at the same time. Remark At the end of transfer of 8-bit serial data, the IRQSIO flag (bit 3, address 3BH of the register file) is turned on (“1”) and an interrupt request occurs. 57 µPD17201A, 17207 11. 11.1 LCD CONTROLLER/DRIVER CONFIGURATION OF LCD CONTROLLER/DRIVER The µPD17207 is equipped with an LCD controller which generates segment and common signals according to the data set to the LCD register and a segment/common driver which can directly drive the LCD panel. Figure 11-1 shows the functional block diagram of the LCD controller/driver. Fig. 11-1 Block Diagram of LCD Controller/Driver LCD register LCDD0 LCDD1 (40 H) (41 H) 0 1 2 3 0 1 2 3 LCDD33 LCDD34 LCDD35 (61 H) (62 H) (63 H) 0 1 2 3 0 1 2 3 0 1 2 3 Multiplexer 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 L C D E N L C D C K 2 L C D C K 1 L C D C K 0 L C D M D 3 L C D M D 2 L C D M D 1 L C D M D 0 Timing controller Data selector Voltage booster circuit for LCD driver Segment/common driver LCD0 58 LCD1 LCD33 LCD34 /COM3 LCD35 /COM2 COM1 COM0 VLCD0 VLCD1 VLCD2 CAPH CAPL µPD17201A, 17207 11.2 FUNCTIONS OF LCD CONTROLLER/DRIVER The LCD controller/driver of the µPD17207 features the following: (1) Automatically reads the LCD register and generates segment signals and common signals. (2) Three display modes available: • Display mode 1: 1/2-duty, 1/3-bias • Display mode 2: 1/3-duty, 1/3-bias • Display mode 3: 1/4-duty, 1/3-bias (3) Four frame frequencies available in each display mode. (4) Since a voltage booster circuit for LCD driver is used, constant output voltage not affected by the fluctuation in the supply voltage. (5) The LCD register which is not used for display can be used as ordinary data memory. Table 11-1 shows the maximum number of pixels available in each display mode. Table 11-1 Maximum Number of Pixels Displayed 11.3 Mode Duty Common Signal Maximum Number of Pixels 1 1/2 COM0, COM1 72 (36 segment signals by 2 common signals) 2 1/3 COM0, COM1, COM2 105 (35 segment signals by 3 common signals) 3 1/4 COM0, COM1, COM2, COM3 136 (34 segment signals by 4 common signals) DISPLAY MODE REGISTER The Display Mode register selects a display mode of the LCD controller/driver, a frame frequency, and LCD on/ off status. The display mode register consists of LCDMD0 to LCDMD3 (address 32H of register file) for selection of a display mode, LCDEN (bit 3, address 31H of the register file) for selection of the LCD on/off status, and LCDCK0 to LCDCK2 (bit 2 to bit 0, address 31H of the register file) for selection of a frame frequency. 59 µPD17201A, 17207 Fig. 11-2 Display Mode Register RF: 32H Bit 3 Bit 2 Bit 1 Bit 0 LCDMD3 LCDMD2 LCDMD1 LCDMD0 Read/write R R R/W R/W Default at reset 0 0 0 1 Read = R, Write = W LCDMD0 _ LCDMD3 LCDMD3 LCDMD2 LCDMD1 LCDMD0 Display Mode 0 0 0 0 Stops the LCD voltage booster circuit.Note 0 0 0 1 Display mode 1 (1/2 duty) 0 0 1 0 Display mode 2 (1/3 duty) 0 0 1 1 Display mode 3 (1/4 duty) Others Inhibited Note All segment and common signals are at a preset voltage (VLCD0) 60 µPD17201A, 17207 Fig. 11-3 LCD Controller/Driver Control Register RF: 31H Bit 3 Bit 2 Bit 1 Bit 0 LCDEN LCDCK2 LCDCK1 LCDCK0 Read/write Default at reset R/W R R/W R/W 0 0 0 0 Read = R, Write = W LCDCK0 _ LCDCK2 Frame Frequency LCDCK2 LCDCK1 LCDCK0 0 0 0 0 0 0 1 1 0 1 0 1 Mode 1 Mode 2 Mode 3 1/2 duty 1/3 duty 1/4 duty fw/(2 × 26) fw/(3 × 26) fw/(4 × 26) [256 Hz] [170 Hz] [128 Hz] fw/(2 × 25) fw/(3 × 25) fw/(4 × 25) [512Hz] [341.3 Hz] [256 Hz] fw/(2 × 28) fw/(3 × 28) fw/(4 × 28) [64 Hz] [42.6 Hz] [32 Hz] fw/(2 × 27) fw/(3 × 27) fw/(4 × 27) [128 Hz] [85.3 Hz] [64 Hz] Others Inhibited Remark 1. fw = fxt or fx/27 2. [ ] : Frequency for fw = 32.768 kHz LCDEN LCDEN Function 0 Turns off the LCD display. (all segment signals are on unselected) 1 Turns on LCD display. 61 µPD17201A, 17207 Cautions 1. The LCD clock is supplied from the watch timer; therefore, the LCD flickers if the watch timer 2. If the main clock and subclock are used, the source clock of the LCD is the subclock. When is reset during display. Do not reset the watch timer during display. the power is switched on, therefore, the LCD may flicker until the oscillation of the subclock stabilizes. Make sure that a sufficiently long time elapses until the oscillation stabilizes before turning on the LCD (it is recommended that all-light mode be used immediately after power application). 3. The LCD display voltages (VLCD0, VLCD1, and VLCD2) become undefined momentarily on turning ON/OFF power, reset, and setting or clearing the STOP mode. As a result, the LCD display may be turned ON (blurring of the LCD). This symptom is conspicuous when only the main clock is used or if the capacitance at the LCD display side is too high. To prevent this, take the following measures. • Provide wait time of 1 frame cycle or longer until the voltage booster circuit is stopped by the display mode register after the LCD display has been turned off. • Provide wait time of around 2 ms after the voltage booster circuit has been stopped until the STOP instruction is executed. 62 µPD17201A, 17207 11.4 LCD REGISTER The LCD register is resident on addresses 40H to 63H (LCDD0 to LCDD35) of BANK 0. The LCD controller/driver reads the LCD register independently of the operation of the CPU. The LCD controller controls segment signals according to the data of the LCD register. The data memory area which is not used for LCD display can be used as ordinary data memory. Figure 11-4 shows the assignment of segment outputs to bits of the LCD register. Fig. 11-4 Assignment of Common Signals and Segment Signals to LCD Register Address b3 b2 b1 b0 LCDD 0 (40 H) LCD0 LCDD 1 (41 H) LCD1 LCDD 2 (42 H) LCD2 LCDD 33 (61 H) LCD33 LCDD 34 (62 H) LCD34/COM3 LCDD 35 (63 H) LCD34/COM3 COM3 COM2 COM1 COM0 63 64 µPD17201A, 17207 Fig. 11-5 Wiring Example of Secondary Time Sharing LCD Panel LCDD 32 (60 H) LCDD 31 (5 FH) LCDD 30 (5 EH) LCDD 29 (5 DH) LCDD 28 (5 CH) LCDD 27 (5 BH) LCDD 26 (5 AH) LCDD 25 (59 H) LCDD 24 (58 H) LCDD 23 (57 H) LCDD 22 (56 H) LCDD 21 (55 H) LCDD 20 (54 H) LCDD 19 (53 H) LCDD 18 (52 H) LCDD 17 (51 H) LCDD 16 (50 H) LCDD 15 (4 FH) LCDD 14 (4 EH) LCDD 13 (4 DH) LCDD 12 (4 CH) LCDD 11 (4 BH) LCDD 10 (4 AH) LCDD 9 (49 H) LCDD 8 (48 H) LCDD 7 (47 H) LCDD 6 (46 H) LCDD 5 (45 H) LCDD 4 (44 H) LCDD 3 (43 H) LCDD 2 (42 H) LCDD 1 (41 H) LCDD 0 (40 H) 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 BIT0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 BIT1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x BIT2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x BIT3 LCDD35 LCDD34 LCDD33 LCDD32 LCD31 LCD30 LCD28 LCD29 LCD27 LCD26 LCD24 LCD25 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD16 LCD17 LCD14 LCD15 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD3 LCD4 LCD1 LCD2 x: Any value because of secondary time sharing display. COM1 LCDD 33 (61 H) 0 0 COM0 LCDD 34 (62 H) 0 LCD0 LCDD 35 (63 H) LCD PANEL TIMING STROBE LCDD 30 (5 EH) LCDD 29 (5 DH) LCDD 28 (5 CH) LCDD 27 (5 BH) LCDD 26 (5 AH) LCDD 25 (59 H) LCDD 24 (58 H) LCDD 23 (57 H) LCDD 22 (56 H) LCDD 21 (55 H) LCDD 20 (54 H) LCDD 19 (53 H) LCDD 18 (52 H) LCDD 17 (51 H) LCDD 16 (50 H) LCDD 15 (4 FH) LCDD 14 (4 EH) LCDD 13 (4 DH) LCDD 12 (4 CH) LCDD 11 (4 BH) LCDD 10 (4 AH) LCDD 9 (49 H) LCDD 8 (48 H) LCDD 7 (47 H) LCDD 6 (46 H) LCDD 5 (45 H) LCDD 4 (44 H) LCDD 3 (43 H) LCDD 2 (42 H) LCDD 1 (41 H) LCDD 0 (40 H) 1 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 BIT0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 0 1 BIT1 0 0 x’ 1 0 x’ 0 0 x’ 1 0 x’ 1 0 x’ 0 0 x’ 1 0 x’ 1 1 x’ 0 0 x’ 1 0 x’ 0 0 x’ 1 0 BIT2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x BIT3 LCD1 LCD0 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19 LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 LCD31 LCD32 LCD33 65 µPD17201A, 17207 Fig. 11-6 Wiring Example of Tertiary Time Sharing LCD Panel COM2 LCDD 31 (5 FH) 0 1 LCD34 x : Any data because of tertiary time-sharing disply. COM1 LCDD 32 (60 H) 1 0 COM0 LCDD 33 (61 H) 0 LCD2 LCDD 34 (62 H) x’ : Any data because it is not connected to any segment on the LCD panel. LCD PANEL TIMING STROBE 66 µPD17201A, 17207 Fig. 11-7 Wiring Example of Quarternary Time Sharing LCD Panel COM3 COM2 COM1 LCDD 31 (5 FH) LCDD 30 (5 EH) LCDD 29 (5 DH) LCDD 28 (5 CH) LCDD 27 (5 BH) LCDD 26 (5 AH) LCDD 25 (59 H) LCDD 24 (58 H) LCDD 23 (57 H) LCDD 22 (56 H) LCDD 21 (55 H) LCDD 20 (54 H) LCDD 19 (53 H) LCDD 18 (52 H) LCDD 17 (51 H) LCDD 16 (50 H) LCDD 15 (4 FH) LCDD 14 (4 EH) LCDD 13 (4 DH) LCDD 12 (4 CH) LCDD 11 (4 BH) LCDD 10 (4 AH) LCDD 9 (49 H) LCDD 8 (48 H) LCDD 7 (47 H) LCDD 6 (46 H) LCDD 5 (45 H) LCDD 4 (44 H) LCDD 3 (43 H) LCDD 2 (42 H) LCDD 1 (41 H) LCDD 0 (40 H) 0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 BIT0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 BIT1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 BIT2 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 BIT3 LCD33 LCD32 LCD31 LCD30 LCD29 LCD28 LCD27 LCD26 LCD25 LCD24 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD16 LCD17 LCD15 LCD14 LCD13 LCD12 LCD11 COM0 LCDD 32 (60 H) 0 LCD10 LCD8 LCD9 LCD6 LCD7 LCD5 LCD4 LCD2 LCD3 LCD1 LCD0 LCDD 33 (61 H) LCD PANEL TIMING STROBE µPD17201A, 17207 11.5 SEGMENT SIGNALS AND COMMON SIGNALS Segment pins LCD0 to LCD35 are connected to the corresponding front electrodes of the LCD panel and common pins COM0 to COM3 are connected to corresponding rear electrodes of the LCD panel. The LCD panel lights when the potential difference between its segment and common signals goes beyond a preset voltage. The LCD panel is driven on an AC voltage because it degrades quickly if a DC voltage is continuously applied between its segment and common pins. Figure 11-8 to Fig. 11-10 shows waveforms of segment and common signals in each display mode. Fig. 11-8 Common and Segment Waveforms in Each Display Mode (for LCDEN = 1) Display mode [Mode 1] [Mode 2] [Mode 3] VLCD2 VLCD1 VLCD0 GND COM 0 pin COM1 pin VLCD2 VLCD1 VLCD0 GND COM2 pin VLCD2 VLCD1 VLCD0 GND Segment pin (LCD25) Segment pin (LCD24) COM3 pin VLCD2 VLCD1 VLCD0 GND Segment pin (LCD24) VLCD2 VLCD1 VLCD0 GND LCDn pin + VLCD2 + VLCD1 + VLCD0 GND _ VLCD2 _ VLCD1 _ VLCD0 COM0-LCDn 1 1 1 1 1 1 : The LCD stripe lights here (by an LCD selection voltage). 67 µPD17201A, 17207 Fig. 11-9 Common and Segment Waveforms for LCDEN = 0 (LCD Display Off) VLCD2 COM0 pin VLCD1 VLCD0 GND VLCD2 COM1 pin VLCD1 VLCD0 GND VLCD2 COM2 pin VLCD1 VLCD0 GND VLCD2 COM3 pin VLCD1 VLCD0 GND VLCD2 LCDn pin VLCD1 VLCD0 GND + VLCD2 + VLCD1 + VLCD0 COM0-LCDn GND _ VLCD0 _ VLCD1 _ VLCD2 68 µPD17201A, 17207 Fig. 11-10 Common and Segment Waveforms for LCDMD0 = 0 and LCDMD1 = 0 (Voltage Booster Circuit Stop) VLCD2 VLCD1 COM0 pin VLCD0 GND VLCD2 COM1 pin VLCD1 VLCD0 GND VLCD2 COM2 pin VLCD1 VLCD0 GND VLCD2 COM3 pin VLCD1 VLCD0 GND VLCD2 LCDn pin VLCD1 VLCD0 GND + VLCD2 + VLCD1 + VLCD0 COM0-LCDn GND _ VLCD0 _ VLCD1 _ VLCD2 69 µPD17201A, 17207 11.6 VOLTAGE BOOSTER CIRCUIT FOR LCD DRIVER The µPD17207 has a voltage booster circuit for LCD driver which prevents the LCD from flickering when the supply voltage fluctuates. Output signals VLCD2, VLCD1, and VLCD0 of the segment and common signals are respectively two times (VLCD1), three times (VLCD2), and equal to the output (reference voltage, VLCD0) of the reference voltage generator. The reference voltage VLCD0 can be adjusted by a resistor connected to the Reference Voltage Adjuster for LCD driver pin VLCDC. Figure 11-11 shows an example of a circuit of adjusting the reference voltage for the LCD driver. Figure 11-12 shows its operating principle. Fig. 11-11 Reference Voltage Adjusting Circuit for LCD Driver (Example) VLCD2 VLCD1 VLCD0 R1 µ PD17207 VLCDC C2 C3 C4 R2 CAPH C1 CAPL R1 + R2 = 2MΩ C1 = C2 = C3 = C4 = 0.47 µ F Reference voltage VLCD0 can be adjusted by resistors R1 and R2. Where VLCDC = 0.6 V, R1 + R2 × 0.6 (V) R2 VLCD1 = 2 × VLCD0 (V) VLCD2 = 3 × VLCD0 (V) VLCD0 = Caution When the power is switched on, the LCD may light until the supply voltage stabilizes because the voltages of the capacitors for the voltage regulator and driver are undefined. It is therefore recommended that the all-light mode be used immediately after the power is switched on. 70 µPD17201A, 17207 Fig. 11-12 Operating Principle of LCD Driver Voltage Booster Circuit (1) Charge C1 with VLCD0 (VLCD0). VLCD2 CAPH VLCD0 C1 CAPL VLCD1 VDD VLCDC _ VLCD0 + R1 Regulator C2 C3 C4 C3 C4 R2 (2) Charge C3 with VLCD0 and voltage of C1 (VLCD0 + VLCD0 = 2 × VLCD0). VLCD2 CAPH VLCD0 C1 CAPL VLCD1 2 × VLCD0 VDD VLCDC _ VLCD0 + R1 Regulator C2 R2 (3) Charge C4 with voltage of C3 and voltage of C1 (2 × VLCD0 + VLCD0 = 3 × VLCD0). VLCD2 CAPH VLCD0 C1 CAPL VLCD1 VDD VLCDC 2 × VLCD0 _ 3 × VLCD0 VLCD0 + R1 Regulator C2 C3 C4 R2 (1) through (3) are repeated to boost the voltage. ( ) indicates the logical value eventually reached. The voltage is not necessarily boosted to the level in ( ) at a time. 71 µPD17201A, 17207 12. INTERRUPT FUNCTIONS When a peripheral hardware unit (INT pin, 8-bit timer, clock timer, or serial interface) makes an interrupt request, the interrupt function temporarily stops the execution of the current program and transfers program control to a predetermined address (termed a vector address). 12.1 INTERRUPT SOURCES The µPD17207 supports the four interrupt sources (see Table 12-1). When accepting an interrupt, the µPD17207 automatically transfers program control to a predetermined address (called a vector address). Table 12-1 Vector Addresses Priority Interrupt Source Vector Address 1 8-bit timer (Internal) 0004H 2 Rising edge of INT pin input (External) 0003H 3 Clock timer (Internal) 0002H 4 Serial interface (Internal) 0001H If two or more interrupt requests are issued at the same time, the interrupt requests are accepted according to the priorities assigned to them. Accepting an interrupt is enabled or disabled by the EI or DI instruction. Basically, the interrupt is accepted when it is enabled by the EI instruction. While the DI instruction is executed or while an interrupt is accepted, the other interrupts are disabled. To enable accepting another interrupt after one interrupt has been completed, the EI instruction must be executed before the RETI instruction. The interrupt is accepted by the EI instruction after the instruction next to EI has been executed; therefore, no interrupt is accepted between the EI and RETI instructions. 12.2 HARDWARE OF INTERRUPT CONTROL CIRCUIT This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is executed. An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. 72 µPD17201A, 17207 (2) EI/DI instruction Whether an accepted interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts. Table 12-2 Interrupt Request Flags and Interrupt Enable Flags Interrupt Request Flag Interrupt Enable Flag Signal Setting Interrupt Request Flag IRQ Set when rising edge of INT pin input signal is detected IP IRQTM Set by coincidence signal of 8-bit timer IPTM IRQWTM Set by interrupt request signal from watch timer. Interrupt request signal generation interval is selected by WTMMD flag (RF: 03H, bit 2) IPWTM IRQSIO Set by signal indicating end of serial data transfer operation from serial interface IPSIO 12.2.1 INT Flag This flag reads the status of the INT pin. This flag is “1” when a high-level signal is on the INT pin or “0” when a low-level signal is there. Fig. 12-1 INT flag RF: Address 0FH Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 I N T 0 _ Read/write Default at reset R: Read R 0 0 _: Undefined INT Function 0 INT pin is low 1 INT pin is high 73 µPD17201A, 17207 12.2.2 Interrupt Enable Flags These flags enable the corresponding interrupts to be accepted. 1: The interrupt is accepted. 2: The interrupt is not accepted. Fig. 12-2 Interrupt Enable Flags RF: Address 2FH Bit 3 Bit 2 Bit 1 Bit 0 I P S I O I P W T M I P I P T M Read/write Default at reset R/W 0 0 R: Read, W: Write 0 0 IPTM Function 0 Disables interrupt by 8-bit timer 1 Enables interrupt by 8-bit timer IP Function 0 Disables interrupt by rising edge of INT pin input 1 Enables interrupt by rising edge of INT pin input IPWTM Function 0 Disables interrupt by watch timer 1 Enables interrupt by watch timer IPSIO Function 74 0 Disables interrupt by serial interface 1 Enables interrupt by serial interface µPD17201A, 17207 12.2.3 Interrupt Request Flags These flags indicates the occurrence or acceptance of the corresponding interrupt requests. 1: The interrupt request has been made. 0: The interrupt request has been accepted. It is possible to set the status of each Interrupt Request flag by programming. When you write “1” in an Interrupt Request flag, the corresponding interrupt can be generated by software. When you write “0” in an Interrupt Request flag, the corresponding interrupt being held is released. Fig. 12-3 Interrupt Request Flags (1/4) RF: Address 3BH Bit 3 Bit 2 Bit 1 Bit 0 I R Q S I O 0 0 0 Read/write R/W R R R Default at reset 0 0 0 0 R: Read, W: Write IRQSIO Function 0 Serial interface interrupt request has not been made. 1 Serial interface interrupt request has been made. Fig. 12-3 Interrupt Request Flags (2/4) RF: Address 3CH Bit 3 Bit 2 Bit 1 Bit 0 0 I R Q W T M 0 0 Read/write R R/W R R Default at reset 0 0 0 0 R: Read, W: Write IRQWTM Function 0 Watch timer interrupt request has not been made. 1 Watch timer interrupt request has been made. 75 µPD17201A, 17207 Fig. 12-3 Interrupt Request Flags (3/4) RF: Address 3DH Bit 3 Bit 2 Bit 1 Bit 0 0 0 I R Q 0 Read/write R R R/W R Default at reset 0 0 0 0 R: Read, W: Write IRQ Function 0 Interrupt request has not been made at rising edge of INT pin input. 1 Interrupt request has been made at rising edge of INT pin input. Fig. 12-3 Interrupt Request Flags (4/4) RF: Address 3EH Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 I R Q T M Read/write R R R R/W Default at reset 0 0 0 1Note R: Read, W: Write IRQTM Function Note 76 1H even after the STOP mode has been released. 0 8-bit timer interrupt request has not been made. 1 8-bit timer interrupt request has been made. µPD17201A, 17207 12.3 INTERRUPT SEQUENCE If the IRQxx flag is set to “1” while the IPxx is “1”, processing of an interrupt starts at the end of the instruction cycle of the instruction being executed when the IRQxx flag was set. Processing of an instruction made in the execution of an MOVT instruction starts at the end of the second instruction cycle as the MOVT instruction runs in the second instruction cycle. When the IPxx flag is “0”, interrupt processing does not start until the IPxx flag is set even when the IRQxx flag is set. When two or more interrupts are enabled, they are processed in the ascending order of priorities. (An interrupt must wait until processing of an interrupt of the higher priority ends.) 12.3.1 Operations When Interrupt Is Accepted When an interrupt has been accepted, the CPU performs processing in the following sequence: (1) Decrements the value of the stack pointer (SP) by 1. (2) Saves the current value of the program counter to the address stack register (ASR) specified by the SP. If the branch (BR) or subroutine call (CALL) instruction is executed when the interrupt has been accepted, the address of the program memory (ROM) to which execution is to branch, or called is loaded to the PC. (3) Saves the value of each flag (BCD, CMP, CY, Z, IXE) of the bank register (BANK) and program status word (PSWORD) to the interrupt stack register (INTSK, three levels). (4) Transfers the vector address to the PC. One instruction cycle is required to perform the above processing. 12.3.2 Returning from Interrupt Processing Routine To return from an interrupt processing routine, use the RETI instruction. Then the following processing is executed within an instruction cycle. (1) Restores the value of the interrupt stack register (INTSK) to each flag (BCD, CMP, CY, Z, IXE) of the program status word (PSWORD). (2) Restores the value of the address stack register (ASR) specified by the stack pointer (SP) to the program counter. (3) Increments the value of the stack pointer by 1. To accept another interrupt after an interrupt has been processed, it is necessary to execute an EI instruction before the RETI instruction. An interrupt will never be accepted between the EI and RETI instructions as an interrupt is accepted by the EI instruction only after the next instruction has been executed. 77 µPD17201A, 17207 13. STANDBY FUNCTIONS The µPD17207 has two modes of standby functions: HALT mode and STOP mode. The standby functions reduce the power dissipation of the µPD17207. In HALT mode, the µPD17207 stops the execution of the program with the main clock on. (The CPU stops to run.) This mode is kept until a HALT releasing condition is satisfied. In STOP mode, the µPD17207 stops the execution of the program with the main clock off. The µPD17207 dissipates less circuit current in STOP mode than in HALT mode. HALT mode is set by the execution of a HALT instruction and STOP mode is set by the execution of a STOP instruction. 13.1 HALT MODE In HALT mode, the µPD17207 stops the execution of the program with the main clock on for reduction of its power dissipation. Execute a HALT instruction to set HALT mode. The condition of releasing HALT mode is determined by the operand of the HALT instruction. See Table 13-1. After HALT mode is released, the µPD17207 performs operations as shown in Table 13-2. Caution Do not execute an instruction to clear the interrupt request flag (IRQxxx) whose interrupt enable flag (IPxxx) is set immediately before the HALT 8H or HALT 0AH instruction is executed. If the flag is cleared, the HALT mode may not be set. Table 13-1 HALT Mode Releasing Conditions Operand Value 78 HALT Mode Releasing Condition 0010B (02H) 1) When an 8-bit timer interrupt request (IRQTM) is made 1000B (08H) 1) When an interrupt request (IRQTM, IRQWTM, IRQSIO, or IRQ) is made for an interrupt whose enable flag (IPTM, IPWTM, IPSIO, or IP) is on (“1”) 2) When any of pins P0A0 to P0A3 goes low 1010B (0AH) 1) 2) When an 8-bit timer interrupt request (IRQTM) is made When an interrupt request (IRQWTM, IRQSIO, or IRQ) is made for an interrupt whose enable flag (IPWTM, IPSIO, or IP) is on (“1”) Others Inhibited µPD17201A, 17207 Table 13-2 Operations after HALT Mode Has Been Released (a) HALT 02H Standby Mode Released by: Satisfaction of Release Interrupt Enable Status Interrupt Enable Flag Operation after Release of Standby Mode DI Disable Execution starts from instruction following Enable HALT Condition by Interrupt Request (IRQTM) EI Disable Enable Branches to vector address of interrupt (b) HALT 08H Standby Mode Released by: Interrupt Enable Status Low Level Input to Port 0A Don’t care Don’t care DI Disable Standby mode is not released Enable Execution starts from instruction following Satisfaction of Release Condition by Interrupt Interrupt Enable Flag Request (IRQTM, IRQWTM, IRQSIO, or IRQ) Operation after Release of Standby Mode Execution starts from instruction following HALT HALT EI Disable Standby mode is not released Enable Branches to vector address of interrupt (c) HALT 0AH Standby Mode Released by: Satisfaction of Release Interrupt Enable Status Interrupt Enable Flag Operation after Release of Standby Mode DI Disable Execution starts from instruction following Enable HALT Condition by Interrupt Request (IRQTM) Satisfaction of Release EI DI Condition by Interrupt Disable Enable Branches to vector address of interrupt Disable Standby mode is not released Enable Execution starts from instruction Request (IRQWTM, IRQSIO, or IRQ) following HALT EI Disable Standby mode is not released Enable Branches to vector address of interrupt 79 µPD17201A, 17207 13.2 CONDITIONS OF EXECUTING AN HALT INSTRUCTION The HALT instruction can be executed only under a specific condition for prevention of malfunction. See Table 13-3. The HALT instruction which does not satisfy the conditions listed in Table 13-3 is treated as an NOP instruction. Table 13-3 Conditions of Executing the HALT Instruction Operand Value 0010B (02H) 1000B (08H) 80 Execution Condition 1) The 8-bit timer interrupt request (IRQTM) should be reset. 1) The interrupt request flag (IRQTM, IRQWTM, IRQSIO, or IRQ) should be reset for an interrupt whose enable flag (IPTM, IPWTM, IPSIO, or IP) is on (“1”) 2) All of pins P0A0 to P0A3 should be high input or output. 3) All of pins P0B0 to P0B3 should be in output mode and output latch should be “0”. 1010B (0AH) 1) The 8-bit timer interrupt request (IRQTM) should be reset. 2) The interrupt request flag (IRQWTM, IRQSIO, or IRQ) should be reset for an interrupt whose enable flag (IPWTM, IPSIO, or IP) is on (“1”) Others Reserved µPD17201A, 17207 13.3 STOP MODE In STOP mode, the µPD17207 stops the execution of the program with the main clock temporarily off for great reduction of its power dissipation. Execute a STOP instruction to set STOP mode. The STOP instruction is not valid for a system using a subclock only. When the system uses a subclock as the system clock (that is, when SYSCK = 0), the STOP instruction is treated as an NOP instruction. The condition of releasing STOP mode is determined by the operand of the STOP instruction. See Table 13-4. After STOP mode is released, the µPD17207 performs operations as follows: 1 Clearing IRQTM 2 Starting watch timer and watchdog timer (not reset) 3 Resetting and starting 8-bit timer 4 The instruction following STOP 8H or the interrupt vector address is executed when the value of the 8-bit counter coincides with the value of the modulo register (setting of IRQTM). Caution When the subclock is used, the watch timer and watchdog timer do not stop even in the STOP mode. The time interval between release of STOP mode and start of the execution of the next instruction is set by the contents of the modulo register of the 8-bit timer. This time interval is expressed as follows: (TMM +1) x 1024/fx [sec] where, TMM : : fx Example: Content of the modulo register Frequency of the main clock. In a system using the main clock of 4 MHz, the time interval between release of STOP mode and start of the execution of the next instruction is: (TMM + 1) x 256 [microseconds] Caution Do not set an instruction that would clear the interrupt request flag (IRQxxx) whose interrupt enable flag (IPxxx) is set immediately before the STOP 8H instruction, if you set such an instruction, the STOP mode may not be set. Table 13-4 STOP Mode Releasing Conditions Operand Value 1000B (08H) STOP Mode Releasing Condition 1 2 Others When an interrupt request (IRQWTM, IRQSIO, or IRQ) is made for an interrupt whose enable flag (IPWTM, IPSIO, or IP) is on (“1”) When any of pins P0A0 to P0A3 goes low Inhibited 81 µPD17201A, 17207 13.4 CONDITIONS OF EXECUTING AN HALT INSTRUCTION The STOP instruction can be executed only under a specific condition for prevention of malfunction. See Table 13-5. The STOP instruction which does not satisfy the conditions listed in Table 13-5 is treated as an NOP instruction. Table 13-5 Conditions of Executing the STOP Instruction Operand Value Execution Condition 1) 1000B (08H) Others 2) 3) The interrupt request flag should be reset for an interrupt whose enable flag (IPWTM, IPSIO, or IP) is on (“1”) All of pins P0A0 to P0A3 should be high input or output. All of pins P0B0 to P0B3 should be in output mode and output latch should be “0”. Inhibited Fig. 13-1 Releasing Standby Mode (a) Releasing STOP mode by interrupt Wait (time set by TMM) STOP instruction Standby release signal Operation mode Clock Oscillation STOP mode HALT mode Oscillation stops Oscillation Operation mode Remark The dotted line indicates when the interrupt that has released the standby mode is accepted (b) Releasing HALT mode by interrupt HALT instruction Standby release signal Operation mode Clock Operation mode HALT mode Oscillation Remark The dotted line indicates when the interrupt that has released the standby mode is accepted 82 µPD17201A, 17207 14. RESET 14.1 RESET BY RESET SIGNAL INPUT When a low-level signal is input to the RESET pin for 50 µs or more, the system is reset. The system must be reset at least once when the power is turned on, as the operation of the internal circuit is undefined. When reset has been effected, the following circuits are initialized: 1 The program counter is reset to 0. 2 The flags of the register file are initialized (for the initial values, refer to Fig. 15-1 Register File List). 3 Initial value 0320H is written to the data buffer. 4 The peripheral hardware is initialized. 5 Oscillation of the main clock is stopped. When the RESET pin is made high, oscillation of the main clock is started, and about 64 ms after that (where the main clock frequency is 4 MHz), execution of the program is started from address 0. Fig. 14-1 Reset Operation by RESET Input Wait (approx. 64 ms/4 MHz) Starts from address 0 RESET Operation mode or standby mode HALT mode Operation mode Main clock oscillation stopped 14.2 RESET BY WATCHDOG TIMER (RESET AND WDOUT PINS CONNECTED) When the watchdog timer is activated while the program is being executed, a low level is output to the WDOUT pin, and the program counter is reset to 0. Therefore, when the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0. When developing a program, reset the watchdog timer (set the WDTRES flag) at intervals of 340 ms or less (where fx = 4 MHz). 14.3 RESET BY STACK POINTER (RESET AND WDOUT PINS CONNECTED) When the value of the stack pointer reaches 6H or 7H while the program is being executed, a low level is output to the WDOUT pin, and the program counter is reset to 0. When the level of nesting of interrupt or subroutine call exceeds 5 (stack overflow), or when the return instruction is executed despite the stack level being 0 because the call instruction and return (RET) instruction have not been correctly used in pairs (stack underflow), the program can be restarted from address 0. 83 µPD17201A, 17207 Table 14-1 Hardware Status after Reset Hardware Program Counter (PC) Port I/O Output Latch Data Memory (RAM) General-Purpose Data Memory (except DBF and port register) DBF System Register (SYSREG) WR Control Register 8-bit Timer RESET Input in Standby Mode RESET Input during Operation 0000H 0000H Input Input 0 0 Holds previous status Undefined 0320H 0320H 0 0 Holds previous status Undefined Refer to Fig. 15-1 Register File List. Counter (TMC) 00H 00H Modulo Register (TMM) FFH FFH Holds previous status Undefined 00H 00H Shift Register of Serial Interface (SIOSFR) Holds previous status Undefined Internal Reference Voltage Setting Register of A/D Converter (ADCR) Holds previous status Undefined Remote Controller Carrier Generator Circuit NRZ High-Level Period Setting Modulo Register (NRZHTMM) NRZ Low-Level Period Setting Modulo Register (NRZLTMM) Counter of Watch Timer/Watchdog Timer 84 µPD17201A, 17207 15. ASSEMBLER RESERVED WORDS 15.1 MASK OPTION DIRECTIVES In µPD17207 programming, it is required to specify mask options in assembler source programs by mask option directives. The following mask options items must be specified: • Pull-up resistor for the RESET pin • Connection between the main clock and the subclock (for selection of system clock) 15.1.1 OPTION and ENDOP Directives A mask option is defined in a block between the OPTION and ENDOP directives. This block is formatted as shown below. Coding format: Symbol Mnemonic [Label: ] OPTION : : : ENDOP Operand Comment [;Comment] 85 µPD17201A, 17207 15.1.2 Mask Option Definition Pseudo Directives Table 15-1 shows directives available in the mask option definition block. Table 15-1 Mask Option Definition Directives Item Directives Number of Operands 1st Operand 2nd Operands RESET mask option RESET pin pull-up resistor OPTRES 1 RESPLUP (Built-in pull-up resistor) OPEN (No pull-up resistor) Main clock System clock OPTCK 2 Subclock USEX (Uses the main clock as the system clock.) NOX (Does not use the main USEXT Uses the subclock as the system clock.) NOXT (Does not use the clock.) subclock.) Remark When both the main clock and the subclock are specified as the system clock, the main clock is initially selected when the system is reset. After that, the subclock can be selected by an instruction in the program. Shown below is a coding example of mask options. Symbol Mnemonic [Label: ] OPTION Operand Comment [;Comment] OPTRES RESPLUP ; Pulls up the RESET pin. OPTCK USEX, USEXT ; Uses the main clock or subclock. ENDOP 15.2 RESERVED SYMBOLS Table 15-2 lists the symbols defined by the device file of the µPD17207. The defined symbols include the following register file names, port names, and peripheral hardware names. 15.2.1 Register File The symbol names assigned to the registers in the register file are defined. These registers are accessed via WR (window register) by the PEEK and POKE instructions. Fig. 15-1 lists the registers in the register file. 15.2.2 Registers on Data Memory and Ports The names of the registers assigned to data memory addresses 00H-7FH, ports assigned to address 70H and those that follow, and system registers are defined. Fig. 15-2 shows the configuration of the data memory. 15.2.3 Peripheral Hardware The names of the peripheral hardware that is accessed by the GET and PUT instructions are defined. Table 153 lists the peripheral hardware. 86 µPD17201A, 17207 Table 15-2 List of Reserved Symbols (1/4) Symbol Name Attribute Value R/W Description DBF3 MEM 0.0CH R/W Bit 15 to bit 12 of data buffer DBF2 MEM 0.0DH R/W Bit 11 to bit 8 of data buffer DBF1 MEM 0.0EH R/W Bit 7 to bit 4 of data buffer DBF0 MEM 0.0FH R/W Bit 3 to bit 0 of data buffer AR3 MEM 0.74H R Bit 15 to bit 12 of address register AR2 MEM 0.75H R/W Bit 11 to bit 8 of address register AR1 MEM 0.76H R/W Bit 7 to bit 4 of address register AR0 MEM 0.77H R/W Bit 3 to bit 0 of address register WR MEM 0.78H R/W Window register BANK MEM 0.79H R/W Bank register IXH MEM 0.7AH R/W Bit 11 to bit 8 of index register MPH MEM 0.7AH R/W Bit 7 to bit 4 of memory pointer MPE FLG 0.7AH.3 R/W Memory pointer enable flag IXM MEM 0.7BH R/W Bit 7 to bit 4 of index register MPL MEM 0.7BH R/W Bit 3 to bit 0 of memory pointer IXL MEM 0.7CH R/W Bit 3 to bit 0 of index register RPH MEM 0.7DH R/W Bit 7 to bit 4 of register pointer RPL MEM 0.7EH R/W Bit 3 to bit 0 of register pointer PSW MEM 0.7FH R/W Program status word BCD FLG 0.7EH.0 R/W BCD operation flag CMP FLG 0.7FH.3 R/W Compare flag CY FLG 0.7FH.2 R/W Carry flag Z FLG 0.7FH.1 R/W Zero flag IXE FLG 0.7FH.0 R/W Index register enable flag LCDD0 MEM 0.40H R/W LCD segment 0 LCDD1 MEM 0.41H R/W LCD segment 1 LCDD2 MEM 0.42H R/W LCD segment 2 LCDD3 MEM 0.43H R/W LCD segment 3 LCDD4 MEM 0.44H R/W LCD segment 4 LCDD5 MEM 0.45H R/W LCD segment 5 LCDD6 MEM 0.46H R/W LCD segment 6 LCDD7 MEM 0.47H R/W LCD segment 7 LCDD8 MEM 0.48H R/W LCD segment 8 LCDD9 MEM 0.49H R/W LCD segment 9 LCDD10 MEM 0.4AH R/W LCD segment 10 LCDD11 MEM 0.4BH R/W LCD segment 11 LCDD12 MEM 0.4CH R/W LCD segment 12 LCDD13 MEM 0.4DH R/W LCD segment 13 LCDD14 MEM 0.4EH R/W LCD segment 14 LCDD15 MEM 0.4FH R/W LCD segment 15 87 µPD17201A, 17207 Table 15-2 List of Reserved Symbols (2/4) Symbol Name Attribute Value R/W Description LCDD16 MEM 0.50H R/W LCD segment 16 LCDD17 MEM 0.51H R/W LCD segment 17 LCDD18 MEM 0.52H R/W LCD segment 18 LCDD19 MEM 0.53H R/W LCD segment 19 LCDD20 MEM 0.54H R/W LCD segment 20 LCDD21 MEM 0.55H R/W LCD segment 21 LCDD22 MEM 0.56H R/W LCD segment 22 LCDD23 MEM 0.57H R/W LCD segment 23 LCDD24 MEM 0.58H R/W LCD segment 24 LCDD25 MEM 0.59H R/W LCD segment 25 LCDD26 MEM 0.5AH R/W LCD segment 26 LCDD27 MEM 0.5BH R/W LCD segment 27 LCDD28 MEM 0.5CH R/W LCD segment 28 LCDD29 MEM 0.5DH R/W LCD segment 29 LCDD30 MEM 0.5EH R/W LCD segment 30 LCDD31 MEM 0.5FH R/W LCD segment 31 LCDD32 MEM 0.60H R/W LCD segment 32 LCDD33 MEM 0.61H R/W LCD segment 33 LCDD34 MEM 0.62H R/W LCD segment 34 LCDD35 MEM 0.63H R/W LCD segment 35 P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A P0A3 FLG 0.70H.3 R/W Bit 3 of port 0A P0B0 FLG 0.71H.0 R/W Bit 0 of port 0B P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B P0B2 FLG 0.71H.2 R/W Bit 2 of port 0B P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B P0C0 FLG 0.72H.0 R/W Bit 0 of port 0C P0C1 FLG 0.72H.1 R/W Bit 1 of port 0C P0C2 FLG 0.72H.2 R/W Bit 2 of port 0C P0C3 FLG 0.72H.3 R/W Bit 3 of port 0C P0D0 FLG 0.73H.0 R/W Bit 0 of port 0D P0D1 FLG 0.73H.1 R/W Bit 1 of port 0D P0D2 FLG 0.73H.2 R/W Bit 2 of port 0D P0D3 FLG 0.73H.3 R/W Bit 3 of port 0D P1A0 FLG 1.70H.0 R/W Bit 0 of port 1A P1A1 FLG 1.70H.1 R/W Bit 1 of port 1A P1A2 FLG 1.70H.2 R/W Bit 2 of port 1A P1A3 FLG 1.70H.3 R/W Bit 3 of port 1A 88 µPD17201A, 17207 Table 15-2 List of Reserved Symbols (3/4) Symbol Name Attribute Value R/W Description SP MEM 0.81H R/W Stack pointer SYSCK FLG 0.82H.1 R/W Selection of system clock XEN FLG 0.82H.0 R/W Main clock enable WDTRES FLG 0.83H.3 R/W Watchdog timer reset WTMMD FLG 0.83H.2 R/W Selection of watch timer mode WTMRES FLG 0.83H.1 R/W Reset of watch timer mode INT FLG 0.8FH.0 R NRZBF FLG 0.91H.0 R/W NRZ buffer data NRZ FLG 0.92H.0 R/W NRZ data ADCCMP FLG 0.0A0H.0 R/W Comparator result VREFEN FLG 0.0A1H.3 R/W A/D converter enable flag ADCEN FLG 0.0A1H.2 R/W A/D converter enable flag ADCCH1 FLG 0.0A1H.1 R/W A/D converter channel selection flag ADCCH0 FLG 0.0A1H.0 R/W A/D converter channel selection flag SIOTS FLG 0.0A2H.3 R/W Serial interface start flag SIOHIZ FLG 0.0A2H.2 R/W SO pin status SIOCK1 FLG 0.0A2H.1 R/W Serial clock selection flag for serial interface SIOCK0 FLG 0.0A2H.0 R/W Serial clock selection flag for serial interface NRZEN FLG 0.0A3H.2 R/W NRZ enable flag TMOE FLG 0.0A3H.1 R/W Timer output enable flag SIOEN FLG 0.0A3H.0 R/W SIO enable flag P0DBIO3 FLG 0.0A7H.3 R/W I/O setting flag (bit 3 of port P0D) P0DBIO2 FLG 0.0A7H.2 R/W I/O setting flag (bit 2 of port P0D) P0DBIO1 FLG 0.0A7H.1 R/W I/O setting flag (bit 1 of port P0D) P0DBIO0 FLG 0.0A7H.0 R/W I/O setting flag (bit 0 of port P0D) IPSIO FLG 0.0AFH.3 R/W INTSIO interrupt enable flag IPWTM FLG 0.0AFH.2 R/W Watch timer interrupt enable flag IP FLG 0.0AFH.1 R/W Interrupt enable flag IPTM FLG 0.0AFH.0 R/W 8-Bit timer interrupt enable flag LCDEN FLG 0.0B1H.3 R/W LCD display enable flag LCDCK2 FLG 0.0B1H.2 R/W LCD display clock selection flag LCDCK1 FLG 0.0B1H.1 R/W LCD display clock selection flag LCDCK0 FLG 0.0B1H.0 R/W LCD display clock selection flag LCDMD3 FLG 0.0B2H.3 R/W LCD display mode register bit 3 LCDMD2 FLG 0.0B2H.2 R/W LCD display mode register bit 2 LCDMD1 FLG 0.0B2H.1 R/W LCD display mode register bit 1 LCDMD0 FLG 0.0B2H.0 R/W LCD display mode register bit 0 TMEN FLG 0.0B3H.3 R/W Timer enable flag TMRES FLG 0.0B3H.2 R/W Timer reset flag TMCK1 FLG 0.0B3H.1 R/W Selection of timer clock source INT pin status 89 µPD17201A, 17207 Table 15-2 List of Reserved Symbols (4/4) Symbol Name Attribute Value R/W Description TMCK0 FLG 0.0B3H.0 R/W Selection of timer clock source P1AGIO FLG 0.0B7H.3 R/W I/O setting flag for port 1A P0CGIO FLG 0.0B7H.2 R/W I/O setting flag for port 0C P0BGIO FLG 0.0B7H.1 R/W I/O setting flag for port 0B P0AGIO FLG 0.0B7H.0 R/W I/O setting flag for port 0A IRQSIO FLG 0.0BBH.3 R/W SIO interrupt request flag IRQWTM FLG 0.0BCH.2 R/W Watch timer interrupt request flag IRQ FLG 0.0BDH.1 R/W INT interrupt request flag IRQTM FLG 0.0BEH.0 R/W 8-bit timer interrupt request flag SIOSFR DAT 01H R/W Serial interface shift register TMM DAT 02H W Modulo register for 8-bit timer TMC DAT 02H R Counter register for 8-bit timer NRZHTMM DAT 03H R/W Modulo register for NRZ low-level period NRZLTMM DAT 04H R/W Modulo register for NRZ high-level period ADCR DAT 05H R/W A/D converter internal reference voltage setting register AR DAT 40H R/W Peripheral address of address register for GET/PUT/PUSH/CALL/BR/ MOVT/INC instruction 90 µPD17201A, 17207 [MEMO] 91 µPD17201A, 17207 Fig. 15-1 Register File (1/2) Bit 3 0 Bit 2 0 (8) Bit 1 SP Bit 0 1 (9) 2 (A) 0 0 0 WDTRES 0 1 0 0 WTMMD 0 SYSCK 1 XEN ∗ Note 7 Note 6 Note 5 0 ∗ WTMRES 0 Bit 3 0 0 0 0 Bit 2 0 0 0 0 Bit 1 0 0 0 0 Bit 0 NRZBF 0 NRZ 0 0 0 Bit 3 0 0 VREFEN 0 SIOTS 0 0 0 P0DBIO3 0 Bit 2 0 0 ADCEN 0 SIOHIZ 0 NRZEN 0 P0DBIO2 0 Bit 1 0 0 ADCCH1 0 SIOCK1 0 TMOE 0 P0DBIO1 0 ADCCMP 0 ADCCH0 0 SIOCK0 0 SIOEN 0 P0DBIO0 0 Bit 0 3 (B) 4 Note Row Address 3 Note 2 Note 1 Note 0 Note Cdolumn Address Bit 3 LCDEN 0 LCDMD3 0 TMEN 1 P1AGIO 0 Bit 2 LCDCK2 0 LCDMD2 0 TMRES 0 P0CGIO 0 Bit 1 LCDCK1 0 LCDMD1 0 TMCK1 0 P0BGIO 0 Bit 0 LCDCK0 0 LCDMD0 1 TMCK0 0 P0AGIO 0 Note Status when the system is reset. ∗: When the mask option selects the main clock (USEX): 1 When the mask option does not select the main clock (NOX): 0 Fig. 15-2 Data Memory Configuration 0 1 2 3 4 5 6 Column address 7 8 9 A B C D E F DBF3 DBF2 DBF1 DBF0 0 DBF Row address 1 2 3 4 5 6 7 AR3 AR2 AR1 AR0 WR BANK IXH System register P0D0 - P0D3 P0C0 - P0C3 P0B0 - P0B3 P0A0 - P0A3 P1A0 - P1A3 92 IXM IXL RPH RPL PSW µPD17201A, 17207 Fig. 15-1 Register File (2/2) F Note E Note D Note C Note B Note Row Address A Note 9 Note 8 Note Cdolumn Address Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 INT P Bit 3 IPSIO 0 2 Bit 2 IPWTM 0 (A) Bit 1 IP 0 Bit 0 IPTM 0 0 (8) Bit 3 Bit 2 1 (9) Bit 1 Bit 0 3 (B) 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ 0 0 0 0 0 0 0 IRQTM 0 0 Bit 3 IRQSIO Bit 2 0 0 IRQWTM Bit 1 0 0 Bit 0 0 0 Note Status when the system is reset. P: When the INT pin goes high: 1 When the INT pin goes low: 0 Remark ( ) indicates an address to be used when the assembler is used. All the flags of the control registers are registered to the device file as assembler reserved words. It is convenient to use these reserved words when you develop a program. Table 15-3 Peripheral Hardware Name Address Valid Bit Remarks SIOSFR 01H 8 Shift register of serial interface TMC 02H 8 Count register of 8-bit timer TMM 02H 8 Modulo register of 8-bit timer NRZLTMM 03H 8 Low-level period setting modulo register for remote controller carrier generator NRZHTMM 04H 8 High-level period setting modulo register for remote controller carrier generator ADCR 05H 8 Compare voltage setting register of A/D converter AR 40H 16 Address register 93 µPD17201A, 17207 16. 16.1 INSTRUCTION SET OUTLINE OF INSTRUCTION SETS b15 b14-b11 0 1 BIN HEX 0000 0 ADD r, m ADD m, #n4 0001 1 SUB r, m SUB m, #n4 0010 2 ADDC r, m ADDC m, #n4 0011 3 SUBC r, m SUBC m, #n4 0100 4 AND r, m AND m, #n4 0101 5 XOR r, m XOR m, #n4 0110 6 OR r, m OR m, #n4 INC AR INC IX MOVT DBF, @AR BR @AR CALL @AR RET RETSK EI DI 0111 7 RETI PUSH AR POP AR GET DBF, p PUT p. DBF PEEK WR, rf POKE rf, WR RORC r STOP s HALT h NOP 94 1000 8 LD r, m ST m, r 1001 9 SKE m, #n4 SKGE m, #n4 1010 A MOV @r, m MOV m, @r 1011 B SKNE m, #n4 SKLT m, #n4 1100 C BR addr (Page 0) CALL addr (Page 0) 1101 D BR addr (Page 1) MOV m, #n4 1110 E SKT m, #n 1111 F SKF m, #n µPD17201A, 17207 16.2 LEGEND AR : Address register ASR : Address stack register specified by stack pointer addr : Program memory address (lower 11 bits) BANK : Bank register CMP : Compare flag CY : Carry flag DBF : Data buffer h : Halt releasing condition INTEF : Interrupt enable flag INTR : Register automatically saved to stack in case of interrupt INTSK : Interrupt stack register IX : Index register MP : Data memory row address pointer MPE : Memory pointer enable flag : Data memory address specified by mR, mC m mR : Data memory row address (high) mC : Data memory column address (low) n : Bit position (4 bits) n4 : Immediate data (4 bits) PAGE : Page (Bit 11 of program counter) PC : Program counter p : Peripheral address pH : Peripheral address (higher 3 bits) pL : Peripheral address (lower 4 bits) r : General register column address rf : Register file address rfR : Register file address (higher 3 bits) rfC : Register file address (lower 4 bits) SP : Stack pointer s : Stop releasing condition WR : Window register (×) : Contents addressed by × 95 µPD17201A, 17207 16.3 LIST OF INSTRUCTION SETS Group Mnemonic Operand Instruction Code Operation OP code r, m (r) ← (r) + (m) 00000 mR mC r m, #n4 (m) ← (m) + n4 10000 mR mC n4 r, m (r) ← (r) + (m) + CY 00010 mR mC r m, #n4 (m) ← (m) + n4 + CY 10010 mR mC n4 AR AR ← AR +1 00111 000 1001 0000 IX IX ← IX +1 00111 000 1000 0000 r, m (r) ← (r) – (m) 00001 mR mC r m, #n4 (m) ← (m) – n4 10001 mR mC n4 r, m (r) ← (r) – (m) – CY 00011 mR mC r m, #n4 (m) ← (m) – n4 – CY 10011 mR mC n4 r, m (r) ← (r) ∨ (m) 00110 mR mC r m, #n4 (m) ← (m) ∨ n4 10110 mR mC n4 r, m (r) ← (r) ∧ (m) 00100 mR mC r m, #n4 (m) ← (m) ∧ n4 10100 mR mC n4 r, m (r) ← (r) ∀ (m) 00101 mR mC r m, #n4 (m) ← (m) ∀ n4 10101 mR mC n4 SKT m, #n CMP ← 0, if (m) ∧ n = n, then skip 11110 mR mC n SKF m, #n CMP ← 0, if (m) ∧ n = 0, then skip 11111 mR mC n SKE m, #n4 (m)-n4, skip if zero 01001 mR mC n4 SKNE m, #n4 (m)-n4, skip if not zero 01011 mR mC n4 SKGE m, #n4 (m)-n4, skip if not borrow 11001 mR mC n4 SKLT m, #n4 (m)-n4, skip if borrow 11011 mR mC n4 RORC r 00111 000 0111 r LD r, m (r) ← (m) 01000 mR mC r ST m, r (m) ← (r) 11000 mR mC r @r, m if MPE = 1 : (MP, (r)) ← (m) if MPE = 0 : (BANK, mR, (r)) ← (m) 01010 mR mC r m, @r if MPE = 1 : (m) ← (MP, (r)) if MPE = 0 : (m) ← (BANK, mR, (r)) 11010 mR mC r m, #n4 (m) ← n4 11101 mR mC n4 DBF, @AR SP ← SP – 1, ASR ← PC, PC ← AR DBF ← (PC), PC ← ASR, SP ← SP + 1 00111 000 0001 0000 ADD Addition ADDC INC SUB Subtraction SUBC OR Logical AND XOR Judge Compare Operand CY → (r)b3 → (r)b2 → (r)b1 → (r)b0 Rotate Transfer MOV MOVT Note Note Two instruction cycles are necessary only for executing the MOVT instruction. 96 µPD17201A, 17207 Group Mnemonic Operand Instruction Code Operation OP code Transfer PUSH AR SP ← SP – 1, ASR ← AR 00111 000 1101 0000 POP AR AR ← ASR, SP ← SP +1 00111 000 1100 0000 PEEK WR, rf WR ← (rf) 00111 rfR 0011 rfC POKE rf, WR (rf) ← WR 00111 rfR 0010 rfC GET DBF, p (DBF) ← (p) 00111 pH 1011 pL PUT p, DBF (p) ← (DBF) 00111 pH 1010 pL PC10–0 ← addr, PAGE ← 0 01100 PC10–0 ← addr, PAGE ← 1 01101 @AR PC ← AR 00111 addr SP ← SP – 1, ASR ← PC PC10–0 ← addr, PAGE ← 0 11100 @AR SP ← SP – 1, ASR ← PC PC ← AR 00111 RET PC ← ASR, SP ← SP +1 RETSK addr Branch BR CALL Other addr 000 0100 0000 addr 000 0101 0000 00111 000 1110 0000 PC ← ASR, SP ← SP +1 and skip 00111 001 1110 0000 RETI PC ← ASR, INTR ← INTSK, SP ← SP +1 00111 100 1110 0000 EI INTEF ← 1 00111 000 1111 0000 DI INTEF ← 0 00111 001 1111 0000 Subroutine Interrupt Operand STOP s STOP 00111 010 1111 s HALT h HALT 00111 011 1111 h No operation 00111 100 1111 0000 NOP 97 µPD17201A, 17207 16.4 ASSEMBLER (AS17K) EMBEDDED MACROINSTRUCTIONS Legend flag n : FLG symbol n : Bit number <> : Can be omitted Mnemonic Operation n Embedded SKTn flag 1, ... flag n if (flag 1) ~ (flag n) = all “1”, then skip 1≤n≤4 macro SKFn flag 1, ... flag n if (flag 1) ~ (flag n) = all “0”, then skip 1≤n≤4 SETn flag 1, ... flag n (flag 1) ~ (flag n) ← 1 1≤n≤4 CLRn flag 1, ... flag n (flag 1) ~ (flag n) ← 0 1≤n≤4 NOTn flag 1, ... flag n if (flag n) = “0”, then (flag n) ← 1 if (flag n) = “1”, then (flag n) ← 0 1≤n≤4 INITFLG <NOT> flag 1, ... <<NOT> flag n> if description = NOT flag n, then (flag n) ← 0 if description = flag n, then (flag n) ← 1 1≤n≤4 (BANK) ← n 0≤n≤2 BANKn 98 Operand µPD17201A, 17207 17. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Symbol Test Condition Rating Unit Supply voltage VDD –0.3 to+7.0 V Analog supply voltage VADC –0.3 to VDD+0.3 V Input voltage VI –0.3 to VDD+0.3 V Output voltage VO –0.3 to VDD+0.3 V Peak value –30 mA Effective value –20 mA Peak value –7.5 mA –5 mA –22.5 mA Effective value –15 mA Peak value 7.5 mA 5 mA 22.5 mA 15 mA REM pin High-level output current IOH One pin (except REM) Effective value All pins (except REM) One pin Low-level output current Peak value Effective value IOL All pins (except REM) Peak value Effective value Operating ambient temperature TA –20 to +75 °C Storage temperature Tstg –40 to +125 °C Note Effective value = Peak value x √Duty Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. CAPACITANCE (TA = 25°C, VDD = 0 V) Parameter Input capacitance Symbol CIN Test Condition INT, SI, and RESET pins MIN. TYP. MAX. Unit 10 pF 99 µPD17201A, 17207 RECOMMENDED OPERATING RANGES (TA = –20 to +75°C) Parameter Symbol Supply voltage Test Condition MIN. TYP. MAX. Unit VDD1 System clock fX = 4 MHz 2.2 3.0 5.5 V VDD2 System clock fX = 8 MHz 4.5 5.0 5.5 V VDD3 System clock fXT = 32.768 kHz 2.0 3.0 5.5 V 1.0 4 8.0 MHz Main clock oscillation frequency fX Subclock oscillation frequency fXT 32.768 fX vs VDD (MHz) 10 9 8 7 6 Main system clock (fX) 5 4 3 Guaranteed operation range 2 1 2.2 4.5 5.5 0.5 0 2 3 4 Supply voltage (VDD) 100 5 6 (V) kHz µPD17201A, 17207 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –20 to +75°C, VDD = 2.2 to 5.5 V) Resonator Constants Recommended XIN Conditions Oscillation frequency XOUT (fX)Note 1 CeramicNote 3 oscillator C1 Item C2 Oscillation stabilization timeNote 2 MIN. TYP. MAX. Unit 1.0 4 8.0 MHz 4 ms 8.0 MHz 10 ms 30 ms From when VDD reaches the minimum oscillation voltage Oscillation frequency XIN XOUT 1.0 (fX)Note 1 CrystalNote 3 oscillator C1 C2 Oscillation stabilization time Notes 1. 4 VDD = 4.5 to 5.5V Note 2 The oscillation frequency is indicated only to express the oscillator characteristics. The oscillation stabilization time is the time required for stabilizing the oscillation after VDD is applied or 2. the STOP mode is released. 3. The recommended oscillators are shown in the table described later. SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS Resonator Constants Recommended XIN XOUT Crystal oscillator Item Oscillation frequency (fXT) Oscillation stabilization time Conditions MIN. TYP. MAX. 32.768 5 Unit kHz 10 s Caution When using the main system clock and the subsystem clock generators, in order to avoid wiring capacitance effects, the following notations must be read and observed for wiring the portion inside the dotted line in the table: • Wiring length must be minimized. • Do not cross with other signal lines. Do not wire close to a large current line. • Capacitors used in the oscillators must always be grounded to GND potential level. Never ground the grounding pattern having a large current flow. • Do not take the signal directly out of the oscillator. In order to reduce the power consumption, the subsystem clock oscillator employs a low amplification factor circuit. Because of this, the subsystem clock oscillator is more sensitive to noise than the main system clock oscillator. Therefore, when using the subsystem clock, wiring must be carefully planned. 101 µPD17201A, 17207 RECOMMENDED OSCILLATORS Main System Clock Oscillator (made of ceramic) Manufacturer MURATA Mfg. External Capacitance Oscillation Voltage Range (pF) (V) Part Name Remarks C1 C2 MIN. MAX. CSA3.58MG 30 30 2.0 6.0 CSA4.00MG 30 30 2.0 6.0 CSA4.19MG 30 30 2.0 6.0 CST3.58MGW Not required Not required 2.0 6.0 CST4.00MGW Not required Not required 2.0 6.0 CST4.19MGW Not required Not required 2.0 6.0 KBR3.58MS 33 33 2.0 6.0 KBR4.0MS 33 33 2.0 6.0 KBR4.19MS 33 33 2.0 6.0 TOKO CRHF4.00 18 18 2.0 6.0 DAISHINKU PRS0400BCSAN 39 33 2.0 6.0 KYOCERA Built-in capacitor Main System Clock Oscillator (made of crystal) Manufacturer Frequency 102 4.0 Oscillation Voltage Range (pF) (V) Holder (MHz) KINSEKI External Capacitance HC-49U-S Remarks C1 C2 MIN. MAX. 22 22 2.0 6.0 µPD17201A, 17207 DC CHARACTERISTICS (TA = –20 to +75°C, VDD = VADC = 2.2 to 3.6 V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Current Low-Level Output Current Built-In Pull-Up Resistor Symbol Test Condition MIN. TYP. RESET and INT pins 0.8VDD VDD V VIH2 Other than RESET and INT pins 0.7VDD VDD V VIL1 RESET and INT pins 0 0.2VDD V VIL2 Other than RESET and INT pins 0 0.3VDD V ILIH1 XTIN, XTOUT, XIN, and XOUT pins 20 µA ILIH2 Other than XTIN, XTOUT, XIN, and XOUT pins 3 µA ILIL1 XTIN, XTOUT, XIN, and XOUT pins –20 µA ILIL2 Other than XTIN, XTOUT, XIN, and XOUT pins –3 µA IOH1 REM pin VOH=VDD-1.2 V –7 –15 mA IOH2 Note 1 VOH=VDD-0.3 V –0.3 –0.7 mA IOL Note 2 VOL=0.3 V 0.5 0.9 mA RP0A P0A0 to P0A3 pins 100 200 350 kΩ RRES RESET pins (mask option) 24 47 94 kΩ ±2 LSB A/D Resolution 8 IADC Comparator Error Supply Current In comparator mode bits 60 120 µA 10 20 mV IDD1 X installed (fx=4.19 MHz) RUN mode 0.8 2.0 mA IDD2 XT not installed HALT mode 0.3 1.5 mA STOP mode 2.0 10 µA RUN mode 7.0 25 µA HALT mode 3.0 15 µA IDD3 VDD=3 V IDD4 X not installed or STOP mode XT installed VDD=3 V (fXT=32.768 kHz) IDD5 Notes 1. Unit VIH1 A/D Absolute Precision A/D Converter Circuit Current MAX. Note 3 P0A0 to P0A3, P0D0 to P0D3, and P1A0 to P1A2 pins 2. P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P0D0 to P0D3, P1A0 to P1A2, WDOUT, and REM pins 3. The specifications of the main STOP mode (sub-mounting) are the same as the sub-HALT mode (with the main clock oscillation stopped). LCD CHARACTERISTICS (TA = –20 to +75°C, VDD = 2.2 to 3.6 V) Parameter Symbol Test Condition MIN. TYP. MAX. Unit 0.6 0.7 V 1.8 V VLCDC Output Voltage VLCDC VDD = 3 V, Ta = 25°C, R1 = R2 = 1 MΩ 0.5 LCD Reference Output Voltage VLCD0 External variable resistance (0 to 2.2 MΩ) 0.8 Doubler Output Voltage VLCD1 C1 to C4 = 0.47 µF 1.9 2.0 VLCD0 Tripler Output Voltage VLCD2 C1 to C4 = 0.47 µF 2.85 3.0 VLCD0 LCD Common Output Current ICOM Output voltage deviation = 0.2 V 30 µA LCD Segment Output Current ILCD Output voltage deviation = 0.2 V 5 µA 103 µPD17201A, 17207 DC CHARACTERISTICS (TA = –20 to +75°C, VDD = VADC = 5 V±10%) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Leakage current Low-Level Input Leakage current High-Level Output Current Low-Level Output Current Built-In Pull-Up Resistor Symbol Test Condition MIN. TYP. RESET and INT pins 0.8VDD VDD V VIH2 Other than RESET and INT pins 0.7VDD VDD V VIL1 RESET and INT pins 0 0.2VDD V VIL2 Other than RESET and INT pins 0 0.3VDD V ILIH1 XTIN, XTOUT, XIN, and XOUT pins 20 µA ILIH2 Other than XTIN, XTOUT, XIN, and XOUT pins 3 µA ILIL1 XTIN, XTOUT, XIN, and XOUT pins –20 µA ILIL2 Other than XTIN, XTOUT, XIN, and XOUT pins –3 µA IOH1 REM pin VOH = VDD-0.6 V –7 –15 mA IOH2 Note 1 VOH = VDD-0.3 V –0.8 –1.2 mA IOL Note 2 VOL = 0.3 V 1.0 1.5 mA RP0A P0A0 to P0A3 pins 140 200 350 kΩ RRES RESET pins (mask option) 27 47 94 kΩ ±2 LSB A/D Resolution 8 IADC Comparator Error Supply Current In comparator mode bits 60 120 µA 10 20 mV IDD1 X installed (fx=4.19 MHz) RUN mode 1.8 5.0 mA IDD2 XT not installed HALT mode 0.6 2.0 mA STOP mode 2.6 20 µA RUN mode 10.5 40 µA HALT mode 6.0 20 µA IDD3 VDD = 5 V IDD4 X not installed or STOP mode XT installed VDD = 5 V (fX = 32.768 kHz) IDD5 Notes 1. Unit VIH1 A/D Absolute Precision A/D Converter Circuit Current MAX. P0A0 to P0A3, P0D0 to P0D3, and P1A0 to P1A2 pins 2. P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P0D0 to P0D3, P1A0 to P1A2, REM, and WDOUT pins 3. The specifications of the main STOP mode (sub-mounting) are the same as the sub-HALT mode (with the main clock oscillation stopped). LCD CHARACTERISTICS (TA = –20 to +75°C, VDD = 5 V±10%) Parameter Symbol Test Condition MIN. TYP. MAX. Unit 1.8 V LCD Reference Output Voltage VLCD0 External variable resistance (0 to 2.2 MΩ) 0.8 Doubler Output Voltage VLCD1 C1 to C4 = 0.47 µF 1.9 2.0 VLCD0 Tripler Output Voltage VLCD2 C1 to C4 = 0.47 µF 2.85 3.0 VLCD0 LCD Common Output Current ICOM Output voltage deviation = 0.2 V 30 µA LCD Segment Output Current ILCD Output voltage deviation = 0.2 V 5 µA 104 µPD17201A, 17207 AC CHARACTERISTICS (TA = –20 to +75°C, VDD = 2.2 to 5.5 V) Parameter Symbol Test Condition VDD =5 V±10 % SCK Input Cycle Time tKCY VDD =5 V±10 % MIN. TYP. MAX. Unit Data Input 2.0 µs Data Output 10 µs Data Input 5 µs Data Output 13 µs Data Input 1.0 µs SCK Input High- and Low-Level tKH, Data Output 5.0 µs Widths tKL Data Input 2.5 µs Data Output 6.5 µs SI Setup Time (vs. SCK↑) tSIK 100 ns SI Hold Time (vs. SCK↑) tKSI 100 ns SCK↓→to SO Output Delay Time tKSO INT High- and Low-Level Width tIOH, tIOL 50 µs RESET Low-Level Width tRSL 50 µs P0A Low-Level Width tRLSL 10 µs CL =100 pF 4.5 Standby Release µs SERIAL TRANSFER TIMING 3-line Serial I/O Mode tKCY tKL tKH SCK tSIK SI tKSI Input data tKSO SO Output data 105 µPD17201A, 17207 18. PERFORMANCE CURVE (REFERENCE VALUE) IDD1 vs VDD (TA = 25 ˚C) 4.0 XIN XOUT Ceramic oscillator XTIN XTOUT Crystal resonator 32.768 kHz 3.0 Operating supply current IDD1 (mA) fX = 8 MHz operation mode 2.0 fX = 4 MHz operation mode fX = 2 MHz operation mode 1.0 fX = 8 MHz HALT mode fX = 4 MHz HALT mode fX = 2 MHz HALT mode 0 1.0 2.2 2.0 3.0 4.0 Supply voltage VDD (V) 106 5.0 5.5 6.0 µPD17201A, 17207 IDD1 vs fX (Operation mode) (TA = 25 ˚C) 4.0 Operating supply current IDD1 (mA) 3.0 VDD = 5.0 V 2.0 VDD = 4.0 V VDD = 3.0 V VDD = 2.5 V 1.0 0 0 1 2 4 8 fX (MHz) IDD2 vs fX (HALT mode) 3.0 (TA = 25 ˚C) HALT current IDD2 (mA) 2.0 1.0 VDD = 5.0 V VDD = 4.0 V VDD = 3.0 V VDD = 2.5 V 0 0 1 2 4 8 fX (MHz) 107 µPD17201A, 17207 IOH1 (REM) vs VDD -VOH _40 IOH2 (P0A) vs VDD -VOH (TA = 25 ˚C) _40 VDD = 5 V (TA = 25 ˚C) VDD = 5 V High-level output current I OH2 (P0A) (mA) High-level output current IOH1 (REM) (mA) VDD = 4 V _30 _20 VDD = 3 V _10 0 1 2 3 4 5 VDD -VOH (V) IOH2 (P1A) vs VDD -VOH _40 (TA = 25 ˚C) VDD = 5 V High-level output current IOH2 (P1A) (mA) VDD = 4 V _30 _20 VDD = 3 V _10 0 108 1 2 3 4 5 VDD -VOH (V) _30 VDD = 4 V _20 VDD = 3 V _10 0 1 2 3 4 5 VDD -VOH (V) µPD17201A, 17207 IOL (REM) vs VOL IOL (P0A) vs VOL (TA = 25 ˚C) 40 (TA = 25 ˚C) 40 VDD = 5 V VDD = 5 V Low-level output current IOL (P0A) (mA) Low-level output current IOL (REM) (mA) VDD = 4 V 30 20 VDD = 3 V 10 0 1 2 VDD = 4 V 30 20 VDD = 3 V 10 0 3 4 5 Low level output voltage VOL (V) 1 IOL (P0B) vs VOL 3 4 5 Low level output voltage VOL (V) IOL (P1A) vs VOL (TA = 25 ˚C) 40 2 (TA = 25 ˚C) 40 VDD = 5 V VDD = 5 V 30 20 VDD = 3 V 10 0 1 2 3 4 5 Low level output voltage VOL (V) VDD = 4 V Low-level output current IOL (P1A) (mA) Low-level output current IOL (P0B) (mA) VDD = 4 V 30 20 VDD = 3 V 10 0 1 2 3 4 5 Low level output voltage VOL (V) 109 µPD17201A, 17207 19. EXAMPLE OF APPLICATION CIRCUIT • Remote Controller for Air Conditioner 0.47 µ F 2 MW 32 kHz 0.47 µ F 0.47 µ F 0.1 µ F 0.47 µ F 0.1 µ F 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 4 MHz 64 2 63 3 62 4 REM 61 5 60 6 59 7 58 8 57 9 10 11 LCD 12 13 14 15 16 µ PD17207GF–×××–3BE 1 56 55 Slide SW LED 53 52 51 50 48 47 19 46 20 45 21 44 22 43 VADC ADC0 ADC1 ADC2 Standby mode release keys 42 INT 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Option SW input VDD Temperature Humidity sensor sensor 110 Key matrix 49 18 24 3V 54 17 23 VDD Sensor error detection µPD17201A, 17207 20. PACKAGE DRAWINGS PACKAGE DRAWINGS OF MASS-PRODUCTION PRODUCT 80 PIN PLASTIC QFP (14 20) A B 64 65 41 40 detail of lead end C D S Q R 25 24 80 1 F J G H I M P K M N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 23.2±0.2 0.913 +0.009 –0.008 B 20.0±0.2 0.787 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.2 0.677±0.008 F 1.0 0.039 G 1.8 0.031 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 0.005±0.003 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GF-80-3B9-3 Caution The ES and mass-production products differ in external shape and materials. Please refer to the package drawing for the ES product. 111 µPD17201A, 17207 ES PRODUCT PACKAGE DRAWINGS ES 80-PIN CERAMIC QFP (For Reference) (UNIT: mm) 20.0 41 1 24 12.0 64 0.32 0.15 2.25 0.8 14.2 18.4 Bottom Caution 1. 112 The metal cap is connected to pin 33 and is at the GND level. 2. Leads on the bottom of the package are guided slantingly. 3. Package length does not include end flash burr. µPD17201A, 17207 21. RECOMMENDED SOLDERING CONDITIONS For the µPD17207, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document “Semiconductor Device Mounting Technology Manual” (C10535E). For other soldering methods, please consult with NEC personnel. Table 21-1 Soldering Conditions of Surface Mount Type µPD17201AGF-xxx-3B9: 80-pin plastic QFP (14 × 20 mm) µPD17207GF-xxx-3B9: 80-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions o Symbol o Infrared Reflow Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 2 max., Days: 7 daysNote (after that, prebaking is necessary for 20 o hours at 125 C) <Caution> Cannot be baked while packed in anything other than a heat-resistant tray (i.e. magazine, taping or non-heat resistant tray). VPS Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 2 max., Days: 7 daysNote (after that, prebaking is necessary for 20 o hours at 125 C) <Caution> Cannot be baked while packed in anything other than a heat-resistant tray (i.e. magazine, taping or non-heat resistant tray). VP15-207-2 Wave Soldering Solder bath temperature: 260oC max., Time: 10 seconds max. Number of times: 1, Pre-heating temperature: 120°C max. (package surface temperature), Days: 7 daysNote (after that, prebaking is necessary for 20 hours at 125°C) WS60-207-1 Partial Heating Pin temperature: 300oC max., Time: 3 seconds max. (per side of device) o Note IR35-207-2 o The number of days the device can be stored after the dry pack was opened, under storage conditions of o 25 C and 65% RH max. Caution Do not use two or more soldering methods in combination (except the partial heating method). 113 µPD17201A, 17207 APPENDIX A. DIFFERENCES BETWEEN µPD17P207 AND µPD17201A/17207 The µPD17P207 has a PROM to which the user can write a program in place of the internal mask ROM of the µPD17201A and 17207. Therefore, the µPD17P207 is identical to µPD17201A and 17207 except for the program memory and mask option. However, some of the electrical characteristics, such as supply current and VLCD0 voltage of the µPD17P207, are different from that of the µPD17201A and 17207. The following table lists the differences between the µPD17P207 and µPD17201A/17207. Item Product Name µPD17P207 –001 µPD17P207 –002 µPD17P207 –003 µPD17201A One-Time PROM Program Memory Pull-Up Resistor of RESET Pin Main Clock Oscillator Circuit Subclock Oscillator Circuit Mask ROM 0000H-0FFFH 0000H-0BFFH 0000H-0FFFH 4096 × 16 bits 3072 × 16 bits 4096 × 16 bits Not provided Provided Not provided Provided Not provided VPP Pin, PROM Program Pin Supply Voltage (TA = –20 to +75°C) µPD17207 Any (mask option) Provided Provided VDD = 2.5 to 5.5 V (at fX = 4 MHz) VDD = 2.4 to 5.5 V (at fX = 4 MHz, TA = –20 to +60°C) Not provided VDD = 2.2 to 5.5 V (at fX = 4 MHz) 80-pin plastic QFP (14 × 20 mm) Package Caution When using the µPD17P207-001, be sure to connect an oscillator to both the main clock oscillation circuit and subclock oscillation circuit. 114 µPD17201A, 17207 APPENDIX B. FUNCTIONAL COMPARISON OF µPD17201A/17207 RELATED PRODUCTS Product Name Item ROM Capacity (bits) µPD17201A µPD17207 µPD17215 µPD17216 µPD17217 µPD17218 3072 × 16 4096 × 16 2048 × 16 4096 × 16 6144 × 16 8192 × 16 RAM Capacity (bits) 336 × 4 LCD Controller/Drive 136 segments max. Not provided LED output is high-active Internal (no LED output) 19 lines 20 lines 1 line (rising-edge detection) 1 line (rising-edge, falling-edge detection) 4 channels (8-bit A/D) Not provided Infrared Remote Controller Carrier Generator (REM) I/O Ports External Interrupt (INT) Analog Input 111 × 4 8-bit timer Timer 2 channels Watch timer Watchdog Timer 8-bit timer 2 channels Basic interval timer Internal (WDOUT output) Low-Voltage Detection Circuit Serial Interface Not provided Internal (WDOUT output) 1 channel Not provided Stack 5 levels (3 levels for multiplexed interrupt) 4 µs (4 MHz: with ceramic Instruction 233 × 4 Main System Clock or crystal oscillator) • 2 µs (8 MHz ceramic oscilator: in high-speed mode) • 4 µs (4 MHz ceramic oscilator: in high-speed mode) • 16 µs (1 MHz ceramic oscilator: in high-speed mode) Execution Time Subsystem Clock 488 µs (32.768 kHz: Not provided with crystal oscillator) Supply Voltage Main System Clock 2.2 to 5.5 V (at fX = 4 MHz) Subsystem Clock 2.0 to 5.5 V (at fXT = 32.768 kHz) Standby Function Pakcage 2.2 to 5.5 V (at fX = 4 MHz, in high speed) Not provided STOP, HALT 80-pin plastic QFP 28-pin plastic SOP 28-pin plastic shrink DIP One-Time PROM Product µPD17P207 µPD17P218 Caution The electrical characteristics differ between the mask ROM model and one-time PROM model. 115 µPD17201A, 17207 APPENDIX C. DEVELOPMENT TOOLS The following tools are available for development of µPD17207 progams: Hardware Name Outline The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators that can be commonly used with the 17K series products. The IE-17K and IE-17K-ET are connected to the host machine, which is a PC-9800 series product or IBM PC/ATTM, via RS-232-C. The EMU-17K is inserted into an expansion slot of a PC-9800 series product. When these in-circuit emulators are used in combination with a system evaluation board (SE board) dedicated to each model of the device, they operate as the emulator dedicated to that model. A more sophisticated debugging environment can be created by using the man-machine interface software, SIMPLEHOSTTM. The EMU-17K has a function that allows you to check the contents of the data memory realtime. In-circuit Emulators IE-17K IE-17K-ETNote 1 EMU-17KNote 2 SE Board (SE-17207) The SE-17207 is an SE board for the µPD17201A, 17207, and 17P207. It may be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. Emulation Probe The EP-17201GF is an emulation probe for the µPD17201A, 17207, and 17P207. (EP-17201GF) It connects an SE board and the target system. Conversion Socket (EV-9200G-80Note 3) The EV-9200G-80 is a socket for an 80-pin QFP (14 x 20 mm) and connects the EP17201GF and the target system. PROM Programmer Note 4 Note 4 (AF-9703 , AF-9704 Note 4 Note 4 AF-9705 , AF-9706 ) Program Adapter (AF-9808A Notes 1. Note 4 ) The AF9703, AF9704, AF9705, and AF9706 are PROM programmers that can program the µ PD17P207. When connected with programmer adapter AF-9808A, this PROM programmer can program the µPD17P207. The AF-9808A is an adapter for programming the µPD17P207 and is used in combination with the AF-9703, AF-9704, AF-9705 and AF-9706. Low-cost model: external power supply type 2. This is a product from I.C Corp. For details, consult I.C Corp. 3. Two EV-9200G-80s are supplied with the EP-17201GF. Five EV-9200G-80s are optionally available as a set. 4. 116 These are products from Ando Electric Co., Ltd. For details, consult Ando Electric. µPD17201A, 17207 Software Name Outline Machine AS17K is an assembler in common with the 17K series products. When developing the program of the µ PD17201A and the µ PD17207, AS17K is used in combination with a device file (AS17201A, AS17207). 17K Series Assembler (AS17K) AS17201 is a device file for µPD17201A, and it is used in combination with an assembler for the 17K series (AS17K) Device File (AS17201) AS17207 is a device file for µPD17207, and it is used in combination with an assembler for the 17K series (AS17K). Device File (AS17207) Support Software (SIMPLEHOST) SIMPLEHOST is a software package that enables man-machine interface on the WINDOWSTM when a program is developed by using an incircuit emulator and a personal computer. Host OS Media PC-9800 series MS-DOSTM IBM PC/AT PC-9800 series IBM PC/AT PC-9800 series IBM PC/AT PC DOSTM MS-DOS PC DOS MS-DOS PC DOS PC-9800 series MS-DOS Windows IBM PC/AT PC DOS Supply Order Code 5" 2HD µS5A10AS17K 3.5" 2HD µS5A13AS17K 5" 2HC µS7B10AS17K 3.5" 2HC µS7B13AS17K 5" 2HD µS5A10AS17201 3.5" 2HD µS5A13AS17201 5" 2HC µS7B10AS17201 3.5" 2HC µS7B13AS17201 5" 2HD µS5A10AS17207 3.5" 2HD µS5A13AS17207 5" 2HC µS7B10AS17207 3.5" 2HC µS7B13AS17207 5" 2HD µS5A10IE17K 3.5" 2HD µS5A13IE17K 5" 2HC µS7B10IE17K 3.5" 2HC µS7B13IE17K Remark The corresponding OS versions are as follows: OS Version MS-DOS Ver. 3.30 to Ver. 5.00ANote PC DOS Ver. 3.1 to Ver. 5.0Note Windows Ver. 3.0 to Ver. 3.1 Note Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software. 117 µPD17201A, 17207 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 118 µPD17201A, 17207 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 119 µPD17201A, 17207 SIMPLEHOST is a trademark of NEC Corporation MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5