LM4940
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LM4940
6W Stereo Audio Power Amplifier
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FEATURES
DESCRIPTION
•
The LM4940 is a dual audio power amplifier primarily
designed for demanding applications in flat panel
monitors and TVs. It is capable of delivering 6 watts
per channel to a 4Ω load with less than 10% THD+N
while operating on a 14.4VDC power supply.
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23
•
•
•
•
•
•
Click and Pop Circuitry Eliminates Noise
During Turn-On and Turn-Off Transitions
Low Current, Active-Low Shutdown Mode
Low Quiescent Current
Stereo 6W Output, RL = 4Ω
Short Circuit Protection
Unity-Gain Stable
External Gain Configuration Capability
APPLICATIONS
•
•
•
Boomer™ audio power amplifiers were designed
specifically to provide high quality output power with a
minimal amount of external components. The
LM4940 does not require bootstrap capacitors or
snubber circuits. Therefore, it is ideally suited for
display applications requiring high power and minimal
size.
Flat Panel Monitors
Flat Panel TVs
Computer Sound Cards
The LM4940 features a low-power consumption
active-low shutdown mode. Additionally, the LM4940
features an internal thermal shutdown protection
mechanism along with short circuit protection.
KEY SPECIFICATIONS
The LM4940 contains advanced pop and click
circuitry that eliminates noises which would otherwise
occur during turn-on and turn-off transitions.
•
•
•
Quiscent Power Supply Current: 40mA (max)
(SE)
POUT
VDD = 14.4V, RL = 4Ω, 10% THD+N: 6 W (typ)
Shutdown Current: 40µA (typ)
The LM4940 is a unity-gain stable and can be
configured by external gain-setting resistors.
TYPICAL APPLICATION
Figure 1. Typical Stereo Audio Amplifier Application Circuit
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2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Boomer is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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CONNECTION DIAGRAM
U = Wafer Fab Code, Z = Assembly Plant Code, XY = Date Code, TT = Die Traceability
Plastic Package, DDPAK
Top View
See Package Number KTW
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS (1) (2) (3)
Supply Voltage (pin 6, referenced to GND, pins 4 and 5)
18.0V
−65°C to +150°C
Storage Temperature
Input Voltage
Pins 3 and 7
Pins 1, 2, 8, and 9
−0.3V to VDD + 0.3V
−0.3V to 9.5V
(4)
Internally limited
ESD Susceptibility (5)
2000V
ESD Susceptibility (6)
200V
Power Dissipation
Junction Temperature
Thermal Resistance
150°C
θJC (KTW)
θJA (KTW) (4)
4°C/W
20°C/W
θJC (NEC)
θJA (NEC) (4)
(1)
(2)
(3)
(4)
(5)
(6)
4°C/W
20°C/W
All voltages are measured with respect to the GND pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device
performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is P DMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is
lower. For the LM4940 typical application (shown in Figure 1) with VDD = 12V, RL = 4Ω stereo operation the total power dissipation is
3.65W. θJA = 20°C/W for both DDPAK and TO–220 packages mounted to 16in2 heatsink surface area.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF–240pF discharged through all pins.
OPERATING RATINGS
Temperature Range (TMIN ≤ TA ≤ TMAX)
−40°C ≤ T A ≤ 85°C
10V ≤ VDD ≤ 16V
Supply Voltage
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ELECTRICAL CHARACTERISTICS VDD = 12V (1) (2)
The following specifications apply for VDD = 12V, AV = 10, RL = 4Ω, f = 1kHz unless otherwise specified. Limits apply for TA =
25°C.
Symbol
Parameter
LM4940
Conditions
Typical (3)
Limit (4) (5)
Units
(Limits)
IDD
Quiescent Power Supply Current
VIN = 0V, IO = 0A, No Load
16
40
mA (max)
ISD
Shutdown Current
VSHUTDOWN = GND (6)
40
100
µA (max)
2.0
VDD/2
V (min)
V (max)
0.4
V (max)
VSDIH
Shutdown Voltage Input High
VSDIL
Shutdown Voltage Input Low
Single Channel
THD+N = 1%
3.1
THD+N = 10%
4.2
2.8
PO
Output Power
VDD = 14.4V, THD+N = 10%
6.0
THD+N
Total Harmomic Distortion + Noise
PO = 1WRMS, AV = 10, f = 1kHz
0.15
%
εOS
Output Noise
A-Weighted Filter, VIN = 0V,
Input Referred
10
µV
XTALK
Channel Separation
PO = 1W
70
dB
Power Supply Rejection Ratio
VRIPPLE = 200mVp-p
fRIPPLE = 1kHz
56
dB
PSRR
(1)
(2)
(3)
(4)
(5)
(6)
W (min)
All voltages are measured with respect to the GND pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Shutdown current is measured in a normal room environment. The Shutdown pin should be driven as close as possible to GND for
minimum shutdown current.
TYPICAL APPLICATION
Figure 2. Typical Stereo Audio Amplifier Application Circuit
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EXTERNAL COMPONENTS DESCRIPTION
Refer to Figure 1.
Components
Functional Description
1.
RIN
This is the inverting input resistance that, along with RF, sets the closed-loop gain. Input resistance RIN and input
capacitance CIN form a high pass filter.
The filter's cutoff frequency is fC = 1/(2πRINCIN).
2.
CIN
This is the input coupling capacitor. It blocks DC voltage at the amplifier's inverting input. CIN and RIN create a
highpass filter. The filter's cutoff frequency is fC = 1/(2πRINCIN). Refer to the SELECTING EXTERNAL
COMPONENTS section for an explanation of determining CIN's value.
3.
RF
This is the feedback resistance that, along with Ri, sets closed-loop gain.
4.
CS
The supply bypass capacitor. Refer to the POWER SUPPLY BYPASSING section for information about properly
placing, and selecting the value of, this capacitor.
5.
CBYPASS
This capacitor filters the half-supply voltage present on the BYPASS pin. Refer to the SELECTING EXTERNAL
COMPONENTS for information about properly placing, and selecting the value of, this capacitor.
6.
COUT
This is the output coupling capacitor. It blocks the nominal VDD/2 voltage present at the output and prevents it
from reaching the load. COUT and RL form a high pass filter whose cutoff frequency is fC = 1/(2πRLCOUT). Refer to
the SELECTING EXTERNAL COMPONENTS section for an explanation of determining COUT's value.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Frequency
THD+N vs Frequency
VDD = 12V, RL = 4Ω, SE operation,
both channels driven and loaded (average shown)
POUT = 1W, AV = 1
Figure 3.
VDD = 12V, RL = 4Ω, SE operation,
both channels driven and loaded (average shown),
POUT = 2.5W, AV = 1
Figure 4.
THD+N vs Frequency
THD+N vs Output Power
VDD = 12V, RL = 8Ω, SE operation,
both channels driven and loaded (average shown),
POUT = 1W, AV = 1
Figure 5.
VDD = 14.4V, RL = 4Ω, SE operation, AV = 1
single channel driven/single channel measured,
fIN = 1kHz
Figure 6.
THD+N vs Output Power
VDD = 12V, RL = 4Ω, SE operation, AV = 1
single channel driven/single channel measured,
fIN = 1kHz
Figure 7.
6
THD+N vs Output Power
VDD = 12V, RL = 8Ω, SE operation, AV = 1
single channel driven/single channel measured,
fIN = 1kHz
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
THD+N vs Output Power
VDD = 12V, RL = 16Ω, SE operation, AV = 1
single channel driven/single channel measured,
fIN = 1kHz
Figure 9.
VDD = 12V, RL = 4Ω, SE operation, AV = 10
single channel driven/single channel measured,
fIN = 1kHz
Figure 10.
THD+N vs Output Power
THD+N vs Output Power
VDD = 12V, RL = 8Ω, SE operation, AV = 10
single channel driven/single channel measured,
fIN = 1kHz
Figure 11.
VDD = 12V, RL = 16Ω, SE operation, AV = 10
single channel driven/single channel measured,
fIN = 1kHz
Figure 12.
Output Power vs Power Supply Voltage
RL = 4Ω, SE operation, fIN = 1kHz,
both channels driven and loaded (average shown),
at (from top to bottom at 12V): THD+N = 10%,
THD+N = 1%
Figure 13.
Output Power vs Power Supply Voltage
RL = 8Ω, SE operation, fIN = 1kHz,
both channels driven and loaded (average shown),
at (from top to bottom at 12V): THD+N = 10%,
THD+N = 1%
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Power Supply Voltage
RL = 16Ω, SE operation, fIN = 1kHz,
both channels driven and loaded (average shown),
at (from top to bottom at 12V): THD+N = 10%,
THD+N = 1%
Figure 15.
VDD = 12V, RL = 8Ω, SE operation,
VRIPPLE = 200mVp-p, at (from top to bottom at 60Hz):
CBYPASS = 1µF, CBYPASS = 4.7µF, CBYPASS = 10µF
Figure 16.
Power Supply Rejection vs Frequency
Output Power vs Load Resistance
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Total Power Dissipation vs Load Dissipation
VDD = 12V, SE operation, fIN = 1kHz,
at (from top to bottom at 1W):
RL = 4Ω, RL = 8Ω
Figure 18.
VDD = 12V, RL = 8Ω, SE operation, VRIPPLE = 200mVp-p,
AV = 10, at (from top to bottom at 60Hz):
CBYPASS = 1µF, CBYPASS = 4.7µF, CBYPASS = 10µF
Figure 17.
VDD = 12V, SE operation, fIN = 1kHz,
both channels driven and loaded,
at (from top to bottom at 15Ω):
THD+N = 10%, THD+N = 1%
Figure 19.
Power Supply Rejection vs Frequency
Channel-to-Channel Crosstalk vs Frequency
VDD = 12V, RL = 4Ω, POUT = 1W, SE operation,
at (from top to bottom at 1kHz): VINB driven,
VOUTA measured; VINA driven, VOUTB measured
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Channel-to-Channel Crosstalk vs Frequency
Power Supply Current vs Power Supply Voltage
RL = 4Ω, SE operation
VIN = 0V, RSOURCE = 50Ω
VDD = 12V, RL = 8Ω, POUT = 1W, SE operation,
at (from top to bottom at 1kHz): VINB driven,
VOUTA measured; VINA driven, VOUTB measured
Figure 21.
Figure 22.
Clipping Voltage vs Power Supply Voltage
RL = 4Ω, SE operation, fIN = 1kHz
both channels driven and loaded,
at (from top to bottom at 13V):
negative signal swing, positive signal swing
Figure 23.
Clipping Voltage vs Power Supply Voltage
RL = 8Ω, SE operation, fIN = 1kHz
both channels driven and loaded,
at (from top to bottom at 13V):
negative signal swing, positive signal swing
Figure 24.
Power Dissipation vs Ambient Temperature
VDD = 12V, RL = 8Ω (SE), fIN = 1kHz,
(from top to bottom at 120°C):
16in2 copper plane heatsink area,
8in2 copper plane heatsink area
Figure 25.
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APPLICATION INFORMATION
Figure 26. Typical LM4940 Stereo Amplifier Application Circuit
HIGH VOLTAGE BOOMER WITH INCREASED OUTPUT POWER
Unlike previous 5V Boomer amplifiers, the LM4940 is designed to operate over a power supply voltages range of
10V to 15V. Operating on a 12V power supply, the LM4940 will deliver 3.1W per channel into 4Ω loads with no
more than 1% THD+N.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended amplifier. Equation 1 states the
maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a
specified output load.
PDMAX-SE = (VDD) 2/ (2π2RL):
Single Ended
(1)
The LM4940's dissipation is twice the value given by Equation 1 when driving two SE loads. For a 12V supply
and two 8Ω SE loads, the LM4940's dissipation is 1.82W.
The maximum power dissipation point (twice the value given by Equation 1 must not exceed the power
dissipation given by Equation 2:
PDMAX' = (TJMAX - TA) / θJA
(2)
The LM4940's TJMAX = 150°C. In the KTW package, the LM4940's θJA is 20°C/W when the metal tab is soldered
to a copper plane of at least 16in2. This plane can be split between the top and bottom layers of a two-sided
PCB. Connect the two layers together under the tab with a 5x5 array of vias. For the NEC package, use an
external heatsink with a thermal impedance that is less than 20°C/W. At any given ambient temperature TA, use
Equation 3 to find the maximum internal power dissipation supported by the IC packaging. Rearranging
Equation 3 and substituting PDMAX for PDMAX' results in Equation 4. This equation gives the maximum ambient
temperature that still allows maximum stereo power dissipation without violating the LM4940's maximum junction
temperature.
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TA = TJMAX - PDMAX-SEθJA
(3)
For a typical application with a 12V power supply and two 4Ω SE loads, the maximum ambient temperature that
allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately
113°C for the KTW package.
TJMAX = PDMAX-SEθJA + TA
(4)
Equation 4 gives the maximum junction temperature TJMAX. If the result violates the LM4940's 150°C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further
allowance should be made for increased ambient temperatures.
The above examples assume that a device is operating around the maximum power dissipation point. Since
internal power dissipation is a function of output power, higher ambient temperatures are allowed as output
power or duty cycle decreases.
If the result of Equation 3 is greater than that of Equation 4, then decrease the supply voltage, increase the load
impedance, or reduce the ambient temperature. Further, ensure that speakers rated at a nominal 4Ω do not fall
below 3Ω. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be
created using additional copper area around the package, with connections to the ground pins, supply pin and
amplifier output pins. Refer to the TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation
information at lower output power levels.
POWER SUPPLY VOLTAGE LIMITS
Continuous proper operation is ensured by never exceeding the voltage applied to any pin, with respect to
ground, as listed in the Absolute Maximum Ratings section.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a voltage regulator typically use a 10µF in parallel with a 0.1µF filter
capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient
response. However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance
connected between the LM4940's supply pins and ground. Do not substitute a ceramic capacitor for the
tantalum. Doing so may cause oscillation. Keep the length of leads and traces that connect capacitors between
the LM4940's power supply pin and ground as short as possible. Connecting a 10µF capacitor, CBYPASS, between
the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR.
The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases
turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass capacitor
values, especially CBYPASS, depends on desired PSRR requirements, click and pop performance (as explained in
the section, SELECTING EXTERNAL COMPONENTS), system cost, and size constraints.
MICRO-POWER SHUTDOWN
The LM4940 features an active-low shutdown mode that disables the amplifier's bias circuitry, reducing the
supply current to 40μA (typ). Connect SHUTDOWN to a voltage between 2V to VDD/2 for normal operation.
Connect SHUTDOWN to GND to disable the device. A voltage that is greater than GND can increase shutdown
current.
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SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Two quantities determine the value of the input coupling capacitor: the lowest audio frequency that requires
amplification and desired output transient suppression.
As shown in Figure 26, the input resistor (RIN) and the input capacitor (CIN) produce a high pass filter cutoff
frequency that is found using Equation 5.
fC = 1/2πRiCi
(5)
As an example when using a speaker with a low frequency limit of 50Hz, Ci, using Equation 5 is 0.159µF. The
0.39µF CINA shown in Figure 26 allows the LM4940 to drive high efficiency, full range speaker whose response
extends below 30Hz.
Output Coupling Capacitor Value Selection
The capacitors COUTA and COUTB that block the VDD/2 output DC bias voltage and couple the output AC signal to
the amplifier loads also determine low frequency response. These capacitors, combined with their respective
loads create a highpass filter cutoff frequency. The frequency is also given by Equation 5.
Using the same conditions as above, with a 4Ω speaker, COUT is 820µF (nearest common valve).
Bypass Capacitor Value
Besides minimizing the input capacitor size, careful consideration should be paid to value of CBYPASS, the
capacitor connected to the BYPASS pin. Since CBYPASS determines how fast the LM4940 settles to quiescent
operation, its value is critical when minimizing turn-on pops. The slower the LM4940's outputs ramp to their
quiescent DC voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CBYPASS equal to 10µF along with
a small value of CIN (in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As
discussed above, choosing CIN no larger than necessary for the desired bandwidth helps minimize clicks and
pops.
OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE
The LM4940 contains circuitry that eliminates turn-on and shutdown transients ("clicks and pops"). For this
discussion, turn-on refers to either applying the power supply voltage or when the micro-power shutdown mode
is deactivated.
As the VDD/2 voltage present at the BYPASS pin ramps to its final value, the LM4940's internal amplifiers are
configured as unity gain buffers and are disconnected from the AMPA and AMPB pins. An internal current source
charges the capacitor connected between the BYPASS pin and GND in a controlled manner. Ideally, the input
and outputs track the voltage applied to the BYPASS pin. The gain of the internal amplifiers remains unity until
the voltage applied to the BYPASS pin.
The gain of the internal amplifiers remains unity until the voltage on the bypass pin reaches VDD/2. As soon as
the voltage on the bypass pin is stable, the device becomes fully operational and the amplifier outputs are
reconnected to their respective output pins. Although the BYPASS pin current cannot be modified, changing the
size of CBYPASS alters the device's turn-on time. Here are some typical turn-on times for various values of
CBYPASS:
12
CB (µF)
TON (ms)
1.0
120
2.2
120
4.7
200
10
440
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In order eliminate "clicks and pops", all capacitors must be discharged before turn-on. Rapidly switching VDD may
not allow the capacitors to fully discharge, which may cause "clicks and pops".
There is a relationship between the value of CIN and CBYPASS that ensures minimum output transient when power
is applied or the shutdown mode is deactivated. Best performance is achieved by setting the time constant
created by CIN and Ri + Rf to a value less than the turn-on time for a given value of CBYPASS as shown in the table
above.
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 3W into a 4Ω load
The following are the desired operational parameters:
Power Output
3WRMS
Load Impedance
4Ω
Input Level
0.3VRMS (max)
Input Impedance
20kΩ
Bandwidth
100Hz–20kHz ± 0.25dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Power Supply Voltage curve in the
TYPICAL PERFORMANCE CHARACTERISTICS section. Another way, using Equation 6, is to calculate the
peak output voltage necessary to achieve the desired output power for a given load impedance. To account for
the amplifier's dropout voltage, two additional voltages, based on the Clipping Dropout Voltage vs Power Supply
Voltage in the TYPICAL PERFORMANCE CHARACTERISTICS curves, must be added to the result obtained by
Equation 6. The result is Equation 7.
(6)
VDD = VOUTPEAK + VODTOP + VODBOT
(7)
The Figure 13 graph for an 8Ω load indicates a minimum supply voltage of 11.8V. The commonly used 12V
supply voltage easily meets this. The additional voltage creates the benefit of headroom, allowing the LM4940 to
produce an output power of 3W without clipping or other audible distortion. The choice of supply voltage must
also not create a situation that violates of maximum power dissipation as explained above in the POWER
DISSIPATION section. After satisfying the LM4940's power dissipation requirements, the minimum differential
gain needed to achieve 3W dissipation in a 4Ω BTL load is found using Equation 8.
(8)
Thus, a minimum gain of 11.6 allows the LM4940's to reach full output swing and maintain low noise and THD+N
performance. For this example, let AV = 12. The amplifier's overall BTL gain is set using the input (RINA) and
feedback (R) resistors of the first amplifier in the series BTL configuration. Additionaly, AV-BTL is twice the gain set
by the first amplifier's RIN and Rf. With the desired input impedance set at 20kΩ, the feedback resistor is found
using Equation 9.
Rf/ RIN = AV
(9)
The value of Rf is 240kΩ. The nominal output power is 3W.
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The last step in this design example is setting the amplifier's -3dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB-desired limit. The results are
an
fL = 100Hz / 5 = 20Hz
(10)
fL = 20kHz x 5 = 100kHz
(11)
and
As mentioned in the SELECTING EXTERNAL COMPONENTS section, RINA and CINA, as well as COUT and RL,
create a highpass filter that sets the amplifier's lower bandpass frequency limit. Find the coupling capacitor's
value using Equation 14.
CIN = 1 / 2πRINfL
(12)
The result is
1 / (2πx20kΩx20Hz) = 0.398µF = CIN
(13)
1 / (2π x 4Ω x 20Hz) = 1989µF = COUT
(14)
and
Use a 0.39µF capacitor for CIN and a 2000µF capacitor for COUT, the closest standard values.
The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AV,
determines the upper passband response limit. With AV = 12 and fH = 100kHz, the closed-loop gain bandwidth
product (GBWP) is 1.2mHz. This is less than the LM4940's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance restricting bandwidth
limitations.
RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT
Figure 27 through Figure 29 show the recommended two-layer PC board layout that is optimized for the DDPAKpackaged LM4940 and associated external components. This circuit board is designed for use with an external
12V supply and 4Ω (min) speakers.
This circuit board is easy to use. Apply 12V and ground to the board's VDD and GND pads, respectively. Connect
a speaker between the board's OUTA and OUTB outputs and their respective GND terminals.
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Demonstration Board Layout
Figure 27. Recommended KTW PCB Layout:
Top Silkscreen
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LM4940
SNAS219C – OCTOBER 2003 – REVISED MAY 2013
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Figure 28. Recommended KTW PCB Layout:
Top Layer
16
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LM4940
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SNAS219C – OCTOBER 2003 – REVISED MAY 2013
Figure 29. Recommended KTW PCB Layout:
Bottom Layer
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Product Folder Links: LM4940
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LM4940
SNAS219C – OCTOBER 2003 – REVISED MAY 2013
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REVISION HISTORY
Changes from Revision B (May 2013) to Revision C
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM4940TS/NOPB
ACTIVE
DDPAK/
TO-263
KTW
9
45
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 85
L4940TS
LM4940TSX/NOPB
ACTIVE
DDPAK/
TO-263
KTW
9
500
Pb-Free (RoHS
Exempt)
CU SN
Level-3-245C-168 HR
-40 to 85
L4940TS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM4940TSX/NOPB
Package Package Pins
Type Drawing
SPQ
DDPAK/
TO-263
500
KTW
9
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
14.85
5.0
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM4940TSX/NOPB
DDPAK/TO-263
KTW
9
500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
KTW0009A
TS9A (Rev B)
BOTTOM SIDE OF PACKAGE
www.ti.com
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