NEC UPA1724

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1724
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
★
PACKAGE DRAWING (Unit : mm)
DESCRIPTION
The µPA1724 is N-Channel MOS Field Effect
8
Transistor designed for power management
5
applications of notebook computers and so on.
1,2,3 ; Source
; Gate
4
5,6,7,8 ; Drain
FEATURES
• 2.5-V gate drive and low on-resistance
RDS(on)1 = 11.0 mΩ MAX. (VGS = 4.5 V, ID = 5.0 A)
1
• Low Ciss: Ciss = 1850 pF TYP.
0.05 MIN.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
4.4
5.37 MAX.
0.8
+0.10
–0.05
1.8 MAX.
RDS(on)3 = 15.0 mΩ MAX. (VGS = 2.5 V, ID = 5.0 A)
6.0 ±0.3
4
0.15
RDS(on)2 = 12.0 mΩ MAX. (VGS = 4.0 V, ID = 5.0 A)
1.44
★
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1724G
Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
20
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±12
V
Drain Current (DC)
ID(DC)
±10
A
ID(pulse)
±40
A
PT
2.0
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to +150
°C
Drain Current (pulse)
Note1
Total Power Dissipation (TA = 25°C)
Note2
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2
2. Mounted on ceramic substrate of 1200 mm x 2.2 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14048EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999, 2000
µ PA1724
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
Drain to Source On-state Resistance
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = 4.5 V, ID = 5.0 A
8.6
11.0
mΩ
RDS(on)2
VGS = 4.0 V, ID = 5.0 A
8.8
12.0
mΩ
RDS(on)3
VGS = 2.5 V, ID = 5.0 A
11.0
15.0
mΩ
VGS(off)
VDS = 10 V, ID = 1 mA
0.5
0.84
1.5
V
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 5.0 A
10.0
19
Drain Leakage Current
IDSS
VDS = 20 V, VGS = 0 V
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±12 V, VDS = 0 V
±10
µA
Input Capacitance
Ciss
VDS = 10 V
1850
pF
Output Capacitance
Coss
VGS = 0 V
610
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
320
pF
Turn-on Delay Time
td(on)
ID = 5.0 A
43
ns
VGS(on) = 4.5 V
170
ns
td(off)
VDD = 10 V
90
ns
tf
RG = 10 Ω
130
ns
Total Gate Charge
QG
ID = 10 A
18
nC
★
Gate to Source Charge
QGS
VDD = 16 V
3.2
nC
★
Gate to Drain Charge
QGD
VGS = 4.5 V
7.8
nC
VF(S-D)
IF = 10 A, VGS = 0 V
0.78
V
Reverse Recovery Time
trr
IF = 10 A, VGS = 0 V
45
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
40
nC
★
Gate to Source Cut-off Voltage
Rise Time
tr
Turn-off Delay Time
Fall Time
Body Diode Forward Voltage
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
RL
RG
RG = 10 Ω
PG.
VGS
VGS
Wave Form
0
PG.
VDD
ID
90 %
90 %
10 %
0 10 %
Wave Form
τ = 1µ s
Duty Cycle ≤ 1 %
tr
td(on)
ton
IG = 2 mA
RL
50 Ω
VDD
90 %
ID
τ
2
VGS(on)
10 %
ID
VGS
0
S
td(off)
tf
toff
Data Sheet G14048EJ1V0DS00
µ PA1724
★ TYPICAL CHARACTERISTICS (TA = 25 °C)
FORWARD TRANSFER CHARACTERISTICS
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
Pulsed
Pulsed
10
50
ID - Drain Current - A
ID - Drain Current - A
100
1
TA = 125˚C
75˚C
25˚C
-25˚C
0.1
0.01
0.001
40
VGS = 4.5 V
30
VGS = 2.5 V
20
VGS = 4.0 V
10
VDS = 10 V
1
0
2
0
0.0
3
25.0
20.0
15.0
VGS = 2.5 V
10.0
VGS = 4.5 V
5.0
0.0
− 50 − 25
ID = 5.0 A
0
25
50
100 125 150
75
Tch - Channel Temperature - ˚C
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
40
Pulsed
30
20
VGS = 2.5 V
10
VGS = 4.0 V
VGS = 4.5 V
0
0.1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
Pulsed
VGS(off) - Gate to Source Cut-off Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance - mΩ
VGS - Gate to Source Voltage - V
30.0
0.4
0.2
0.8
0.6
1.0
VDS - Drain to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
30
Pulsed
20
10
ID = 5.0 A
ID = 2.0 A
0
0
5
10
15
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
2
VDS = 10 V
ID = 1 mA
1.5
1
0.5
0
− 50
0
50
100
150
Tch - Channel Temperature - ˚C
ID - Drain Current - A
Data Sheet G14048EJ1V0DS00
3
µ PA1724
100
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
VDS =10 V
Pulsed
10
1 000
IF - Diode Forward Current - A
|yfs| - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
TA = -25˚C
TA = 25˚C
TA = 75˚C
TA = 125˚C
1
0.1
0.01
0.1
1
10
Pulsed
100
VGS = 4.0 V
VGS = 0 V
10
1
0.1
0.0
100
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD - Source to Drain Voltage - V
ID- Drain Current - A
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
Ciss, Coss, Crss - Capacitance - pF
10 000
VGS = 0 V
f = 1 MHz
Ciss
1 000
Coss
Crss
100
10
0.01
0.1
1
10
100
trr - Reverse Recovery Time - ns
1 000
di/dt = 100A/µs
VGS = 0 V
100
10
1
0.1
VDS - Drain to Source Voltage - V
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
12
30
ID = 10 A
10
25
VGS
20
15
10
100
4
2
5
VDS
0
10
0
20
30
40
QG - Gate Charge - nC
ID - Drain Current - A
4
6
10
0
1
8
VDD = 16 V
10 V
4V
Data Sheet G14048EJ1V0DS00
50
60
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
µ PA1724
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
2.8
100
80
60
40
20
0
20
40
60
80
2.0
1.6
1.2
0.8
0.4
0
100 120 140 160
Mounted on ceramic
substrate of
1200 mm 2 ×2.2 mm
2.4
TA - Ambient Temperature - ˚C
0
20
40
60
80
100 120 140 160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
PW
10
1
=
10
0
m
µs
s
ID(DC) = 10 A
10
m
s
10
0
Po
m
s
we
rD
iss
ipa
tio
1
n
Lim
ite
d
TA = 25 ˚C
0.1 Single Pulse
0.1
1
10
Remark
2
Mounted on ceramic substrate of 1200 mm x 2.2 mm
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1 000
rth(t) - Transient Thermal Resistance - ˚C/W
ID - Drain Current - A
ID(pulse) = 40 A
d
ite V)
Lim 4.5
n)
S(o S =
RD VG
(@
Rth(ch-A) = 62.5˚C/W
100
10
1
0.1
0.01
0.001
Mounted on ceramic
substrate of 1200 mm2× 2.2 mm
Single Pulse
10 µ
100 µ
1m
10 m
100 m
1
10
100
1 000
PW - Pulse Width - s
Data Sheet G14048EJ1V0DS00
5
µ PA1724
[MEMO]
6
Data Sheet G14048EJ1V0DS00
µ PA1724
[MEMO]
Data Sheet G14048EJ1V0DS00
7
µ PA1724
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8