SLUS242B – JANUARY 1999 – REVISED JUNE 2001
D 1-V Input Voltage Operation Start-up
D
D
D
D
D
D
D
D OR N PACKAGE
(TOP VIEW)
Ensured Under Full Load on Main Output
With Operation Down to 0.4 V
Input Voltage Range of 1 V to VOUT + 0.5 V
500-mW Output Power at Battery Voltages
as Low as 0.8 V
Secondary 9-V Supply From a Single
Inductor
Adjustable Output Power Limit Control
Output Fully Disconnected in Shutdown
Adaptive Current-Mode Control for
Optimum Efficiency
8-µA Shutdown Supply Current
VOUT
VGD
VIN
SD
1
8
2
7
3
6
4
5
SW
PGND
SGND
PLIM
UCC3941–ADJ ONLY
(TOP VIEW)
VOUT
VGD
VIN
SD
1
8
2
7
3
6
4
5
SW
PGND
FB
PLIM
description
The UCC3941 family of low-input-voltage single-inductor boost-converters are optimized to operate from a
single- or dual-alkaline cell, and step up to a 3.3-V, 5-V, or an adjustable output at 500 mW. The UCC3941 family
also provides an auxiliary 9-V, 100-mW output, primarily for the gate drive supply, which can be used for
applications requiring an auxiliary output such as a 5-V supply by linear regulating. The primary output starts
up under full load at input voltages typically as low as 0.8 V, with a guaranteed maximum of 1 V, and operates
down to 0.4 V once the converter is operating, maximizing battery utilization.
Demanding applications such as pagers and personal digital assistants require high efficiency from several
milliwatts to several hundred milliwatts, and the UCC3941 family accommodates these applications with > 80%
typical efficiencies over the wide range of operation. The high-efficiency at low-output current is achieved by
optimizing switching and conduction losses along with low-quiescent current. At higher output current the
0.25-Ω charge switch, and the 0.4-Ω synchronous rectifier, along with continuous-mode conduction, provide
high efficiency. The wide input-voltage range on the UCC3941 family can accommodate other power sources
such as NiCd and NiMH.
Other features include maximum power control and shutdown control. The device is available in 8-pin SOIC (D)
and 8-pin DIP (N).
AVAILABLE OPTIONS
PACKAGED DEVICES
SOIC (D)†
TA
DIP (N)
VOUT (V)
Adjustable
3.3
(1.3 V to 6 V)
3.3
5.0
–40_C to 85_C
UCC2941D–3
UCC2941D–5
UCC2941D–ADJ
0_C to 70_C
UCC3941D–3
UCC3941D–5
UCC3941D–ADJ
5.0
Adjustable
(1.3 V to 6 V)
UCC2941N–3
UCC2941N–5
UCC2941N–ADJ
UCC3941N–3
UCC3941N–5
UCC3941N–ADJ
† The SOIC (D) package is available left end taped and reeled. Add an R suffix to the device type (e.g., UCC2941DR–3) to order
quantities of 2500 devices per reel.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(! ,'&$% & !" $ %)(&&#$ % )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- ! ,'&$ )! &(%%2 , (% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
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1
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
functional block diagram
10 µF
VIN
UCC3941–3 = 3.3 V
UCC3941–5 = 5.0 V
UCC3941–ADJ = 1.30 V TO 6 V
VOUT
8
8.5 V
VGD
10 µF
0.8 V TO VOUT+0.5 V
SW
3
2
+
22 µH
0.4 Ω
STARTUP
CIRCUITRY
1
0.25 Ω
100 µF
S SYNCHRONOUS RECTIFICATION CIRCUITRY
S ANTI–CROSS CONDUCTION STARTUP
S MULTIPLEXING LOGIC
S MAXIMUM INPUT POWER CONTROL
S ADAPTIVE CURRENT CONTROL
PLIM
5
SD
4
UCC3941–ADJ
OPEN = SD
+
{SGND/FB
6
1.25 V
FOR UCC3941–ADJ ONLY
MODULATOR CONTROL CIRCUIT
PGND
7
UDG–98147
† For UCC3941–ADJ only: Pin 7 = SGND & PGND, Pin 6 = output sense feedback, FB
2
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
Terminal Functions
TERMINAL
NO.
UCC2941–3
UCC2941–5
UCC3941–3
UCC3941–5
UCC2941–ADJ
UCC3941–ADJ
FB
–
6
I
Feedback control pin used in the UCC3941–ADJ version only. The internal
reference for this comparator is 1.25V and external resistors provide the gain to
the output voltage.
PGND
7
7
–
Power ground of the IC. The inductor charging current flows through this pin. For
the UCC3941–ADJ signal ground and power ground lines are tied to a common
pin.
PLIM
5
5
I
Peak current limit
SGND
6
–
–
Signal ground of the IC. For the UCC3941–ADJ signal ground and power ground
lines are tied to a common pin
SD
4
4
I
Shutdown pin
SW
8
8
I
Inductor connection
VGD
2
2
O
Gate drive supply
VIN
3
3
I
Input voltage to supply the IC during startup. After the output is running the IC
draws power from VOUT or VGD
VOUT
1
1
O
Main output voltage
NAME
I/O
DESCRIPTION
detailed description
peak limit (PLIM)
The PLIM pin is programmed to set the maximum input power for the converter. For example a 1-A current limit
at 1 V would have a 333-mA limit at 3 V input keeping the input power constant at 1 W. The peak current at
VIN = 1 V is programmed to 1.5 A (1.5 W) when this pin is grounded. The power limit is given by:
PL
W
+
ǒ
Ǔ
ǒ
11.8 n ) V
IN
R ) 6.7
PL
0.26
Ǔ
(1)
where RPL is equal to the external resistor from the PLIM pin to ground and n is the expected efficiency of the
converter. The peak current limit is given by:
I
PK(A)
11.8
+
V
IN
n
ǒRPL ) 6.7Ǔ
) 0.26
(2)
Constant power gives several advantages over constant current such as lower output ripple.
shutdown (SD)
When the SD pin is open, the built-in 7-µA current source pulls up on the pin and programs the IC to go into
shutdown mode. This pin requires an open circuit for shutdown and does not operate correctly when driven to
a logic level high with TTL or CMOS logic. When this pin is connected to ground, (either directly or with a
transistor) the IC is enabled and both output voltages regulate.
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3
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
detailed description (continued)
needs a name (SW)
The SW pin inductor is connected between this node and VIN. The VGD (gate drive supply) flyback diode is
also connected to this pin. When servicing the 3.3-V supply, this pin goes low charging the inductor, then shut
off, dumping the energy through the synchronous rectifier to the output. When servicing the VGD supply, the
internal synchronous rectifier stays off, and the energy is diverted to VGD through the flyback diode. During
discontinuous portions of the inductor current a MOSFET resistively connects VIN to SW damping excess
circulating energy to eliminate undesired high frequency ringing.
gate drive supply (VGD)
The VGD pin is coarsely regulated around 9 V, and is primarily used for the gate drive supply for the power
switches in the IC. This pin can be loaded with up to 10 mA as long as it does not present a load at voltages
below 2 V. This ensures proper startup of the IC. The VGD supply can go as low as 7.5 V without interfering
with the servicing of the 3.3-V output. Below 7.5 V, VGD has the highest priority, although in practice the voltage
should not decay to that level if the output capacitor is sized properly.
output voltage (VOUT)
Main output voltage (3.3 V, 5 V, or adjustable) which has highest priority in the multiplexing scheme, as long
as VGD is above the critical level of 7.5 V. Loads over 150 mA are achievable at an input voltage of 1-V. This
output starts up with 1-V input at full load.
absolute maximum ratings over operating free–air temperature range (unless otherwise noted)†
Input voltage VIN, PLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 10 V
Voltage range, VGD, SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Voltage range, SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VIN
Output voltage range, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 10 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300_C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDM 1 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. Currents are positive into, negative
out of the specified terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25_C
POWER RATING
DERATING FACTOR
ABOVE TA = 25_C
TA = 85_C
POWER RATING
D
760 mW
6.1 mW/_C
390 mW
N
980 mW
7.9 mW/_C
510 mW
recommended operating conditions
4
MIN
MAX
Input voltage
0.8
5.0
Output voltage
1.8
5.5
V
Output current
0
200
mA
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UNIT
V
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
electrical characteristics over recommended operating junction temperature range, for UCC3941,
TA = 0_C to 70_C, for UCC2941, TA = –40_C to 85_C, VIN = 1.25 V, TA = TJ (unless otherwise noted)
input voltage
PARAMETER
TEST CONDITIONS
TJ = 25_C,
IOUT = 100 mA,
Minumum startup voltage
Minumum dropout voltage
MIN
TYP
MAX
UNIT
No external VGD load,
See Note 1
0.8
1.0
V
TJ = 0_C to 85_C, No external VGD load,
IOUT = 100 mA, See Note 1
0.9
1.1
V
TJ = –40_C to 0_C, No external VGD load,
IOUT = 100 mA, See Note 1
0.9
1.5
V
0.5
V
VOUT
+ 0.5
V
IOUT = 0 mA,
VGD = 6.3 V
No external VGD load,
Input voltage range
1
Quiescent supply current
See note 2
13
25
µA
Shutdown supply current
SD = open
8
20
µA
output voltage
PARAMETER
TEST CONDITIONS
Quiescent supply current
See note 2
Shutdown supply current
SD = open
Regulation voltage
Feedback voltage
TYP
MAX
32
1 V < VIN < 3 V
UCC3941–3
MIN
1 V < VIN < 3 V,
See Note 1
0 mA < IOUT < 150 mA,
1 V < VIN < 5 V
UCC3941–5
1 V < VIN < 5 V,
See Note 1
UCC3941–ADJ
1 V < VIN < 3 V
0 mA < IOUT < 100 mA,
UNIT
80
µA
6
15
µA
3.18
3.25
3.37
V
3.17
3.30
3.43
V
4.85
5.00
5.15
V
4.8
5.0
5.2
V
1.212
1.250
1.288
V
MIN
TYP
MAX
VGD output
PARAMETER
TEST CONDITIONS
Quiescent supply current
See note 2
Shutdown supply current
SD = open
25
1 V < VIN < 3 V
Regulation voltage
1 V < VIN < 3 V,
See Note 1
0 mA < IOUT < 10 mA,
UNIT
60
µA
8
20
µA
7.5
8.7
9.2
V
7.4
87
9.3
V
NOTE 1: Performance from application circuit shown in Figures 3, 4, and 5. Ensured by design. Not 100% production tested.
NOTE 2: For the UCC3941–3, VOUT = 3.47 V and VGD = 9.3 V. For the UCC3941–5, VOUT = 5.25 V, VGD = 9.3 V. For the UCC3941–ADJ,
FB = 1.315 V, VGD = 9.3 V.
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5
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
electrical characteristics over recommended operating junction temperature range, for UCC3941,
TA = 0_C to 70_C, for UCC2941, TA = –40_C to 85_C, VIN = 1.25 V, TA = TJ (unless otherwise noted)
(continued)
inductor charging (L = 22 µH)
PARAMETER
TEST CONDITIONS
Peak discontinuous current
Over operating range
Peak continuous current
RPLIM = 6.2 Ω,
Charge switch RDS(on)
N and D package, I = 200 mA
Current limit delay
See Note 1
See Note 1
MIN
0.5
TYP
MAX
UNIT
0.05
0.85
A
0.9
1.3
A
0.25
0.40
50
Ω
ns
synchronous rectifier
PARAMETER
Rectifier RDS(on)
TEST CONDITIONS
UCC3941N–ADJ
UCC3941D–ADJ
I = 200 mA,
UCC3941N–3
UCC3941D–3
UCC3941N–5
UCC3941D–5
MIN
TYP
MAX
UNIT
0.35
0.6
Ω
I = 200 mA
0.35
0.6
Ω
I = 200 mA
0.5
0.8
Ω
VOUT = 3.3 V
shutdown
PARAMETER
Shutdown bias current
TEST CONDITIONS
SD = 0 V
MIN
–10
TYP
–7
MAX
UNIT
µA
NOTE 1: Performance from application circuit shown in Figures 3, 4, and 5. Ensured by design. Not 100% production tested.
NOTE 2: For the UCC3941–3, VOUT = 3.47 V and VGD = 9.3 V. For the UCC3941–5, VOUT = 5.25 V, VGD = 9.3 V. For the UCC3941–ADJ,
FB = 1.315 V, VGD = 9.3 V.
6
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
A detailed block diagram of the UCC3941 is shown in Figure 1. Unique control circuitry provides high-efficiency
power conversion for both light and heavy loads by transitioning between discontinuous and continuous
conduction based on load conditions. Figure 2 depicts converter waveforms for the application circuit shown
in Figure 3. A single 22-µH inductor provides the energy pulses required for a highly efficient 3.3-V converter
at up to 500 mW output power.
VIN
SW
3
8
ANTI–RINGING
SWITCH
1
VGD
VGD
VGD ZERO
DETECT
200 kHz
STARTUP
OSCILLATOR
AND CONTROL
2
VGD
VOUT
VOUT ZERO
DETECT
+
+
1.7 µS
OFF TIME
CONTROLLER
+
5V
VGD
FROM
SD
RECTIFIER
CONTROL
FROM SD
1.1 A
5 Ω MAX
PLIM
5
CLK
CURRENT
LIMIT
D
Q
L1
+
50 mV
MAXIMUM
R
VSAT
SD
SD
4
50 mV
VIN
VIN
ON TIME
CONTROLLER
11 µSEC
T ON =
VIN
Q
SD
BOOST
LATCH
6
Q
+
*
+
**
+
***
FB
(UCC3941–ADJ
ONLY)
R
VGD
SD
6
THERMAL
SHUTDOWN
SGND
(UCC3941–3/–5
ONLY)
VGD
* 3.3 V FOR UCC3941–3
5.0 V FOR UCC3941–5
1.25 V FOR UCC3941–ADJ
** 8.7 V FOR UCC3941–3
9.6 V FOR UCC3941–5/–ADJ
7
PGND
*** 7.7 V FOR UCC3941–3
8.8 V FOR UCC3941–5/–ADJ
UDG–98146
NOTE: Switches are shown in the logic low state; external RPLIM = 6.2 Ω
Figure 1. 1–V Synchronous Boost
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7
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
UDG–96117
Figure 2. Inductor Current and Output Ripple Waveforms
At time t1, the 3.3-V output drops below its lower threshold, and the inductor is charged with an on time
determined by:
t
ON
+
12 ms
VIN
(3)
For a 1.25-V input, and a 22-µH inductor, the resulting peak current is approximately 500 mA. At time t2, the
inductor begins to discharge with a minimum off time of 1.7 µs. Under lightly loaded conditions, the amount of
energy delivered in this single pulse satisfies the voltage-control loop, and the converter does not command
any more energy pulses until the output again drops below the lower voltage threshold.
At time t3, the VGD supply has dropped below its lower threshold, but the output voltage is still above its
threshold point. This results in an energy pulse to the gate drive supply at t4. However, while the gate drive is
being serviced, the output voltage has dropped below its lower threshold, so the state machine commands an
energy pulse to the output as soon as the gate drive pulse is completed.
Time t6, represents a transition between light and heavy load. A single energy pulse is not sufficient to force
the output voltage above its upper threshold before the minimum off-time has expired, and a second charge
cycle is commanded. Since the inductor current does not reach zero in this case, the peak current is greater
than 0.5 A at the end of the next charge on time. This results in a ratcheting of the inductor current until either
the output voltage is satisfied, or the converter reaches its programmed current limit. At time t7, the gate drive
voltage has dropped below its threshold but the converter continues to service the output because it has highest
priority, unless VGD drops below 7.5 V.
Between t7 and t8, the converter reaches its peak current limit which is determined by RPL and VIN. Once the
limit is reached, the converter operates in continuous mode with approximately 200 mA of ripple current. At time
t8, the output voltage is satisfied, and the converter can service VGD, which occurs at t9.
8
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
programming the power limit
The UCC3941 incorporates an adaptive power limit control that modifies the converter current limit as a function
of input voltage. In order to program the function, the user simply determines the output power requirements
and makes an initial converter efficiency estimate. The programming resistor is chosen by:
R
PL
+
P
OUT
11.8
n
* 0.26
n
ǒ
V
Ǔ
BAT
* 6.7
(4)
Where n is the initial efficiency estimate. For 500 mW of output power, with a 1.0 V input, and an efficiency
estimate of 0.75:
R
PL
+
11.8
0.5 * (0.26
0.75
0.75
1.0)
* 6.7 + 22 W
(5)
For decreasing values of RPL, the power limit increases. Therefore, to ensure that the converter can supply
500 mW of output power, a power limiting resistor of less than 22 Ω must be chosen.
P +V
L
BAT
ǒ
Ǔ
11.8
) (1.0
I +
L
22 ) 6.7
0.26) + 0.67 W
MMSZ5240BT1
10 V
10 µ F
DT3316P–223
22 µ H
3
8
VIN
SW
(6)
1 V TO 3.5 V
+
3.3 V AT 500 mW
8.5 V
2
VOUT
VGD
10 µ F
1
10SN100M
100 µ F
UCC3941–3
PLIM
5
R PL 6.2 Ω
4
OPEN = SD
SD
SGND
6
PGND
7
WCR0805–6R207
UDG–98163
Figure 3. Dual Output Synchronous Boost, 3.3-V Version
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9
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
programming the power limit (continued)
DT3316P–223
22 µH
MMSZ5240BT1
10 V
10 µF
8.5 V
2
3
8
VIN
SW
VGD
+ 1 V TO 5.5 V
5.0 V AT 500 mW
1
VOUT
10SN100M
100 µF
10 µF
UCC3941–5
5
PLIM
4
RPL 6.2 Ω
WCR0805–6R207
SD
OPEN = SD
SGND
6
PGND
7
UDG–98159
Figure 4. Dual Output Synchronous Boost, 5-V Version
MMSZ5240BT1
10 V
10 µF
2
8.5 V
10 µF
3
8
VIN
SW
VGD
VOUT
DT3316P–223
22 µH
VOUT + 1.25
SD
10SN100M
100 µF
FB
6
PLIM
5
R1
VREF = 1.25 V
RPL 6.2 Ω
WCR0805–6R207
OPEN = SD
(SGND)
PGND
ǒ1 ) R1
Ǔ AT 500 mA
R2
1
UCC3941–ADJ
4
+ 1 V TO VOUT + 0.5 V
R2
7
UDG–98164
Figure 5. Dual Output Synchronous Boost, Adjustable Version
10
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
programming the power limit (continued)
This power limiting setting supports 0.5 W of output power. It should be noted that the power limit equation
contains an approximation which results in slightly less actual input power than the equation predicts. This
discrepancy results from the fact that the average current delivered to the load is less than the peak current set
by the power limit function due to current ripple. However, if the ripple component of the current is kept low, the
power limit equation can be used as an adequate estimate of input power. Furthermore, since an initial efficiency
estimate was required, sufficient margin can be built into this estimate to ensure proper converter operation.
The 6.2-Ω external power limit resistor (shown in Figures 3, 4, and 5) results in approximately 700 mW of power
capability with a 1.0-V input.
inductor selection
An inductor value of 22 µH works well in most applications, but values between 10 µH and 100 µH are also
acceptable. Lower-value inductors typically offer lower ESR and smaller physical size. Due to the nature of the
bang–bang controllers, larger inductor values typically results in larger overall voltage ripple, because once the
output voltage level is satisfied the converter goes discontinuous, resulting in the residual energy of inductor
causing overshoot.
It is recommended to keep the ESR of the inductor below 0.15 Ω for 500-mW applications. A Coilcraft
DT3316P–223 surface mount inductor is one choice since it has a current rating of 1.5 A and an ESR of 84 mΩ.
Other choices for surface mount inductors are shown in Table 1.
Table 1. Inductor Suppliers
MANUFACTURER
CONTACT INFORMATION
PART NUMBERS
Coilcraft
Cary, Illinois
Tel: (708) 639–2361 Fax: (708) 639–1469
DT Series
Coiltronics
Boca Raton, Florida
Tel: (407) 241–7878
CTX Series
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11
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
output capacitor selection
Once the inductor value is selected, the capacitor value determines the ripple of the converter. The worst case
peak-to-peak ripple of a cycle is determined by two components, one is due to the charge storage characteristic,
and the other is the ESR of the capacitor. The worst-case ripple occurs when the inductor is operating at
maximum current and is expressed as follows:
2
DV +
2
ǒICLǓ L
) ǒI
CL
C ǒV * V Ǔ
I
O
C
Ǔ
ESR
(7)
where
ǒ
Ǔ
D ICL = the peak inductor current I CL + Power Limit
V
D
D
D
D
IN
∆V = output ripple
VO = output voltage
VI = input voltage
CESR = ESR of the output capacitor
A Sanyo OS–CON series surface mount capacitor (10SN100M) is one recommendation. This part has an ESR
rating of 90 µW at 100 µF. Other potential capacitor sources are shown in Table 2.
Table 2. Capacitor Suppliers
MANUFACTURER
CONTACT INFORMATION
PART NUMBERS
Sanyo Video Components
San Diego, California
Tel: (619) 661–6322
Fax: (619) 661–1055
OS–CON Series
AVX
Sanford, Maine
Tel: (207) 282–5111
Fax: (207) 283–1941
TPS Series
Sprague
Concord, New Hampshire
Tel: (603) 224–1961
695D Series
input capacitor selection
Since the UCC3941 family does not require a large decoupling capacitor on the input voltage to operate
properly, a 10-µF capacitor is sufficient for most applications. Optimum efficiency occurs when the capacitor
value is large enough to decouple the source impedance. This usually occurs for capacitor values in excess
of 100 µF.
12
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
system shutdown
The UCC3941 is enabled by shorting the SD pin to ground either directly or through a transistor.The UCC3941
is shut down when the SD pin is floated (an internal current source pulls up on the SD pin). Since the SD pin
is not TTL compatible, 0 V enables the part but 3 V or even 5 V does not properly shut down the device.
The recommended circuit for a system requiring shutdown control is shown below. The enable line is driven from
a microprocessor or system logic. If enable is low, the SD pin is floated since Q1 base voltage is too low to turn
on. If enable is high, Q1 turns on and SD is grounded, enabling the UCC3941. A 1-MΩ resistor to VGD allows
Q1 to turn on if the enable pin is high impedance during startup. If shutdown control is not required for the
application, SD should be grounded directly.
CAUTION:
The UCC3941 should be allowed sufficient time to properly shutdown in a controlled
manner. This is accomplished by ensuring that enable is held low at least 500 µs before
subsequently being brought high. Not adhering to the timings in Figure 7 can result in
DEVICE FAILURE.
VSD – Shutdown Voltage – V
PROPOGATION DELAY AND RISE TIME
SHUTDOWN INTERFACE CIRCUIT
10
8
6
VGD
Ensure 500 µs
4
2
2
1 MΩ
20 kΩ
0
SD
Enable Voltage – V
ENABLE
4
~
~
6
4
2
0
0
Figure 6
~
~
500
t – Time – µs
1000
Figure 7. SD Timings
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13
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
SD interface circuit
reducing inrush current
A switch mode boost converter requires VIN to be less than VOUT in order to control current in the inductor.
Forward voltage is applied across the inductor during the tON time (increasing current) while reverse voltage
is applied during the tOFF time (decreasing current). During startup, VOUT is less than VIN, resulting in inrush
current until the output is charged.
The UCC3941 has two outputs; VGD and VOUT. Inrush current in a two cell alkaline application is typically higher
than with a single cell and should be minimized to reduce peak currents in the controller. The VGD inrush current
can be minimized by reducing the value of the VGD capacitor. For example a 10-µF capacitor may cause a 3-A
inrush where a 1-µF capacitor results in less than 1-A of inrush. Reducing the VOUT inrush current is more
difficult since the output capacitance may need to be large to minimize output ripple. In a two cell application,
a diode from VIN to VOUT (shown In Figure 8) precharges the VOUT capacitor and reduces inrush.
PRECHARGE DIODE
3
22 µH
VIN
8
+
2 CELL
INPUT
220 µF
SW
VOUT
1
10 V
ZENER
100 µF
2
VGD
1 µF
UDG–00155
Figure 8. Optional Precharge Diode for VOUT for 2-Cell Input
avoiding inductor saturation
Inductor selection should take into account size, on resistance, and the current capabilities of the part. Inductor
ratings include both saturation current and maximum operating current for the device. The RPLIM resistor and
inductor should be selected to guarantee the inductor does not saturate during normal operation. A saturated
inductor can cause excessive peak currents and δi/δt slopes which may result in part failure. Inrush and normal
operating current should be viewed with a current probe and oscilloscope to ensure the inductor current is linear
and controlled.
14
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
TYPICAL CHARACTERISTICS
EFFICIENCY
vs.
OUTPUT CURRENT
EFFICIENCY
vs.
OUTPUT CURRENT
100
100
VIN = 1.5 V
VIN = 2 V
80
Efficiency – %
Efficiency – %
80
VIN = 1.25 V
60
VIN = 1 V
40
60
VIN = 3 V
VIN = 2.5 V
40
20
20
VOUT = 3.3 V
VOUT = 3.3 V
0
0
0.1
1 – Output Current
10 – mA
IOUT
0.1
100
Figure 9
1
10
IOUT – Output Current – mA
100
Figure 10
STARTUP CHARACTERISTICS
PSUEDO CONTINUOUS MODE OPERATION
L = 22 µH
C = 100 µF
CVGD = 22 µH
RPL = 6Ω
VIN = 1.25 V
IOUT = 100 mA
VOUT
1 V/div
3.3 V
VOUT
VOUT
RIPPLE
20 mV/div
VGD
5 V/div
IL
0.5 A/div
IL
0.2 A/div
t0
t1
t2 t3 t4
20 µs/div
2 ms/ div
Figure 11
Figure 12
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15
SLUS242B – JANUARY 1999 – REVISED JUNE 2001
startup characteristics timing sequence (for single output mode)
(see Figure 11)
D
D
D
D
D
t0
the 200-kHz srartup oscillator starts VGD rising
t1
VGD reaches sufficient voltage (5 V) to run in normal operating mode
t2
VGD reaches sufficient voltage (7.5 V) to start VOUT
t3
VOUT is serviced and starts up
t4
VOUT reaches sufficient voltage and VGD is serviced until it reaches 8.5 V
VGD LOAD = 10 mA
VOUT LOAD = 50 mA
VOUT
AC COUPLED
50 mV/DIV
VGD
AC COUPLED
100 mV/DIV
INDUCTOR
CURRENT
200 mA/DIV
t1
t2
t3 t4
t5
Figure 13.
startup characteristics timing sequence (for dual output mode)
(see Figure 13)
16
D t1
D t2
D t3
VOUT is serviced and inductor current goes continuous
D t4
D t5
VOUT is satisfied and VGD is serviced until the second threshold (8.7 V) is reached
VGD is serviced with discontinuous operation and reaches its first threshold (7.5 V)
VOUT requires servicing and because VGD has reached its minimum threshold of 7.5 V, VOUT
takes priority
Both outputs are satisfied
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SLUS242B – JANUARY 1999 – REVISED JUNE 2001
TYPICAL CHARACTERISTICS
UCC3941–3 DROPOUT VOLTAGE
vs.
OUTPUT CURRENT
MINIMUM STARTUP VOLTAGE
vs.
OUTPUT CURRENT
1.2
1.20
1.16
1.12
VIN – Startup Voltage – V
VIN – Dropout Voltage – V
1.0
0.8
0.6
0.4
1.08
1.04
1.00
0.96
0.92
0.88
0.2
0.84
0
0.80
0
50
100
IOUT – Output Current – mA
150
0
50
100
IOUT – Output Current – mA
Figure 14
150
Figure 15
UCC3941–ADJ (N and D PACKAGES) CURRENT LIMIT
vs.
PROGRAMMING RESISTANCE
STARTUP VOLTAGE
vs.
TEMPERATURE
2.1
1.2
1.9
VIN = 1 V
1.0
VIN = 1.25 V
1.5
VIN – Startup Voltage – V
IL – Current Limit – A
1.7
VIN = 1.5 V
1.3
VIN = 1.75 V
1.1
VIN = 2 V
0.9
VIN = 3 V
0.7
0.5
0.3
0
IL
(Rp)
+
2
6
8
10 12 14 16 18
RP – Programming Resistance – Ω
11.5
) 0.26
ǒǒ6.7 ) RPǓ
4
V
20
0.8
0.6
0.4
0.2
0
–40
–20
0
20
40
60
80
100
Temperature – _C
Ǔ
BAT
Figure 17
Figure 16
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17
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