8-Channel CMOS Logic to High Voltage Level Translator ADG3123 FEATURES FUNCTIONAL BLOCK DIAGRAM VDDA 2.3 V to 5.5 V input voltage range Output voltage levels (VDDA and VDDB to VSS ≤ 35 V) Low output voltage levels: down to −24.4 V High output voltage levels: up to +35 V Rise/fall time: 12 ns/19.5 ns typical Propagation delay: 80 ns typical Operating frequency: 100 kHz typical Ultralow quiescent current: 65 μA typical 20-lead, Pb-free, TSSOP package A1 A2 A3 A4 A5 A6 ADG3123 6 CHANNELS Y1 Y2 Y3 Y4 Y5 Y6 GND VSS APPLICATIONS A8 2 CHANNELS Y7 Y8 VDDB 05655-001 A7 Low voltage to high voltage translation TFT-LCD panels Piezoelectric motor drivers Figure 1. GENERAL DESCRIPTION The ADG3123 is an 8-channel, noninverting CMOS to high voltage level translator. Fabricated on an enhanced LC2MOS process, the device is capable of operating at high supply voltages while maintaining ultralow power consumption. The ADG3123 is guaranteed to operate over the −40°C to +85°C temperature range and is available in a compact, 20-lead TSSOP, Pb-free package. The internal architecture of the device ensures compatibility with logic circuits running from supply voltages within the 2.3 V to 5.5 V range. The voltages applied to Pin VDDA, Pin VDDB, and Pin VSS set the logic levels available at the outputs on the Y side of the device. Pin VDDA and Pin VDDB set the high output level for Pin Y1 to Pin Y6 and for Pin Y7 to Pin Y8, respectively. The VSS pin sets the low output level for all channels. The ADG3123 can provide output voltages levels down to −10 V for a low input level and up to +30 V for a high input logic level. For proper operation, VDDB must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. PRODUCT HIGHLIGHTS 1. Compatible with a wide range of CMOS logic levels. 2. High output voltage levels. 3. Fast rise and fall times coupled with low propagation delay. 4. Ultralow power consumption. 5. Compact, 20-lead TSSOP, Pb-free package. The low output impedance of the channels guarantees fast rise and fall times even for significant capacitive loads. This feature, combined with low propagation delay and low power consumption, makes the ADG3123 an ideal driver for TFT-LCD panel applications. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADG3123 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications....................................................................................... 1 Terminology .......................................................................................9 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 10 General Description ......................................................................... 1 Input Driving Requirements..................................................... 10 Product Highlights ........................................................................... 1 Output Load Requirements ...................................................... 10 Revision History ............................................................................... 2 Power Supplies ............................................................................ 10 Specifications..................................................................................... 3 Applications..................................................................................... 11 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 12 ESD Caution.................................................................................. 4 Ordering Guide .......................................................................... 12 Pin Configuration and Function Descriptions............................. 5 REVISION HISTORY 5/06—Rev. 0 to Rev. A Changes to Features, General Description, and Product Highlights ........................................................................... 1 Changes to Specifications ................................................................ 3 Changes to Figure 4 through Figure 9 ........................................... 6 Changes to Figure 14 and Figure 15............................................... 7 Changes to Theory of Operations section and Power Supplies section................................................................... 10 9/05—Revision 0: Initial Version Rev. A | Page 2 of 12 ADG3123 SPECIFICATIONS VDDA = VDDB = 27 V, VSS = −7 V, GND = 0 V, unless otherwise noted. 1 Table 1. Parameter DIGITAL INPUTS (Pin A1 to Pin A8) Input High Voltage Input Low Voltage Leakage Current Capacitance 3 ANALOG INPUTS (Pin VDDA) Input Voltage Range DIGITAL OUTPUTS (Pin Y1 to Pin Y8) Output High Voltage (Pin Y1 to Pin Y6) Output High Voltage (Pin Y7 to Pin Y8) Output Low Voltage Output Impedance SWITCHING CHARACTERISTICS3 Propagation Delay Low to High Transition High to Low Transition Rise Time Fall Time Maximum Operating Frequency POWER REQUIREMENTS Quiescent Power Supply Current Symbol Min VIH VIL IIL CI 1.7 VDDA 0 Typ 2 ±0.03 1 VOH VOH VOL R0 Unit 0.8 ±1 V V μA pF VDDB V VDDA − 1 VDDB − 1 VSS + 1 30 tPLH tPHL tR tF F0 50 IDDA IDDB ISS Power Supply Voltages VDDB to VSS VDDB to GND VSS to GND Max 76 80 12 19.5 100 125 125 20 32 0.03 65 0.03 1 150 1 μA μA μA 35 35 0 V V V 10.8 10.8 −24.2 VDDB VSS V V V Ω ns ns ns ns kHz Conditions VAX = 0 V to 5.5 V VDDA = VDDB = 25 V to 30 V, VSS = −5 V to −7 V, VDDA and VDDB to VSS ≤ 35V IOH = −10 mA IOH = −10 mA IOL = +10 mA VDDA = VDDB = +27 V, VSS = −7 V See Figure 2 100 pF load, all channels, see Figure 2 VAX = 0 V or 5.5 V, no load, VDDA ≤ VDDB VDDB to VSS ≤ 35 V VDDB to VSS ≤ 35 V 1 Temperature range for B version is −40°C to +85°C. Typical values are specified at 25°C. 3 Guaranteed by design; not subject to production testing. 2 VDDA 10µF VDDB + 0.1µF 0.1µF VDDA VIN VDDB 50% Z0 = 50Ω ADG3123 VIN AX RS 50Ω 10µF VOUT 100pF RT 50Ω VSS YX VOUT VSS + GND tPHL tPLH 90% 50% 10% tF tR 05655-002 SIGNAL SOURCE + 10µF 0.1µF Figure 2. Switching Characteristics Test Circuit Rev. A | Page 3 of 12 ADG3123 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VDDA/VDDB to VSS VDDB to GND VDDA to GND VSS to GND Digital Inputs 1 Load Current Per Device Average Peak Current 2 Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Thermal Impedance, θJA Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating 44 V −0.3 V to +32 V −0.3 V to VDDB +0.3 V to −32 V VSS − 0.3 V to VDDB + 0.3 V or 20 mA, whichever occurs first 15 mA at 25°C 8 mA at 85°C 150 mA at 25°C 80 mA at 85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. −40°C to +85°C −65°C to +125°C 150°C 78°C/W 3 260 (+0/−5)°C 10 seconds to 40 seconds 1 Overvoltage at Pin A1 to Pin A8 is clamped by internal diodes. Limit the current to the maximum ratings given. 2 Pulsed at 100 kHz; 10% duty cycle maximum with the load shown in Figure 2. 3 Guaranteed when the device is soldered on a 4-layer board. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 4 of 12 ADG3123 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 20 VDDA A1 2 19 Y1 A2 3 18 Y2 A4 5 A5 6 ADG3123 TOP VIEW (Not to Scale) 17 Y3 16 Y4 15 Y5 A6 7 14 Y6 A7 8 13 Y7 A8 9 12 Y8 VSS 10 11 VDDB 05655-003 A3 4 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 to 9 10 11 12 to 19 20 Mnemonic GND A1 to A8 VSS VDDB Y8 to Y1 VDDA Description Ground Reference (0 V). Level Translator CMOS Inputs. Most Negative Power Supply. Use the VSS pin to generate the output low level for Output Y1 to Output Y8. Positive Power Supply. Use the VDDB pin to generate the output high level for Output Y7 and Output Y8. Level Translator High Voltage Outputs. Analog Input. Use the VDDA pin to generate the output high level for Output Y1 to Output Y6 (VDDA ≤ VDDB). Rev. A | Page 5 of 12 ADG3123 TYPICAL PERFORMANCE CHARACTERISTICS 4.1 3.9 3.7 6.5 TA = 25°C VSS = –7V RL = 5kΩ CL = 100pF DUTY CYCLE = 50% 1 CHANNEL 6.0 5.5 VDDA = VDDB = 27V 5.0 IDDB (mA) IDDB (mA) 3.5 TA = 25°C VSS = –7V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL 3.3 4.5 VDDA = VDDB = 27V 4.0 3.1 VDDA = VDDB = 25V 2.9 3.5 VDDA = VDDB = 25V 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 2.5 0.1 05655-004 2.5 10 3.7 3.5 1.1 1.6 2.1 2.6 3.1 3.6 4.1 4.6 CAPACITIVE LOAD (nF) Figure 4. Supply Current (IDDB) vs. Frequency 3.9 0.6 05655-007 3.0 2.7 Figure 7. Supply Current (IDDB) vs. Capacitive Load 4.1 TA = 25°C VSS = –7V RL = 5kΩ CL = 100pF DUTY CYCLE = 50% 1 CHANNEL 3.9 3.7 TA = 25°C VSS = –7V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL IDDA (mA) VDDA = VDDB = 27V 3.1 3.3 VDDA = VDDB = 27V 3.1 2.9 2.9 VDDA = VDDB = 25V VDDA = VDDB = 25V 2.7 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 2.5 0.1 –0.7 VSS = –7V ISS (mA) –5.5 50 60 70 80 FREQUENCY (kHz) 4.1 4.6 VSS = –5V –1.5 40 3.6 –3.5 –4.5 30 3.1 90 100 TA = 25°C VDDA = VDDB = 27V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL –2.5 –1.3 20 2.6 –1.5 –1.1 –1.7 10 2.1 –0.5 –6.5 0.1 05655-006 ISS (mA) –0.9 1.6 Figure 8. Supply Current (IDDA) vs. Capacitive Load TA = 25°C VDDA = VDDB = 27V RL = 5kΩ CL = 100pF DUTY CYCLE = 50% 1 CHANNEL VSS = –5V 1.1 CAPACITIVE LOAD (nF) Figure 5. Supply Current (IDDA) vs. Frequency –0.5 0.6 05655-008 20 05655-005 2.5 10 2.7 VSS = –7V 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 CAPACITIVE LOAD (nF) Figure 6. Supply Current (ISS) vs. Frequency Figure 9. Supply Current (ISS) vs. Capacitive Load Rev. A | Page 6 of 12 4.6 05655-009 IDDA (mA) 3.5 3.3 ADG3123 RISE TIME (ns) 250 200 TA = 25°C VDDA = VDDB = 27V VSS = –7V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL 270 220 tPLH (ns) 300 150 TA = 25°C VDDA = VDDB = 27V VSS = –7V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL 170 100 120 0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10 CAPACITIVE LOAD (nF) 70 0.10 05655-010 0 0.10 400 FALL TIME (ns) 350 1.60 2.10 2.60 3.10 3.60 4.10 Figure 13. Propagation Delay (tPHL) vs. Capacitive Load 10 TA = 25°C VDDA = VDDB = 27V VSS = –7V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL VDDA = VDDB = 27V VSS = –7V TA = 250°C 1 CHANNEL FREQUENCY (MHz) 450 1.10 CAPACITIVE LOAD (nF) Figure 10. Rise Time vs. Capacitive Load 500 0.60 05655-013 50 300 250 200 150 1 05655-014 100 50 0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10 CAPACITIVE LOAD (nF) 0.1 0.01 05655-011 0 0.10 1000 TA = 25°C VDDA = VDDB = 27V VSS = –7V RL = 5kΩ FREQUENCY = 20kHz DUTY CYCLE = 50% 1 CHANNEL 120 100 VDDA = VDDB = 27V VSS = –7V TA = 25°C 8 CHANNELS 100 10 60 0.10 0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10 CAPACITIVE LOAD (nF) 1 0.01 05655-015 80 05655-012 tPLH (ns) 140 10 Figure 14. Maximum Operating Frequency vs. Capacitive Load (One Channel) FREQUENCY (kHz) 160 1 CAPACITIVE LOAD (nF) Figure 11. Fall Time vs. Capacitive Load 180 0.1 0.1 1 10 CAPACITIVE LOAD (nF) Figure 15. Maximum Operating Frequency vs. Capacitive Load (Eight Channels) Figure 12. Propagation Delay (tPLH) vs. Capacitive Load Rev. A | Page 7 of 12 ADG3123 –6.4 27.0 TA = 25°C VDDA = VDDB = 27V VSS = –7V 1 CHANNEL VAX = 0V 26.9 TA = 25°C VDDA = VDDB = 27V VSS = –7V 1 CHANNEL VAX = 5.5V VOH (V) VOL (V) –6.6 26.8 –6.8 0 5 10 LOAD CURRENT (mA) 15 26.6 –15 –10 –5 LOAD CURRENT (mA) Figure 17. Output Voltage (VOH) vs. Load Current Figure 16. Output Voltage (VOL) vs. Load Current Rev. A | Page 8 of 12 0 05655-015 –7.0 05655-014 26.7 ADG3123 TERMINOLOGY VIH Logic input high voltage at Pin A1 to Pin A8. tF Fall time of the output signal at the Pin Y1 to Pin Y8 (see Figure 2). VIL Logic input low voltage at Pin A1 to Pin A8. FO Frequency of the signal applied to the A1 to A8 input pins. IIL Leakage current at Pin A1 to Pin A8. VDDA Input voltage used to generate the high logic levels for Y1 to Y6 outputs. CI Capacitance measured at Pin A1 to Pin A8. VDDB Positive power supply voltage. Also used to generate the high logic levels for Y7 to Y8 outputs. VOH Logic output high voltage at Pin Y1 to Pin Y8. VOL Logic output low voltage at Pin Y1 to Pin Y8. VSS Negative power supply voltage. It is used to generate the low logic level for Y1 to Y8 outputs. Ro Output impedance. tPLH Propagation delay through the part measured between the input signal applied to any one channel and its corresponding output for a low-to-high transition (see Figure 2). tPHL Propagation delay through the part measured between the input signal applied to any one channel and its corresponding output for a high-to-low transition (see Figure 2). GND Ground (0 V) reference. IDDA Supply current at the VDDA pin. IDDB Supply current at the VDDB pin. ISS Supply current at the VSS pin. tR Rise time of the output signal at Pin Y1 to Pin Y8 (see Figure 2). Rev. A | Page 9 of 12 ADG3123 THEORY OF OPERATION The ADG3123 is an 8-channel, noninverting CMOS to high voltage level translator. Fabricated on an enhanced LC2MOS process, the device is capable of operating at high supply voltages while maintaining ultralow power consumption. Capacitive Loads The device requires a dual-supply voltage, VDDB and VSS, which sets the low logic levels for all outputs and the high logic levels for the Y7 and Y8 outputs. The VDDA pin acts as an analog input. The voltage applied to the VDDA pin sets the output high logic level for the Y1 to Y6 outputs. FO is the frequency of the signal applied to the channel in Hz. CL is the load capacitance in farads. VSS is the voltage applied to the VSS pin. VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs. The device translates the CMOS logic levels applied to the A1 to A8 inputs into high voltage bipolar levels available on the Y side of the device at Pin Y1 to Pin Y8. Resistive Loads I CHANNEL ( A) = FO × C L × (VDDX + | VSS |) where: To ensure proper operation, VDDB must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. INPUT DRIVING REQUIREMENTS The ADG3123 design ensures low input capacitance and leakage current thereby reducing the loading of the circuit that drives the input pins (Pin A1 to Pin A8) to a minimum. Its input threshold levels are compliant with JEDEC standards for drivers operated from supply voltages between 2.3 V and 5.5 V. It is recommended that the inputs of any unused channel be tied to a stable logic level (low or high). OUTPUT LOAD REQUIREMENTS The low output impedance of the ADG3123 allows each channel to drive both resistive and capacitive loads. The maximum load current is limited by the current carrying capability of any given channel. If more channels are used, the maximum load current per channel is reduced accordingly. Note that the sum of the load currents on all channels should never exceed the absolute maximum ratings specifications. The average load current on each channel, ICHANNEL, can be determined using the formulas shown in the Capacitive Loads and the Resistive Loads sections. I CHANNEL ( A) = D × VDDX + (1 − D) × VSS RL where: D is the duty cycle of the input signal. D is defined as the ratio between the high state duration of the signal and its period. RL is the load resistor in Ω. VSS is the voltage applied to the VSS pin. VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs. POWER SUPPLIES The ADG3123 operates from a dual-supply voltage. As good design practice for all CMOS devices dictates, power up the ADG3123 first (VDDB and VSS) before applying the signals to its inputs (A1 to A8 and VDDA). To ensure correct operation of the ADG3123, the voltage applied to the VDDB pin must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. To ensure optimum performance, use decoupling capacitors on all power supply pins. Furthermore, good engineering and layout practice suggests placing these capacitors as close as possible to the package supply pins. Rev. A | Page 10 of 12 ADG3123 APPLICATIONS The high voltage operation coupled with high current driving capability and the wide range of CMOS levels accepted by the ADG3123, make the device ideal for LCD-TFT panel applications. In this type of application, the controllers that generate the timing signals required to control the pixel scanning process inside the panel are usually low voltage CMOS devices. Most LCD-TFT panels operate at high supply voltages; therefore, the timing signals generated by the controller require level translation to drive the panel. Figure 18 shows a typical application circuit where the ADG3123 translates eight timing signals provided by the timing controller into high voltage logic levels required to drive the panel. + 10µF 0.1µF ADG3123 1 GND OUT1 2 A1 Y1 19 OUT2 3 A2 Y2 18 OUT3 4 A3 Y3 17 OUT4 5 A4 Y4 16 OUT5 6 A5 Y5 15 OUT6 7 A6 Y6 14 OUT7 8 A7 Y7 13 OUT8 9 A8 10 VSS VDD VDD = +2.3V TO +5.5V –5V TO –10V DC TO DC CONVERTER VDDA 20 LCD-TFT PANEL Y8 12 VDDB 11 + + 10µF 10µF 0.1µF 0.1µF +25V TO +30V +25V TO +30V NOTE: |VDDB | + |VSS| ≤ 35V and VDDA ≤ VDDB Figure 18. Typical Application Circuit Rev. A | Page 11 of 12 05655-016 TIMING CONTROLLER GND ADG3123 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 19. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model ADG3123BRUZ 1 ADG3123BRUZ-REEL1 ADG3123BRUZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP) 20-Lead Thin Shrink Small Outline Package (TSSOP) 20-Lead Thin Shrink Small Outline Package (TSSOP) Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05655-0-5/06(A) Rev. A | Page 12 of 12 Package Option RU-20 RU-20 RU-20