STB75NH02L N-CHANNEL 24V - 0.0062Ω -75A - D2PAK STripFET™ III POWER MOSFET TARGET DATA TYPE STB75NH02L ■ ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 24V < 0.008Ω 75A TYPICAL RDS(on) = 0.0062Ω @ 10 V TYPICAL RDS(on) = 0.008Ω @ 5 V RDS(ON) * Qg INDUSTRY’s BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE SURFACE-MOUNTING D2PAK (TO-263) POWER PACKAGE IN TUBE (NO SUFFIX) OR IN TAPE & REEL (SUFFIX ”T4”) 3 1 D2PAK TO-263 (Suffix “T4”) INTERNAL SCHEMATIC DIAGRAM DESCRIPTION The STB75NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved. APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STB75NH02LT4 B75NH02L D2PAK TAPE & REEL July 2003 1/8 STB75NH02L ABSOLUTE MAXIMUM RATINGS Symbol Vspike(1) VDS VDGR VGS Parameter Value Unit Drain-source Voltage Rating 30 V Drain-source Voltage (VGS = 0) 24 V Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage 24 V ± 20 V ID Drain Current (continuous) at TC = 25°C 75 A ID Drain Current (continuous) at TC = 100°C 53 A IDM (5) PTOT EAS (2) Tstg Tj Drain Current (pulsed) 300 A Total Dissipation at TC = 25°C 85 W Derating Factor 1 W/°C TBD mJ -55 to 175 °C Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 1 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature for Soldering Purpose 300 °C Tl ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Test Conditions Min. Typ. Max. Zero Gate Voltage Drain Current (VGS = 0) VDS = 20V 1 µA VDS = 20V, TC = 125 °C 10 µA Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±100 nA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 30 A VGS = 5 V, ID = 30 A IGSS 24 Unit ID = 25 mA, VGS = 0 IDSS 2/8 Parameter Drain-source Breakdown Voltage V(BR)DSS V 1 V 0.0062 0.008 0.008 0.014 Ω Ω STB75NH02L ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (3) Parameter Test Conditions Min. Typ. Max. Unit Forward Transconductance VDS = 15 V , ID = 30 A TBD S Ciss Input Capacitance VDS = 15 V, f = 1 MHz, VGS = 0 2000 pF Coss Output Capacitance 420 pF Crss Reverse Transfer Capacitance 210 pF 1 Ω Rg Gate Input Resistance f= 1 MHz Gate DC Bias= 0 Test Signal Level= 20 mV Open Drain SWITCHING ON Symbol Parameter Test Conditions Min. Typ. td(on) tr Turn-on Delay Time Rise Time VDD = 10 V, ID = 37.5 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) TBD TBD Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 10 V, ID =75 A, VGS = 10 V 35 TBD TBD Output Charge VDS = 16 V, VGS = 0 TBD Qoss (4) Max. Unit ns ns 47 nC nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions Min. VDD = 10 V, ID = 37.5 A, RG = 4.7 Ω, VGS = 10 V (see test circuit, Figure 3) Typ. Max. TBD TBD Unit ns ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Source-drain Current (pulsed) VSD (3) Forward On Voltage ISD = 37.5 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 75 A, di/dt = 100A/µs, VDD = 15V, Tj = 150°C (see test circuit, Figure 5) IRRM 1. 2. 3. 4. 5. Typ. Source-drain Current ISDM (1) trr Qrr Min. TBD TBD TBD Max. Unit 75 A 300 A 1.3 V ns nC A Garanted when external Rg = 4.7 Ω and tf < tf max Starting Tj = 25°C, ID = 25A, VDD = 15V Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Qoss = Coss*∆ Vin, Coss = Cgd+Cds. See Appendix A Pulse width limited by safe operating area 3/8 STB75NH02L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/8 STB75NH02L D2PAK MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 D1 E 8 0.315 10 E1 10.4 0.393 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R 0.015 0º 8º 3 V2 0.4 5/8 1 STB75NH02L D2PAK FOOTPRINT TUBE SHIPMENT (no suffix)* TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A DIM. mm inch MIN. MAX. MIN. MAX. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 R 50 1.574 T 0.25 0.35 0.0098 0.0137 W 23.7 24.3 * on sales type 6/8 0.075 0.082 0.933 0.956 MAX. MIN. 330 B 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA inch MAX. 12.992 0.059 13.2 0.504 0.520 26.4 0.960 1.039 0795 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 STB75NH02L Appendix A: Buck Converter Power Losses Estimation DESCRIPTION The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: - Very low RDS(on) to reduce conduction losses - Small Qgls to reduce the gate charge losses - Small Coss to reduce losses due to output capaci tance - Small Qrr to reduce losses on SW1 during its turn-on - The Cgd/C gs ratio lower than Vth /VGG ratio especially with low drain to source voltage to avoid the cross conduction phenomenon Pswitching Parameter δ Qgsth Qgls Pconduction Pswitching Pdiode Pdiode PQoss Low Side Switch (SW2) RDS(on)SW1* I *δ RDS(on)SW2* I2L *(1− δ ) Vin *(Qgsth(SW1)+ Qgd(SW1)) *f * IL Ig Zero Voltage Switching Recovery Not Applicable Conduction Not Applicable Vf(SW2) * IL * t deadtime*f Pgate(QG ) Qg(SW1)* Vgg * f Qgls(SW2)* Vgg * f PQoss Vin *Qoss(SW1)*f Vin *Qoss(SW2)*f 2 2 Pdiode The high side (SW1) device requires: - Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate - Small Qg to have a faster commutation and to reduce gate charge losses - Low RDS(on) to reduce the conduction losses High Side Switch (SW1) 2 L Pconduction 1 Vin * Qrr(SW2)*f Meaning Duty-Cycle Post Threshold Gate Charge Third Quadrant Gate Charge On State Losses On-off Transition Losses Conduction and Reverse Recovery Diode Losses Gate Drive Losses Output Capacitance Losses 1 Dissipated by SW1 during turn-on 7/8 STB75NH02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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