CXG1156K Power Amplifier Module for JCDMA Description The CXG1156K is the power amplifier module which operates at a single power supply. This IC is designed using the Sony’s original p-Gate HFET process. 10 pin LCC (Ceramic) Features • Single power supply operation: VDD1 = VDD2 = 3.5V (High power mode), 1.3V (Low power mode 1), 1.0V (Low power mode 2), VGG = 2.7V • Small package: 0.065cc (6.2mm × 6.2mm × 1.7mm) • High efficiency: ηadd = 40%@POUT = 27.5dBm (High power mode), ηadd = 23%@POUT = 15dBm (Low power mode 1) • Output power (high/low power mode switching supported): POUT = 18 to 27.5dBm: High power mode, POUT = 15 to 18dBm: Low power mode 1, POUT ≤ 15dBm: Low power mode 2 • Gain: Gp = 29dB (@900MHz) Applications Power amplifier for JCDMA system cellular phones Structure p-Gate HFET module Absolute Maximum Ratings (Ta = 25°C) • Operating case temperature Tcase –30 to +90 °C • Storage temperature Tstg –30 to +125 °C • Bias voltage VDD1, VDD2 6 V • Bias voltage VGG 3.3 V (@VDD1 = VDD2 = 3.5V) • Input power PIN 8 dBm Recommended Operating Conditions* • VDD1 = VDD2 = 3.2 to 4.2V@POUT = 18 to 27.5dBm, 1.3 to 2.0V@POUT ≤ 18dBm, 1.0 to 2.0V@POUT ≤ 15dBm • VGG = 2.7V ± 1% *This recommended operating voltage is the value that specified the supply voltage range where the functional operation was confirmed by the Sony’s recommended evaluation board. GaAs module is ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02641-PS CXG1156K Package Outline/Pin Configuration Front GND GND 10 9 PIN 1 8 VGG VDD1 2 7 GND VDD2 3 6 POUT 6 POUT 7 GND 8 VGG 4 5 GND GND GND GND 4 5 Back VDD2 3 VDD1 2 PIN 1 11 GND 10 9 GND GND Note) Be sure to solder the GND part (11) to the land. For the land where the GND part (11) is connected, form the GND pattern by making the throgh holes in the land. –2– CXG1156K Electrical Characteristics Item (ZS = ZL = 50Ω, IS-95 Modulation, Tc = 25°C) Conditions Min. Typ. 887 Frequency Max. Unit 925 MHz Current consumption 1 POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V 405 420 mA Current consumption 2 POUT = 15dBm, VDD = 1.3V, VGG = 2.7V 105 110 mA Current consumption 3 POUT = 12dBm, VDD = 1.0V, VGG = 2.7V 79 90 mA Gain 1 POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V 25 29 dB Gain 2 POUT = 18dBm, VDD = 1.3V, VGG = 2.7V 22 24 dB Gain 3 POUT = 15dBm, VDD = 1.0V, VGG = 2.7V 20 22 dB ACPR1 (High power mode) POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V, ±900kHz offset, 30kHz band width –54 –47 dBc ACPR2 (High power mode) POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V, ±1.98MHz offset, 30kHz band width –64 –58 dBc ACPR1 (Low power mode 1) POUT = 18dBm, VDD = 1.3V, VGG = 2.7V, ±900kHz offset, 30kHz band width –56 –50 dBc ACPR2 (Low power mode 1) POUT = 18dBm, VDD = 1.3V, VGG = 2.7V, ±1.98MHz offset, 30kHz band width –63 –58 dBc ACPR1 (Low power mode 2) POUT = 15dBm, VDD = 1.0V, VGG = 2.7V, ±900kHz offset, 30kHz band width –56 –50 dBc ACPR2 (Low power mode 2) POUT = 15dBm, VDD = 1.0V, VGG = 2.7V, ±1.98MHz offset, 30kHz band width –63 –58 dBc 2nd, 3rd harmonics POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V –27 –23 dBc Input VSWR VDD = 3.5V, VGG = 2.7V 1.3 2 Gate current VGG = 2.7V, POUT ≤ 27.5dBm 1.7 2.5 –3– mA CXG1156K Recommended External Circuit C1: 1µF C2: 10µF GND GND PIN VGG C1 C2 VDD1 C2 C1 C2 C1 GND GND VDD2 POUT GND GND Recommended Evaluation Board Board material: Glass fabric-base epoxy Size: 40mm × 50mm × 0.6mm Relative dielectric constant: 4.6 Front Back VGG GND C2 GND C1 PIN POUT VDD1 C1 C1 C2 C2 GND GND VDD2 –4– CXG1156K Example of Representative Characteristics Conditions: f = 900MHz VDD1 = VDD2 = 3.5V, VGG = 2.7V (High power mode) VDD1 = VDD2 = 1.3V, VGG = 2.7V (Low power mode 1) Ta = 25°C IDD vs. POUT 600 550 500 400 350 300 250 200 150 100 50 0 ACPR1 vs. POUT ACPR2 vs. POUT VDD = 3.5V VDD = 1.3V ACPR2 [dBc] ACPR1 [dBc] 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] PIN [dBm] –34 –36 –38 –40 –42 –44 –46 –48 –50 –52 –54 –56 –58 –60 –62 –64 –66 –68 –70 –72 –74 VDD = 3.5V VDD = 1.3V 450 IDD [mA] POUT [dBm] POUT vs. PIN 32 30 VDD = 3.5V 28 VDD = 1.3V 26 24 22 20 18 16 14 12 10 8 6 4 2 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] –48 –50 –52 –54 –56 –58 –60 –62 –64 –66 –68 –70 –72 –74 –76 –78 VDD = 3.5V VDD = 1.3V 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] –5– CXG1156K Package Outline Unit: mm 10PIN LCC SOLDERING POINT X 6.0 6.0 + 0.5 ∗6.2 - 0.3 1.7 ± 0.15 0.1Max 0.2 S PIN 1 INDEX 0.1 S ∗6.2 ± 0.3 S SOLDERING POINT Detail X 3.8 2 7 1 8 1.1 ± 0.15 6 4.9 3 3.4 ± 0.15 TERMINAL 1.7 ± 0.1 4 Y 1.6 5 0.15 1.4 0.9 COAT SUBSTRATE COAT 10 2 × 2-R0.2 2-R0.2 0.15 0.15 C0.1 9 R0.2 0.15 4-R0.2 0.6 ± 0.2 Detail Y TERMINAL PACKAGE STRUCTURE NOTE: Dimension "∗" does not include cutting burr. SONY CODE LCC-10C-03 PACKAGE MATERIAL CERAMIC SUBSTRATE TERMINAL TREATMENT GOLD PLATING JEITA CODE TERMINAL MATERIAL NICKEL PLATING JEDEC CODE PACKAGE MASS 0.8g –6– Sony Corporation