ESDALC6V1-5P6 ESD protection for high speed interface Features ■ Diode array topology ■ Low capacitance (12 pF typical) ■ Lead-free package SOT666 Benefits ■ Low capacitance uni-directional ESD protection. ■ Low PCB space consuming, 2.5 mm2 max. footprint ■ Low leakage current ■ High reliability offered by monolithic integration Figure 1. ESDALC6V1-5P6 functional diagram Complies with the following standards ■ IEC 61000-4-2 level 4: – 8 kV (contact discharge) – 15 kV (air discharge) ■ MIL STD 883G-Method 3015-7: class3B – Human body model Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment Description The ESDALC6V1-5P6 is a monolithic array designed to protect up to 5 lines against ESD transients. The device is ideal for high speed interface applications where both reduced printed circuit board space and power absorption capability are required. November 2007 Rev 3 1/8 www.st.com 8 Characteristics 1 ESDALC6V1-5P6 Characteristics Table 1. Absolute ratings (Tamb = 25 °C) Symbol Parameter IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge VPP(1) Peak pulse voltage PPP (1) Peak pulse power dissipation (8/20 µs) Value Unit ±8 ± 15 kV 30 W Tj initial = Tamb IPP Peak pulse current (8/20 µs) 2.5 A Tj Junction temperature 125 °C -55 to +150 °C 260 °C - 40 + 125 °C Storage temperature range Tstg TL Maximum lead temperature for soldering during 10 s Operating temperature range TOP 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT Voltage temperature coefficient VF Forward voltage drop C Capacitance Rd Dynamic resistance Parameter VRRM VF VCL VBR VRM = 3 V VCL Non repetitive peak pulse voltage (8/20 µs) VF IF = 10 mA Rd C Min Typ 6.1 Unit 5 V 7.2 V 70 nA 10 IPP = 2.5 A 14 V 1 IR = 1 mA VR = 0 V DC, F = 1 MHz, Vosc = 30 mV rms Max IPP = 1 A 2 1. ΔVBR = αT x (Tamb - 25 °C) x VBR (25 °C) 2/8 IPP Reverse stand-off voltage IRM V IRM Test condition IR = 1 mA αT VRM Slope: 1/Rd VBR (1) I IF 12 V 3 Ω 5 10-4/°C 15 pF ESDALC6V1-5P6 Figure 2. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 3. Peak pulse power versus exponential pulse duration (Tj initial = 25 °C) PPP(W) PPP[Tj initial] / PPP[Tj initial=25°C) 1.1 1000 Tj initial = 25°C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj(°C) tp(µs) 0.0 10 0 25 Figure 4. 50 75 100 125 150 Clamping voltage versus peak pulse current (typical values) 1 10 Figure 5. IPP(A) 100 Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj=25°C] 10.0 1000 8/20 µs Tj initial = 25°C VR=3V 100 1.0 10 Tj(°C) VCL(V) 1 0.1 5 6 Figure 6. 7 8 9 10 11 12 13 14 25 15 Breakdown voltage versus initial junction temperature 50 Figure 7. VBR 75 100 125 150 Junction capacitance versus reverse voltage applied (typical values) C(pF) 8.0 14 1 mA F=1MHz VOSC=30mVRMS Tj=25°C 12 10 8 7.0 6 4 2 VR(V) Tj(°C) 6.0 0 25 50 75 100 125 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3/8 Characteristics Figure 8. ESDALC6V1-5P6 ESD response to IEC 61000-4-2 (air discharge +15 kV surge) Figure 9. 10 V per div. ESD response to IEC 61000-4-2 (air discharge -15 kV surge) 10 V per div. 0.1 µs per division 0.1 µs per division Figure 10. Frequency response curves - all lines together Figure 11. Crosstalk response curves - 1/2 and 1/3 dB dB 0.00 0.00 - 20.00 - 6.00 - 40.00 - 12.00 - 60.00 - 80.00 - 18.00 - 100.00 - 24.00 - 120.00 F (Hz) - 30.00 100.0k 1.0M Line 1 Line 3 4/8 10.0M 100.0M Line 2 Line 5 1.0G F (Hz) - 140.00 100.0k Xtalk 1.0M 1/2 10.0M 100.0M Xtalk 1/3 1.0G ESDALC6V1-5P6 2 Application information Application information Figure 12. Application schematic diagram V DD IMAGE PROCESSING Viewfinder FrontEnd JPEG Encoder SCL BB interface Image Sensor SDA Sensor Controller I2C I2CBUS BUS(115kbs) (115khz) EN DCLCK D0 D1 D2 D3 D4 D5 D6 D7 BB IC BB IC HSYNC VSYNC FLASH MEMORY 3 Ordering information scheme Figure 13. Ordering information scheme ESDA LC 6V1 - 5 P6 ESD Array Low Capacitance Breakdown Voltage (min) 6V1 = 6.1 Volt Number of lines protected 5 Package P6 = SOT666 5/8 Package information 4 ESDALC6V1-5P6 Package information ● Epoxy meets UL 94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. SOT666 dimensions Dimensions b1 Ref. Millimeters Inches L1 Min. L3 Typ. Max. Min. Typ. Max. A 0.45 0.60 0.018 0.024 A3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 D 1.50 1.70 0.059 0.067 E 1.50 1.70 0.059 0.067 E1 1.10 1.30 0.043 0.051 b D E1 0.27 0.34 0.007 0.011 0.013 A L2 E A3 e 0.50 0.020 L1 0.19 0.007 L2 0.10 0.30 0.004 0.012 e L3 0.10 Figure 14. SOT666 footprint (dimensions in mm) 0.50 0.62 0.99 0.30 6/8 2.60 0.004 ESDALC6V1-5P6 Ordering information Figure 15. Tape and reel specifications Dot identifying Pin A1 location 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 3.5 ± 0.1 8 ± 0.3 0.69 ± 0.05 4 ± 0.1 User direction of unreeling All dimensions in mm Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. 5 Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC6V1-5P6 J(1) SOT666 2.9 mg 3000 Tape and reel 1. The marking can be rotated by 90° to diferentiate assembly location 6 Revision history Table 5. Document revision history Date Revision Description of changes 29-May-2007 1 First issue. 30-Jul-2007 2 Upgrade VCL from 8 V to 10 V and from 9.5 V to 14 V. 15-Nov-2007 3 Reformatted to current standards. Marking changed to J in Table 4. Notes on marking rotation added to Table 4 and Figure 15. 7/8 ESDALC6V1-5P6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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