FDS4070N3 40V N-Channel PowerTrench MOSFET General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for “low side” synchronous rectifier operation, providing an extremely low RDS(ON) in a small package. • 15.3 A, 40 V. RDS(ON) = 7.5 mΩ @ VGS = 10 V • High performance trench technology for extremely low RDS(ON) • High power and current handling capability Applications • Fast switching, low gate charge • Synchronous rectifier • FLMP SO-8 package: Enhanced thermal • DC/DC converter performance in industry-standard package size 5 Absolute Maximum Ratings Symbol Bottom-side Drain Contact 4 6 3 7 2 8 1 TA=25oC unless otherwise noted Ratings Units VDSS Drain-Source Voltage Parameter 40 V VGSS Gate-Source Voltage ± 20 V ID Drain Current (Note 1a) 15.3 A PD Maximum Power Dissipation (Note 1a) 3.0 W TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C (Note 1a) 40 °C/W (Note 1) 0.5 – Continuous – Pulsed 60 Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS4070N3 FDS4070N3 13’’ 12mm 2500 units 2004 Fairchild Semiconductor Corporation FDS4070N3 Rev B2 (W) FDS4070N3 February 2004 Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 310 mJ 15.3 A Drain-Source Avalanche Ratings (Note 2) EAS Drain-Source Avalanche Energy IAS Drain-Source Avalanche Current Single Pulse, VDD=40V, ID=15.3A Off Characteristics Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient ID = 250 µA VGS = 0 V, ID = 250 µA, Referenced to 25°C Zero Gate Voltage Drain Current VDS = 32 V, IGSSF Gate–Body Leakage, Forward IGSSR Gate–Body Leakage, Reverse BVDSS ∆BVDSS ∆TJ IDSS On Characteristics VGS(th) ∆VGS(th) ∆TJ RDS(on) gFS 40 V mV/°C 42 1 µA VGS = 20 V, VDS = 0 V 100 nA VGS = –20 V, VDS = 0 V –100 nA VGS = 0 V (Note 2) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance Forward Transconductance ID = 250 µA VDS = VGS, ID = 250 µA, Referenced to 25 °C VGS = 10 V, ID = 15.3 A VGS = 10 V, ID=15.3A, TJ =125°C VDS = 10 V, ID = 15.3 A 2 3.9 –8 5 5.5 8 52 7.5 12 V mV/°C mΩ S Dynamic Characteristics Ciss VDS = 20 V, f = 1.0 MHz Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn–On Delay Time tr Turn–On Rise Time td(off) Turn–Off Delay Time tf Turn–Off Fall Time Qg Total Gate Charge Qgs Gate–Source Charge Qgd Gate–Drain Charge V GS = 0 V, 2819 pF 600 pF 291 pF (Note 2) VDD = 20 V, VGS = 10 V, VDS = 20 V, VGS = 10 V ID = 1 A, RGEN = 6 Ω ID = 15.3 A, 16 29 ns 12 22 ns 41 66 ns 29 46 ns 47 67 nC 15 nC 14 nC FDS4070N3 Rev B2 (W) FDS4070N3 Electrical Characteristics Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 2.5 A 1.2 V Drain–Source Diode Characteristics and Maximum Ratings IS VSD trr Qrr Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward IS = 2.5 A VGS = 0 V, Voltage Diode Reverse Recovery Time IF = 15.3 A, diF/dt = 100 A/µs Diode Reverse Recovery Charge 0.7 (Note 2) 32 nS 39 nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 40°C/W when mounted on a 1in2 pad of 2 oz copper b) 85°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size pape 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0 FDS4070N3 Rev B2 (W) FDS4070N3 Electrical Characteristics FDS4070N3 Typical Characteristics 60 ID, DRAIN CURRENT (A) 3 6.0V 5.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 10V 50 7.0V 40 5.0V 30 20 4.5V 10 VGS = 5.0V 2.6 2.2 1.8 5.5V 6.0V 1.4 7.0V 10V 1 0.6 0 0 0.25 0.5 0.75 1 1.25 0 1.5 10 20 Figure 1. On-Region Characteristics. 50 60 0.015 ID = 7.7A ID = 15.3A VGS = 10V 1.6 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 40 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 0.013 0.011 TA = 125oC 0.009 0.007 TA = 25oC 0.005 0.003 150 4 5 o TJ, JUNCTION TEMPERATURE ( C) 6 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation withTemperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 60 IS, REVERSE DRAIN CURRENT (A) VDS = 5V 50 ID, DRAIN CURRENT (A) 30 ID, DRAIN CURRENT (A) VDS, DRAIN-SOURCE VOLTAGE (V) 40 30 TA =125oC 20 25oC 10 -55oC 3 3.5 4 4.5 5 TA = 125oC 1 25oC 0.1 -55oC 0.01 0.001 0.0001 0 2.5 VGS = 0V 10 5.5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 6 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4070N3 Rev B2 (W) FDS4070N3 Typical Characteristics 4000 ID = 15.3 VDS = 10V 20V 8 CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 10 30V 6 4 3000 2000 COSS 1000 2 CRSS 0 0 0 10 20 30 40 0 50 10 20 Figure 7. Gate Charge Characteristics. 40 Figure 8. Capacitance Characteristics. 1000 P(pk), PEAK TRANSIENT POWER (W) 50 100 100µs RDS(ON) LIMIT 1ms 10ms 100ms 1s 10 10s DC 1 VGS = 10V SINGLE PULSE RθJA = 85oC/W 0.1 TA = 25oC 0.01 0.01 0.1 1 10 SINGLE PULSE RθJA = 85°C/W TA = 25°C 40 30 20 10 0 0.01 100 0.1 1 VDS, DRAIN-SOURCE VOLTAGE (V) 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) ID, DRAIN CURRENT (A) f = 1MHz VGS = 0 V CISS Figure 10. Single Pulse Maximum Power Dissipation. 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 85 °C/W 0.2 0.1 0.1 P(pk) 0.05 t1 0.02 0.01 t2 0.01 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDS4070N3 Rev B2 (W) FDS4070N3 Dimensional Outline and Pad Layout FDS4070N3 Rev B2 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I8