HIP0061 60V, 3.5A, 3-Transistor Common Source ESD Protected Power MOSFET Array December 1997 Features Description • Three 3.5A Power MOS N-Channel Transistors The HIP0061 is a power MOSFET array that consists of three matched N-Channel enhancement mode MOS transistors connected in a common source configuration. The advanced Harris PASIC2 process technology used in this product utilizes efficient geometries that provides outstanding device performance and ruggedness. • Output Voltage to 60V • rDS(ON) . . . . . 0.225Ω Max Per Transistor at VGS = 10V • Pulsed Current . . . . . . . . . . . . . . . . 10A Each Transistor • Avalanche Energy . . . . . . . . . . 100mJ Each Transistor The HIP0061 is designed to integrate three power devices in one chip thus providing board layout area and heat sink savings for applications such as Motor Controls, Lamps, Solenoids and Resistive Loads. • Grounded Tab Eliminates Heat Sink Isolation Applications • Automotive Symbol • Appliance • Industrial Control DRAIN1 • Robotics DRAIN2 2 DRAIN3 5 7 • Relay, Solenoid, Lamp Drivers Ordering Information PART NUMBER TEMP. RANGE (oC) GATE1 GATE2 GATE3 1 3 6 PKG. NO. PACKAGE 4 HIP0061AS1 -40 to 125 7 Ld Staggered Vertical SIP Z7.05C HIP0061AS2 -40 to 125 7 Ld Gullwing SIP Z7.05B SOURCE, TAB Pinouts HIP0061AS1 (SIP - VERTICAL) TOP VIEW HIP0061AS2 (SIP - GULLWING) TOP VIEW 7 6 5 4 3 2 1 DRAIN3 GATE3 DRAIN2 SOURCE GATE2 DRAIN1 GATE 1 7 6 5 4 3 2 1 DRAIN3 GATE3 DRAIN2 SOURCE GATE2 DRAIN1 GATE 1 TAB TAB TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4 TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 3982.3 HIP0061 TA = 25oC Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) SIP-Vertical Package . . . . . . . . . . . . . 55 3 SIP-Gullwing Package . . . . . . . . . . . . 55 3 Maximum Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Drain to Source Voltage, VDS (Over Operating Junction and Case Temperature Range) . . . . 60V Drain to Gate Voltage, VDGR . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Gate to Source Voltage, VGS . . . . . . . . . . . . . . . . . . . . . . .-15, +20V Pulsed Drain Current, IDM, Each Output, All Outputs on at VGS = 10V (Notes 1, 2) . . . . . . . . . . . . . . . . 10A Continuous Source to Drain Diode Current, ISD at VGS = 10V (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5A Continuous Drain Current, IDS, Each Output, All Outputs on at VGS = 10V (Note 2) . . . . . . . . . . . . . . . . . . 3.5A Single Pulse Avalanche Energy, EAS (Note 3) . . . . . . . . . . . . 100mJ Die Characteristics Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . V- (Source, Tab) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC Drain to Source On-State Voltage Range . . . . . . . . . . . . 5V to 10V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Pulse width limited by maximum junction temperature. 2. Drain current limited by package construction. 3. VDD = 25V, Start TJ = 25oC, L = 15mH, RGS = 50Ω, IPEAK = 3.5A. See Figures 1, 2, 12, and 13. 4. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETERS Drain to Source Breakdown Voltage SYMBOL BVDSS TEST CONDITIONS ID = 100µA, VGS = 0V TC = -40o C to 125oC TC = 25o C Gate Threshold Voltage Zero Gate Voltage Drain Current VGS(TH) IDSS VGS = VDS, ID = 250µA VDS = 60V VGS = 0V MIN TYP MAX UNITS 60 - - V - 70 - V 1.8 2.3 2.7 V TC = 25o C - - 1 µA TC = 125o C - - 10 µA Forward Gate Current, Drain Short Circuited to Source IGSSF VDS = 0V, VGS = 20V - - 100 nA Reverse Gate Current, Drain Short Circuited to Source IGSSR VDS = 0V, VGS = -15V - - -100 nA rDS(ON) VGS = 10V, ID = 3.5A TC = 25oC - 0.215 0.265 Ω VGS = 10V, ID = 3.5A TC = 125oC - 0.365 0.425 Ω VGS = 5V, ID = 2A TC = 25oC - 0.275 0.320 Ω VGS = 5V, ID = 2A TC = 125oC - 0.465 0.5 Ω rDS(ON) VGS = 10V, ID = 3.5A TC = 25oC - 95 - % gfs VDS = 10V, ID = 1A - 2.5 - S VDD = 30V, RL = 15Ω, VGS = +10V, ID = 2A, RG = 50Ω See Figure 14 - 10 - ns - 25 - ns td(OFF) - 18 - ns tf - 12 - ns - 8.0 9.5 nC - 0.7 1.0 nC - 3.5 4.0 nC Drain to Source On Resistance (Note 5) Drain to Source On Resistance Matching Forward Transconductance (Note 5) Turn-On Delay Time (Note 6) Rise Time (Note 6) Turn-Off Delay Time (Note 6) Fall Time (Note 6) Total Gate Charge (Note 6) td(ON) tr Qg(TOT) Gate-Source Charge (Note 6) Qgs Gate-Drain Charge (Note 6) Qgd VDS = 50V, VGS = 10V, ID = 2A See Figures 16, 17 2 HIP0061 Electrical Specifications TC = 25oC, Unless Otherwise Specified (Continued) PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 142 - pF Short-Circuit Input Capacitance, Common Source CISS VDS = 25V, VGS = 0V f = 1MHz Short-Circuit Output Capacitance, Common Source COSS - 107 - pF Short-Circuit Reverse Transfer Capacitance, Common Source CRSS - 24 - pF Source-Drain Diode Ratings and Specifications PARAMETERS SYMBOL Diode Forward Voltage (Note 5) VSD Reverse Recovery Time trr MIN TYP MAX UNITS ISD = 2A, VGS = 0V TEST CONDITIONS - 0.9 1.1 V ISD = 2A, dISD/dt = 100A/µs - 50 - ns NOTES: 5. Pulse test: Pulse width ≤ 300µs, duty cycle ≤ 2%. 6. Independent of operating temperature. Typical Performance Curves 10µs 10 ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 10 100µs 1ms 10ms 100ms DC 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10µs 100µs 100µs 1 TC = 25oC TJ = MAX RATED 0.1 10 1 1 VDS , DRAIN VOLTAGE (V) 10ms 100ms DC TC = 105oC TJ = MAX RATED 0.1 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 1B. 105oC SAFE-OPERATING AREA CURVE FIGURE 1A. 25oC SAFE-OPERATING AREA CURVE 50 IAS, AVALANCHE CURRENT (A) ID , DRAIN CURRENT (A) 10 10µs 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 TC = 125oC TJ = MAX RATED 1 100µs 1ms 10ms 100ms DC 10 STARTING TJ = 25oC STARTING TJ = 125oC 10 5 1 0.001 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 1C. 125oC SAFE-OPERATING AREA CURVE 0.01 0.1 tAV , TIME IN AVALANCHE (ms) FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING 3 1.0 HIP0061 Typical Performance Curves 20 VGS = 10V VGS = 8V VGS = 6V VDS = 15V -40oC VGS = 5V 25oC 125oC 7.5 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10.0 (Continued) 5.0 VGS = 4V 2.5 15 10 5 PULSE DURATION = 300µs, TC = 25oC 0 0 2 4 6 0 0 10 8 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. TYPICAL TRANSFER CHARACTERISTICS 2.5 1.2 PULSE DURATION = 300µs, VGS = 10V, ID = 3.5A ID = 100µA 2.0 NORMALIZED BVDSS rDS(ON), NORMALIZED ON RESISTANCE FIGURE 3. TYPICAL SATURATION CHARACTERISTICS 1.5 1.0 0.5 0 -75 -25 25 75 125 1.1 1.0 0.9 0.8 -75 175 -25 TJ, JUNCTION TEMPERATURE (oC) FIGURE 5. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE 175 12 VGS, GATE-SOURCE VOLTAGE (V) VGS = VDS, ID = 250µA 1.5 1.0 0.5 0 -75 25 75 125 TJ, JUNCTION TEMPERATURE (oC) FIGURE 6. NORMALIZED BVDSS vs JUNCTION TEMPERATURE 2.0 VGS(TH), NORMALIZED 10 -25 25 75 125 VDS = 50V VDS = 30V VDS = 20V 8 4 ID = 2.0A, TC = 25oC 0 175 0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION TEMPERATURE 2 4 6 Q, GATE CHARGE (nC) 8 FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE 4 10 HIP0061 Typical Performance Curves 5 VGS = 0V, f = 1MHz, TC = 25oC 600 ID , DRAIN CURRENT (A) C, CAPACITANCE (pF) 750 (Continued) 450 CISS COSS CRSS 300 150 3 VGS = 10V VGS = 5V 2 1 0 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 25 50 75 100 150 FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 1 125 TC, CASE TEMPERATURE (oC) FIGURE 9. TYPICAL CAPACITANCE vs VOLTAGE ZθJC, NORMALIZED THERMAL IMPEDANCE 4 TC = 25oC D = 1.0 0.5 0.2 0.1 0.1 0.05 0.02 0.01 NOTES: 1. DUTY FACTOR, D = t1/t2 2. PEAK TJ = PDM x (ZθJC) +TC SINGLE PULSE 10-6 10-5 10-4 10-3 t, RECTANGULAR PULSE DURATION (s) 10-2 10-1 FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE Test Circuits and Waveforms tP VDS VGS L RG DUT 0V tP 10 V 0 IAS + - VGS tAV VDD ID ID 0 BVDSS VDS 0.01Ω 0 FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS 5 HIP0061 Test Circuits and Waveforms tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% VDS 90% VGS 10% DUT 10% 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 15. RESISTIVE SWITCHING WAVEFORMS FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT CURRENT REGULATOR + 10V BATTERY 0.2µF +VDS Qg SAME TYPE AS DUT 10V 25kΩ - 0.1µF Qgs VG DUT 0 Qgd IGS CHARGE FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. BASIC GATE CHARGE WAVEFORM 6 HIP0061 PSPICE Model Listing Device Model Netlist for the HIP0061 Power MOSFET Array *Rev: 6/12/95 .SUBCKT HIP0061 1 2 3 4 5 6 7 X1 8 1 11 4 HIP0061_1 LS1 2 8 7.5n X2 9 3 11 4 HIP0061_1 LS2 5 9 7.5n X3 10 6 11 4 HIP0061_1 LS3 7 10 7.5n LS4 4 11 7.5n .ENDS .SUBCKT HIP0061_1 3 2 11 9 MOS1 4 2 1 1 NMOS1 JFET 13 1 4 J1 D1 5 6 D1 DBODY 1 13 D2 DBREAK 3 7 D3 DSUB 9 13 D4 DESD1 2 12 D5 DESD2 15 12 D5 VBREAK 7 1 DC 90 C21 2 1 750P C23 2 13 45P C24 2 4 1100P RDRAIN 13 14 9.0e-02 LDRAIN 14 3 7.5n RSOURCE 1 15 17.5e-03 LSOURCE 15 11 7.5n FDSCHRG 4 2 VMEAS 1.0 E41 5 15 4 1 1.0 VPINCH 6 8 DC 10.0 VMEAS 8 15 DC 0.0 .MODEL NMOS1 NMOS LEVEL=3 (VTO=2.75 TOX=5e-08 KP=3.150e-03 PHI=0.65 GAMMA=2.55 + VMAX=6.42e+07 NSUB=4.33e+16 THETA=0.60973 ETA=0.0015 KAPPA=1.275 + L=1u W=3050u) .MODEL J1 NJF (VTO=-15.0 BETA=10.736 LAMBDA=1.15e-02 PB=0.5848 IS=+1.0e-13 + RD=3.53e-02 ALPHA=0.2) .MODEL D1 D (IS=1.0e-15 N=0.03 RS=1.0) .MODEL D2 D (IS=3.0e-13 RS=2.5e-03 TT=20N CJO=350e-12) .MODEL D3 D (IS=1.0e-13 N=1.0 RS=2.0) .MODEL D4 D (IS=1.0e-13 RS=2.0e-03 CJO=80e-12) .MODEL D5 D (IS=1.0e-15 RS=1.0e-03 CJO=2.5e-12) .ENDS NOTE: For further discussion of the PSPICE PowerFET macromodel consult Spicing-Up SPICE II Software for Power MOSFET Modeling, Harris Application Note AN8610. 7 HIP0061 Single-In-Line Plastic Packages (SIP) -A- A Z7.05B 0.006 -B- (0.15) E 7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT “GULLWING” LEAD FORM C2 INCHES L2 HEATSLUG PLANE D -CL 0.00 - 0.0098 (0.00 - 0.25) L1 PIN #1 c 0o- 8o e b 0.010 (0.25) M B A M 0.004 (0.10) C M L3 SYMBOL MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - C2 0.048 0.055 1.22 1.39 5 D 0.350 0.370 8.89 9.39 - E 0.395 0.405 10.04 10.28 - D1 0.310 - 7.88 E1 0.310 - 7.88 0.549 0.569 13.95 14.45 - L1 0.068 0.088 1.72 2.24 - L2 0.045 0.055 1.15 1.40 - 0.350 (8.89) MIN 0.76 BSC - 4 b 0.028 0.034 0.71 0.86 5, 6, 7 c 0.018 0.024 0.46 0.60 5 0.050 BSC 1.27 BSC Rev. 2 12/95 NOTES: 0.609 (15.46) MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-169AC, Issue A. 2. Controlling dimension: Inch. 3. Dimensioning and tolerance per ANSI Y14.5M-1982. 4. Gauge plane L3 is parallel to heatslug plane. 5. Dimensions include lead finish. 6. Leads are not allowed above the datum -B- . 7. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” by more than 0.003’’ (0.08mm). BACK VIEW 0.129 (3.27) TYP 0.030 (0.76) TYP 0.030 BSC - - L e D1 - E1 L3 0.450 (11.43) MIN MILLIMETERS e LAND PATTERN 8 HIP0061 Single-In-Line Plastic Packages (SIP) Z7.05C 0.006 (0.15) 7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM A INCHES D -BØP D1 F E2 HEADER BOTTOM E L1 E1 L -A- e B e3 e1 C 7 PLACES 0.010 (0.25) M e2 A B M ALL LEADS 0.024 (0.61) M A MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.170 0.180 4.32 4.57 - B 0.028 0.034 0.71 0.86 3, 4 C 0.018 0.024 0.46 0.60 3 D 0.395 0.405 10.04 10.28 - D1 0.198 0.202 5.03 5.13 - E 0.595 0.605 15.11 15.37 - E1 0.350 0.370 8.89 9.39 - E2 0.110 BSC 2.79 BSC NOTES e 0.050 BSC 1.27 BSC - e1 0.200 BSC 5.08 BSC - e2 0.169 BSC 4.29 BSC - e3 0.300 BSC 7.62 BSC - F 0.048 0.055 1.22 1.39 3 L 0.150 0.176 3.81 4.47 - L1 0.600 0.620 15.24 15.74 - ØP 0.147 0.152 3.73 3.86 3 Rev. 0 6/95 NOTES: 1. Controlling dimension: INCH. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimensions include lead finish. 4. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall not cause lead width to exceed maximum “B” by more than 0.003 inches (0.08mm). All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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