PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS843002I-40 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS843002I-40 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock VCO. PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or STM-16 (SDH). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application. • (2) Differential LVPECL outputs ICS • Selectable CLKx, nCLKx differential input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels • Maximum output frequency: 175MHz • FemtoClock VCO frequency range: 560MHz - 700MHz • RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical) • Full 3.3V or mixed 3.3V core/2.5V output supply voltage • -40°C to 85°C ambient operating temperature PIN ASSIGNMENT nCLK1 V EE CLK1 R_SEL0 R_SEL1 R_SEL2 XTAL_IN XTAL_OUT The ICS843002I-40 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. “Hitless switching” is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. 32 31 30 29 28 27 26 25 LF1 1 24 LOR0 LF0 2 23 LOR1 ISET 3 22 nc VCC 4 21 VCCO_LVCMOS CLK0 5 20 VCCO_LVPECL nCLK0 6 19 nQB CLK_SEL 7 18 QB nc 8 17 VEE • Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz QA nQA VCCA nc QB_SEL0 • Loop bandwidth: 50Hz - 250Hz QB_SEL1 QA_SEL1 • VCXO 19.44MHz crystal QA_SEL0 9 10 11 12 13 14 15 16 Typical ICS843002I-40 configuration in SONET/SDH Systems: ICS843002I-40 32-Lead VFQFN 5mm x 5mm x 0.75mm package body K Package Top View • Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, Hi-Z The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843002AKI-40 www.icst.com/products/hiperclocks.html 1 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR BLOCK DIAGRAM LF0 Phase Detector VCCO_LVCMOS CLK1 nCLK1 Activity Detector 1 R Divider = 1, 2, 4, 8, 16 or 32 Divide by 32 LF1 Charge Pump and Loop Filter XTAL_OUT ISET ICS843002-40 19.44 MHz Pullable xtal XTAL_IN External Loop Components VCXO 19.44 MHz LOR1 0 CLK0 nCLK0 Divide by 32 Activity Detector VCXO Jitter Attenuation PLL LOR0 VCCO_LVPECL 622.08 MHz CLK_SEL 110 FemtoClock PLL x32 110 QA nQA C0 Divider = 4, 8, 32, or HiZ 111 2 QA_SEL1:0 111 R_SEL2:0 QB nQB C1 Divider = 4, 8, 32, or HiZ 3 2 QB_SEL1:0 NOTE 1: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications. 843002AKI-40 www.icst.com/products/hiperclocks.html 2 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 LF1, LF0 3 ISET Type Analog Input/Output Analog Input/Output Power 4 VCC 5 CLK0 Input 6 nCLK0 Input 7 9, 10 12, 13 CLK_SEL QA_SEL1, QA_SEL0 QB_SEL1, QB_SEL0 Description Loop filter connection node pins. Charge pump current setting pin. Core power supply pin. Input Pulldown Pullup/ Pulldown Pulldown Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 bias voltage when left floating. Input clock select. LVCMOS/LVTTL interface levels. See Table 3A. Input Pullup LVPECL output divider control for QA/nQA outputs. See Table 3C. Input Pullup LVPECL output divider control for QB/nQB outputs. See Table 3C. 14 VCCA Power Analog supply pin. 15, 16 QA, nQA Output Differential clock output pair. LVPECL interface levels. 17, 27 VEE Power Negative supply pins. 18, 19 QB, nQB Output Differential clock output pair. LVPECL interface levels. 20 VCCO_LVPECL Power Output power supply pin for QA, nQA and QB, nQB. Power supply pin for LOR0 and LOR1. 21 VCCO_LVCMOS Power 8, 11, 22 nc Unused 23 LOR1 Output 24 LOR0 Output 25 nCLK1 Input No connect. Alarm output, loss of reference for CLK1. LVCMOS/LVTTL interface levels. Alarm output, loss of reference for CLK0. LVCMOS/LVTTL interface levels. Pullup/ Inver ting differential clock input. Pulldown VCC/2 bias voltage when left floating. Pulldown Non-inver ting differential clock input. 26 CLK1 Input 28, R_SEL0, R_SEL1, Input Pulldown Input divider selection. LVCMOS/LVTTL interface. See Table 3B. 29, R_SEL2 30 Cr ystal oscillator interface. XTAL_OUT is the output. 31, XTAL_OUT, Input XTAL_IN is the input. 32 XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 50 kΩ RPULLDOWN Input Pulldown Resistor 50 kΩ 843002AKI-40 Test Conditions www.icst.com/products/hiperclocks.html 3 Minimum Typical Maximum Units REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TABLE 3A. INPUT REFERENCE SELECTION FUNCTION TABLE Inputs CLK_SEL Input Selected 0 CLK0 1 CLK1 TABLE 3B. INPUT REFERENCE DIVIDER SELECTION FUNCTION TABLE Inputs R_SEL2:0 R Divider Value or State 000 ÷1 001 ÷2 010 ÷4 011 ÷8 100 ÷16 101 ÷32 110 bypass VCXO PLL 111 bypass VCXO and FemtoClock™ PLL's TABLE 3C. OUTPUT DIVIDER SELECTION FUNCTION TABLE Inputs Qx_SEL1:0 Output Divider Value or State 00 Output Q and nQ Hi-Z 01 ÷32 10 ÷8 11 ÷4 843002AKI-40 www.icst.com/products/hiperclocks.html 4 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, VI -0.5V to VCC + 0.5V Maximum Ratings may cause permanent damage to the Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA yond those listed in the DC Characteristics or AC Character- Package Thermal Impedance, θJA 34.8°C/W (0 lfpm) conditions for extended periods may affect product reliability. Storage Temperature, TSTG -65°C to 150°C istics is not implied. Exposure to absolute maximum rating TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC VCCA Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V VCCO_LVCMOS, VCCO_LVPECL Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IEE Power Supply Current 175 mA ICCA Analog Supply Current 10 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVCMOS = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current CLK_SEL, R_SEL0:2 VCC = VIN = 3.465V 15 0 µA QA_SEL0:1, QB_SEL0:1 VCC = VIN = 3.465V 5 µA CLK_SEL, R_SEL0:2 QA_SEL0:1, QB_SEL0:1 VOH Output High Voltage LOR0, LOR1; NOTE 1 VOL Output Low Voltage LOR0, LOR1; NOTE 1 VCC = 3.465V, -5 µA VCC = 3.465V, VIN = 0V -150 µA VCCO_LVCMOS = 3.3V 2.6 V VCCO_LVCMOS = 2.5V 1.8 V VIN = 0V VCCO_LVCMOS = 3.3V or 2.5V 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO_LVCMOS/2 .See Parameter Measurement Information Section, “Output Load Test Circuit”. 843002AKI-40 www.icst.com/products/hiperclocks.html 5 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVPECL = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum Typical CLK0, CLK1 nCLK0, nCLK1 VIN = VCC = 3.465V Maximum Units 150 µA 150 µA CLK0, CLK1 VIN = 0V, VCC = 3.465V -5 µA nCLK0, nCLK1 VIN = 0V, VCC = 3.465V -150 µA 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V. 1.3 V VCC - 0.85 V TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVPECL = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V Peak-to-Peak Output Voltage Swing 0.6 1.0 VSWING NOTE 1: Outputs terminated with 50 Ω to VCCO_LVPECL - 2V. See "Parameter Measurement Information" section, "Output Load Test Circuit". V TABLE 5. CRYSTAL CHARACTERISTICS Symbol Parameter fN Nominal Frequency Test Conditions Minimum Typical Maximum 19.44 Units MHz fT Frequency Tolerance ±TBD ppm fS Frequency Stability ±TBD ppm CL Load Capacitance 12 pF CO Shunt Capacitance 4 pF CO/C1 Pullability Ratio ESR Equivalent Series Resistance Operating Temperature Range 0 70 220 Drive Level Mode of Operation 843002AKI-40 °C 240 50 Ω 1 mW Fundamental www.icst.com/products/hiperclocks.html 6 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter tsk(o) Output Frequency RMS Phase Jitter, (Random); NOTE 1 Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time FOUT tjit(ø) Test Conditions Minimum Typical 19.44 Maximum Units 175 MHz 155.52MHz, Integration range: 12kHz - 20MHz 0.81 ps 105 ps 20% to 80% 890 ps odc Output Duty Cycle 50 See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter tsk(o) Output Frequency RMS Phase Jitter, (Random); NOTE 1 Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time FOUT tjit(ø) Test Conditions Minimum Typical 19.44 155.52 MHz, Integration range: 12kHz - 20MHz 20% to 80% www.icst.com/products/hiperclocks.html 7 Units 175 MHz 0.83 ps 95 ps 900 ps odc Output Duty Cycle 50 See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 843002AKI-40 Maximum % REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TYPICAL PHASE NOISE AT 155.52MHZ ➤ 0 -10 -20 -30 Filter 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical) -40 -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -50 -120 ➤ -130 -140 -150 Phase Noise Result by adding Filter to raw data -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843002AKI-40 www.icst.com/products/hiperclocks.html 8 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 2V 2.8V±0.04V 2V VCC , VCCA, VCCO_LVPECL Qx SCOPE VCC , VCCA Qx SCOPE VCCO_LVPECL LVPECL LVPECL VEE nQx VEE -1.3V ± 0.165V nQx -0.5V ± 0.125V 3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power VCC nCLK0, nCLK1 V V Cross Points PP Phase Noise Mask CMR nCLK0, nCLK1 f1 V EE Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot DIFFERENTIAL INPUT LEVEL PHASE JITTER nQx nQA, nQB QA, QB Qx t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 843002AKI-40 www.icst.com/products/hiperclocks.html 9 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR APPLICATION INFORMATION DESCRIPTION OF THE PLL STAGES SETTING THE VCXO PLL LOOP RESPONSE The ICS843002I-40 is a two stage device, a VCXO PLL followed by a low phase noise FemtoClock PLL. The VCXO uses an external pullable crystal which can be pulled ±100ppm by the VCXO PLL circuitry to phase lock it to the input reference frequency. The FemtoClock PLL is a wide bandwidth PLL (about 800kHz) which means it will phase track the VCXO PLL. Most of the reference clock jitter attenuation needs to be accomplished by VCXO PLL. The VCXO PLL loop response is determined both by fixed device characteristics and by other characteristics set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. The VCXO PLL loop bandwidth is approximated by: RS x ICP x KO NBW (VCXO PLL) = By using the bypass FemtoClock PLL mode (Table 3B), the selected input reference clock can be passed directly to the FemtoClock PLL which will multiply it up by 32 to a higher frequency. A second mode, VCXO and FemtoClock bypass, routes the selected input refrence directly to the LVPECL output dividers. 32 WHERE: RS = Value of resistor RS in loop filter in Ohms ICP = Charge pump current in amps (see table on page 12) KO = VCXO Gain in Hz/V The above equation calculates the “normalized” loop bandwidth (denoted as “NBW”) which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. VCXO PLL LOOP RESPONSE CONSIDERATIONS Loop response characteristics of the VCXO PLL is affected by the VCXO feedback divider value (bandwidth and damping factor), and by the external loop filter components (bandwidth, damping factor, and 2 nd frequency response). A practical range of VCXO PLL bandwidth is from about 10Hz to about 1kHz. The setting of VCXO PLL bandwidth and damping factor is covered later in this document. A PC based PLL bandwidth calculator is also under development. For assistance with loop bandwidth suggestions or value calculation, please contact ICS applications. To prevent jitter on the clock output due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed: NBW (VCXO PLL) ≤ ƒ (Phase Detector) 20 ƒ (Phase Detector) = Input Frequency ÷ (R Divider x 32) The PLL loop damping factor is determined by: DF (VCLK) = RS 2 x ICP x CS x KO 32 WHERE: CS = Value of capacitor CS in loop filter in Farads 843002AKI-40 www.icst.com/products/hiperclocks.html 10 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR EXTERNAL VCXO PLL COMPONENTS CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband. A higher damping factor may also increase lock time and output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for phase noise ingress. LF1 LF0 CP RS ISET 32 CP also dampens VCXO PLL input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO PLL input voltage can hit the supply or ground rail resulting in nonlinear loop response. 31 1 2 The best way to set the value of CP is to use the filter response software under development from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak. 3 CS LOOP FILTER RESPONSE SOFTWARE RSET Online tools to calculate loop filter response (coming soon) at www.icst.com. Contact your local sales representative if a tool cannot be found for this product. The external crystal devices and loop filter components should be kept close to the device. Loop filter and crystal PCB connection traces should be kept short and well separated from each other and from other signal traces. Other signal traces should not run underneath the device, the loop filter or crystal components. NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS In the loop filter schematic diagram, capacitors are shown between pins 32 to ground and between pins 31 to ground. These are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). Note that the addition of external load capacitors will decrease the crystal pull range and the Kvco value. NOTES ON SETTING THE VALUE OF CP As another general rule, the following relationship should be maintained between components CS and CP in the loop filter: CP = CS 20 LOSS OF REFERENCE INDICATOR (LOR0 AND LOR1) OUTPUT PINS. The LOR0 and LOR1 pins are controlled by the internal clock activity monitor circuits. The clock activity monitor circuits are clocked by the VCXO PLL phase detector feedback clock. The LOR output is asserted high if there are three consecutive feedback clock edges without any reference clock edges (in both cases, either a negative or positive transition is counted 843002AKI-40 as an “edge”). The LOR output will otherwise be low. The activity monitor does not flag excessive reference transitions in an phase detector observation interval as an error. The monitor only distinguishes between transitions occurring and no transitions occurring. www.icst.com/products/hiperclocks.html 11 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR NOTES ON SETTING CHARGE PUMP CURRENT The recommended range for the charge pump current is 50μA to 300μA. Below 50μA, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor. CHARGE PUMP CURRENT, EXAMPLE SETTINGS RSET Charge Pump Current (ICP) 17.6k 62.5µA 8.8k 125µA 4.4k 250µA 2.2k 500µA ICP, Amps 1E-3 100E-6 10E-6 1k 10k RSET, Ω FIGURE 1. CHARGE PUMP CURRENT 843002AKI-40 VS. VALUE OF 100k RSET (EXTERNAL www.icst.com/products/hiperclocks.html 12 RESISTOR) GRAPH REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843002I-40 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. TERMINATION FOR 3.3V VCC 10 Ω .01μF VCCA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 843002AKI-40 www.icst.com/products/hiperclocks.html 13 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 843002AKI-40 FIN 50Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 14 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 5E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 843002AKI-40 BY www.icst.com/products/hiperclocks.html 15 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR SINGLE ENDED CLOCK INPUT INTERFACE When using a LVCMOS or LVTTL clock driver, the clock input is connected to the CLKx (CLK0 or CLK1) input pin. The nCLKx (nCLK0 or nCLK1) pin is left unconnected. To help reduce interference with the internal VCO circuits, an external resistor can be placed in series with the clock signal right near the CLKx input pin. Combined with the input pin Series Termination LVTTL or LVCMOS Optional Series Filter Resistor (no connection) capacitance, this resistor acts as a low pass signal filter. The typical value for this optional series filter resistor is 100Ω. This will lower both the amplitude and edge rate of the clock input signal. In the case of a very short clock trace a series termination resistor may not be needed. 3.3V CLKx 3.3V CLK 50kΩ nCLKx nCLK 50kΩ 50kΩ Differential Input Stage Internal Device Circuitry External Circuitry FIGURE 6. SINGLE-ENDED CLOCK INPUT INTERFACE 843002AKI-40 www.icst.com/products/hiperclocks.html 16 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843002I-40. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843002I-40 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 175mA = 606.375mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 606.375mW + 60mW = 666.38mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming an air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 34.8°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.666W * 34.8°C/W = 108.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN VFQFN, FORCED CONVECTION θJA vs. Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 843002AKI-40 34.8°C/W www.icst.com/products/hiperclocks.html 17 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (V CCO_MAX • -V OH_MAX ) = 0.9V For logic low, VOUT = V =V OL_MAX (V CCO_MAX -V OL_MAX CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX ))/R ] * (V -V OH_MAX CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω) * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843002AKI-40 www.icst.com/products/hiperclocks.html 18 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR A 32 LEAD VFQFN θJA vs. Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W TRANSISTOR COUNT The transistor count for ICS843002I-40 is: 5536 843002AKI-40 www.icst.com/products/hiperclocks.html 19 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR FOR A 32 LEAD VFQFN TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL A 0.80 A1 0 -- 1.00 -- 0.05 0.25 Ref. A3 b 0.18 0.25 8 NE 5.00 BASIC D 1.25 2.25 1.25 2.25 3.25 0.50 BASIC e L 3.25 5.00 BASIC E E2 0.30 8 ND D2 MAXIMUM 32 N 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 843002AKI-40 www.icst.com/products/hiperclocks.html 20 REV. A JUNE 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843002AKI-40 ICS43002A40 32 Lead VFQFN tray -40°C to 85°C ICS843002AKI-40T ICS43002A40 32 Lead VFQFN 2500 tape & reel -40°C to 85°C The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843002AKI-40 www.icst.com/products/hiperclocks.html 21 REV. A JUNE 22, 2005