PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS853058 is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL Clock Multiplexer which can HiPerClockS™ operate up to 2.5GHz and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853058 has 8 differential selectable clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL2 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 000 selects PCLK0, nPCLK0). • High speed 8:1 differential multiplexer ICS • 1 differential 3.3V or 2.5V LVPECL output • 8 selectable differential PCLK, nPCLK inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2.5GHz • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input • Part-to-part skew: TBD • Propagation delay: 620ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PCLK0 nPCLK0 000 PCLK1 nPCLK1 001 PCLK2 nPCLK2 010 PCLK3 nPCLK3 011 PCLK4 nPCLK4 100 PCLK5 nPCLK5 101 PCLK6 nPCLK6 110 PCLK7 nPCLK7 111 PIN ASSIGNMENT PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 Q0 nQ0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PCLK7 nPCLK7 PLCK6 nPCLK6 VCC Q0 nQ0 VEE PCLK5 nPCLK5 PCLK4 nPCLK4 ICS853058 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View SEL2 SEL1 SEL0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853058AG www.icst.com/products/hiperclocks.html REV. A APRIL 13, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 PCLK0 Type Input 2 nPCLK0 Input 3 PCLK1 Input Description Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. 4 nPCLK1 Input 5, 20 VCC Power 6, 7, 8 SEL0, SEL1, SEL2 Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. 9 PCLK2 Input Pulldown Non-inver ting differential LVPECL clock input. Positive supply pins. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. 10 nPCLK2 Input 11 PCLK3 Input Pulldown 12 nPCLK3 Input Pullup/Pulldown Inver ting differential LVPECL clock input. VCC/2 default when left floating. 13 nPCLK4 Input Pullup/Pulldown Inver ting differential LVPECL clock input. VCC/2 default when left floating. 14 PCLK4 Input Pulldown 15 nPCLK5 Input 16 PCLK5 Input Non-inver ting differential LVPECL clock input. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. 17 VEE Power Negative supply pin. 18, 19 nQ0, Q0 Output Differential output pair. LVPECL interface levels. 21 nPCLK6 Input Pullup/Pulldown 22 PCLK6 Input Pulldown 23 nPCLK7 Input Pullup/Pulldown 24 PCLK7 Input Pulldown Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 853058AG www.icst.com/products/hiperclocks.html 2 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units KΩ RVDD/2 Pullup/Pulldown Resistosr 50 KΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs Outputs SEL2 SEL1 SEL0 Q0 nQ0 0 0 0 PCLK0 nPCLK0 0 0 1 PCLK1 nPCLK1 0 1 0 PCLK2 nPCLK2 0 1 1 PCLK3 nPCLK3 1 0 0 PCLK4 nPCLK4 1 0 1 PCLK5 nPCLK5 1 1 0 PCLK6 nPCLK6 1 1 1 PCLK7 nPCLK7 853058AG www.icst.com/products/hiperclocks.html 3 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Inputs, VI (LVPECL mode) 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to V + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Negative Supply Voltage, VEE CC Outputs, IO Continuous Current Surge Current cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- 50mA 100mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 70°C/W (0 mps) mum rating conditions for extended periods may affect product reliability. (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage Test Conditions ICC Power Supply Current Minimum Typical Maximum Units 2.375 3.3 3.465 V 38 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V Symbol Parameter VIH Input High Voltage VIL Test Conditions Minimum SEL0:SEL2 Input Low Voltage SEL0:SEL2 IIH Input High Current SEL0:SEL2 IIL Input Low Current SEL0:SEL2 VCC = VIN = 3.465V, VCC = VIN = 2.625V VCC = 3.465V, VIN = 0V, VCC = 2.625V, VIN = 0V Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V 150 µA -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V Symbol Parameter Test Conditions Typical Units 150 µA -10 µA nPCLK0:nPCLK7 VCC = 3.465V, VIN = 0V -150 µA 0.15 V Input High Current IIL Input Low Current V PP VOH Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage Voltage; NOTE 3 VOL Output Low Voltage; NOTE 3 VCC = VIN = 3.465V 1.2 3.3 www.icst.com/products/hiperclocks.html 4 V VCC - 1.005 V VCC - 1.78 V Peak-to-Peak Output Voltage Swing 0.8 VSWING NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. 853058AG Maximum VCC = 3.465V, VIN = 0V IIH VCMR Minimum PCLK0:PCLK7 nPCLK0:nPCLK7 PCLK0:PCLK7 V REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 -1.005 V VOL Output Low Voltage; NOTE 1 -1.78 V VIH Input High Voltage -1.225 -0.94 V VIL Input Low Voltage -1.87 -1.535 V V PP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK0:PCLK7 High Current nPCLK0:nPCLK7 PCLK0:PCLK7 Input Low Current nPCLK0:nPCLK7 VCMR IIH IIL 800 VEE + 1.2 mV 0 V 150 µA -10 µA -150 µA NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V OR VCC = 2.375 TO 3.465V; VEE = 0V Symbol Parameter Test Conditions Minimum Typical Maximum Units 2.5 GHz fMAX Output Frequency t PD Propagation Delay; NOTE 1 620 ps tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 TBD ps Output Rise/Fall Time 20% to 80% 150 tR / tF All parameters measured up to 1.3GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. 853058AG www.icst.com/products/hiperclocks.html 5 ps REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx V CC SCOPE nPCLK0:7 LVPECL V Cross Points PP V CMR PCLK0:7 nQx VEE VEE -1.465V to -0.375V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nPCLK0:7 nQx PART 1 Qx PCLK0:7 nQ0 nQy PART 2 Qy Q0 tPD t sk(pp) PROPAGATION DELAY PART-TO-PART SKEW 80% 80% VOD Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 853058AG www.icst.com/products/hiperclocks.html 6 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 853058AG 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 853058AG www.icst.com/products/hiperclocks.html 8 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER LVPECL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 Zo = 60 Ohm SSTL Zo = 50 Ohm R4 120 PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL IN DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V R4 125 R3 125 Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PCL K/n PC LK R2 1K FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853058AG www.icst.com/products/hiperclocks.html 9 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER SCHEMATIC EXAMPLE nation approaches are available in the LVPECL Termination Application Note. It is recommended at least one decoupling capacitor per power pin. The decoupling capacitor should be low ESR and located as close as possible to the power pin. An application schematic example of ICS853058 is shown in Figure 5. The inputs can accept various types of differential signals. In this example, the inputs are driven by 3.3V LVPECL drivers. The ICS853058 output is an LVPECL driver. An example of LVPECL terminations is shown this schematic. Other termi- Zo = 50 Logic Control Input Examples Set Logic Input to '1' 3.3V Zo = 50 LVPECL R1 50 R2 50 Set Logic Input to '0' 3.3V RU2 Not Install RU1 1K To Logic Input pins To Logic Input pins R3 50 RD2 1K RD1 Not Install Zo = 50 U1 Zo = 50 3.3V LVPECL R4 50 R5 50 R6 50 C1 0.1u 1 2 3 4 5 6 7 8 9 10 11 12 PCLK7 nPCLK7 PCLK6 nPCLK6 VCC Q0 nQ0 GND PCLK5 nPCLK5 PCLK4 nPCLK4 PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 24 23 22 21 20 19 18 17 16 15 14 13 Zo = 50 3.3V + Zo = 50 - LVPECL C2 0.1u R7 50 R8 50 ICS853058 R9 50 FIGURE 5. ICS853058 SCHEMATIC EXAMPLE 853058AG www.icst.com/products/hiperclocks.html 10 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853058. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853058 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V ± 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 38mA = 131.67mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30.94mW = 30.94mW Total Power_MAX (3.465V, with all outputs switching) = 131.67mW + 30.94mW = 162.61mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.163W * 65°C/W = 95.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP FORCED CONVECTION θJA by Velocity (Meters per Second) 0 70°C/W Multi-Layer PCB, JEDEC Standard Test Boards 853058AG www.icst.com/products/hiperclocks.html 11 1 65°C/W 2.5 62°C/W REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX =V OL_MAX CCO_MAX -V OL_MAX CCO_MAX – 0.935V ) = 0.935V For logic low, VOUT = V (V =V CCO_MAX – 1.67V ) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V OH_MAX )= [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.67V)/50Ω] * 1.67V = 11.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853058AG www.icst.com/products/hiperclocks.html 12 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) 0 70°C/W Multi-Layer PCB, JEDEC Standard Test Boards 1 65°C/W 2.5 62°C/W TRANSISTOR COUNT The transistor count for ICS853058 is: 326 853058AG www.icst.com/products/hiperclocks.html 13 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 E E1 7.90 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 853058AG www.icst.com/products/hiperclocks.html 14 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS853058AG ICS853058AG 24 Lead TSSOP 60 per tube -40°C to 85°C ICS853058AGT ICS853058AG 24 Lead TSSOP on Tape and Reel 2500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853058AG www.icst.com/products/hiperclocks.html 15 REV. A APRIL 13, 2004