IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V
LVPECL FANOUT BUFFER
FEATURES:
DESCRIPTION:
• Five differential 3.3V LVPECL outputs
• Selectable differential CLK, xCLK, or LVPECL clock inputs
• CLK, xCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, and HCSL
• PCLK, xPCLK supports the following input types: LVPECL, CML,
and SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on xCLK input
• Output skew: 35ps (max.)
• Part-to-part skew: as low as 150ps
• Propagation delay: 2.1ns (max.)
• 3.3V operating supply
• Available in TSSOP package
The IDT85304-01 is a low skew, high performance 1-to-5 differential-to3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The
CLK/ xCLK pair can accept most standard differential input levels. The PCLK/
xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable
is internally synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the IDT8530401 ideal for those applications that demand well-defined performance and
repeatability.
FUNCTIONAL BLOCK DIAGRAM
D
CLK_EN
Q
LE
CLK
xCLK
0
Q0
PCLK
xPCLK
xQ0
1
Q1
xQ1
Q2
xQ2
CLK_SEL
Q3
xQ3
Q4
xQ4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2004
1
c
2004
Integrated Device Technology, Inc.
DSC 6174/2
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Power Supply Voltage
4.6
V
Input Voltage
–0.5 to VDD+0.5
V
VO
–0.5 to VDD+0.5 V
92.6
°C/W
Q0
1
20
VDD
xQ0
2
19
CLK_EN
θJA
Output Voltage
Package Thermal Impedance (0 lfpm)
Q1
3
18
VDD
TSTG
Storage Temperature
4
17
xPCLK
Q2
5
16
PCLK
xQ2
6
15
VEE
Q3
7
14
xCLK
xQ3
8
13
CLK
Q4
9
12
CLK_SEL
xQ4
10
11
VDD
Unit
VDD
VI
xQ1
Max
–65 to +150
°C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter
CIN
RPULLUP
RPULLDOWN
Description
Typ.
Max.
Unit
Input Capacitance
—
4
pF
Input Pullup Resistor
51
—
KΩ
Input Pulldown Resistor
51
—
KΩ
TSSOP
TOP VIEW
PIN DESCRIPTION(1)
Symbol
Number
xQ0, Q0
1, 2
Output
Type
Differential Output Pair. LVPECL interface levels.
Description
xQ1, Q1
3, 4
Output
Differential Output Pair. LVPECL interface levels.
xQ2, Q2
5, 6
Output
Differential Output Pair. LVPECL interface levels.
xQ3, Q3
7, 8
Output
Differential Output Pair. LVPECL interface levels.
xQ4, Q4
9, 10
Output
Differential Output Pair. LVPECL interface levels.
VDD
11, 18, 20
Power
Positive Supply Pins
CLK_SEL
12
Input
Pulldown
Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects
CLK / xCLK inputs. LVTTL / LVCMOS interface levels.
CLK
13
Input
Pulldown
Pullup
xCLK
14
Input
VEE
15
Power
Non-Inverting Differential Clock Input
Inverting Differential Clock Input
Negative Supply Pin
PCLK
16
Input
Pulldown
xPCLK
17
Input
Pullup
Non-Inverting Differential LVPECL Clock Input
Inverting Differential LVPECL Clock Input
CLK_EN
19
Input
Pullup
Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS
interface levels.
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
2
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE(1,2)
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0:Q4
xQ0:xQ4
0
0
CLK, xCLK
Disabled; LOW
Disabled; HIGH
0
1
PCLK, xPCLK
Disabled; LOW
Disabled; HIGH
1
0
CLK, xCLK
Enabled
Enabled
1
1
PCLK, xPCLK
Enabled
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Enabled
Disabled
CLK0, CLK1
≈
CLK EN
≈
≈
xQ0, xQ1, xQ2, xQ3, xQ4
Q0, Q1, Q2, Q3, Q4
CLK_EN Timing Diagram
CLOCK INPUT FUNCTION TABLE(1)
Inputs
Outputs
CLK or PCLK
xCLK or xPCLK
Q0:Q4
xQ0:xQ4
Input to Output Mode
Polarity
0
1
L
H
Differential to Differential
Non-Inverting
1
0
Non-Inverting
H
L
Differential to Differential
0
(2)
Biased
L
H
Single-Ended to Differential
Non-Inverting
1
Biased(2)
H
L
Single-Ended to Differential
Non-Inverting
Biased(2)
0
H
L
Single-Ended to Differential
Inverting
Biased(2)
1
L
H
Single-Ended to Differential
Inverting
NOTES:
1. H = HIGH
L = LOW
2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
3
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Positive Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
—
—
55
mA
Max.
Unit
2
VDD + 0.3
V
-0.3
0.8
V
µA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL
Symbol
Parameter
Test Conditions
Min.
Typ.
VIH
Input Voltage, HIGH
CLK_EN,
VIL
Input Voltage, LOW
CLK_EN,
IIH
Input Current HIGH
CLK_EN
VIN = VDD = 3.465V
5
CLK_SEL
VIN = VDD = 3.465V
150
CLK_SEL
CLK_SEL
IIL
Input Current LOW
CLK_EN
VIN = 0V, VDD = 3.465V
-150
CLK_SEL
VIN = 0V, VDD = 3.465V
-5
µA
DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL
Symbol
Parameter
Test Conditions
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage
IIH
IIL
(1,2)
Input Current HIGH
Input Current LOW
Min.
Max.
Unit
0.15
Typ.
1.3
V
0.5
VDD - 0.85
V
µA
xCLK
VIN = VDD = 3.465V
5
CLK
VIN = VDD = 3.465V
150
xCLK
VIN = 0V, VDD = 3.465V
-150
CLK
VIN = 0V, VDD = 3.465V
-5
µA
NOTES:
1. For single-ended applications, the max. input voltage for CLK / xCLK is VDD + 0.3V.
2. Common mode voltage is defined as VIH.
DC ELECTRICAL CHARACTERISTICS, LVPECL
Symbol
IIH
IIL
Parameter
Input Current HIGH
Input Current LOW
Test Conditions
Min.
Typ.
Max.
Unit
µA
PCLK
VIN = VDD = 3.465V
150
xPCLK
VIN = VDD = 3.465V
5
PCLK
VIN = 0V, VDD = 3.465V
-5
xPCLK
VIN = 0V, VDD = 3.465V
-150
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage
VEE + 1.5
VDD
V
VOH
Output Voltage HIGH(3)
VDD - 1.4
VDD - 1
V
VOL
Output Voltage LOW(3)
VDD - 2
VDD - 1.7
V
0.6
0.85
V
VSWING
0.15
µA
(1,2)
Peak-to-Peak Output Voltage Swing
NOTES:
1. For single-ended applications, the max. input voltage for PCLK / xPCLK is VDD + 0.3V.
2. Common mode voltage is defined as VIH.
3. Outputs terminated with 50Ω to VDD - 0.2V.
4
1.3
V
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
All parameters measured at 500MHz unless noted otherwise;
Cycle-to-cycle jitter = jitter on output; the part does not add jitter
Symbol
FMAX
tPD
Parameter
Test Conditions
Min.
f ≤ 650MHz
1
Output Frequency
Propagation Delay(1)
tSK(O)
Output Skew
tSK(PP)
Part-to-Part Skew
tR
Output Rise Time
20 - 80% @ 50MHz
300
Output Fall Time
20 - 80% @ 50MHz
300
tF
odc
Typ.
(2,4)
(3,4)
Output Duty Cycle
48
50
Max.
Unit
650
MHz
2.1
ns
35
ps
150
ps
700
ps
700
ps
52
%
NOTES:
1. Measured from the differential input crossingpoint to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
5
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
VDD
Scope
Z = 50Ω
Qx
LVPECL
50Ω
VDD = 2V
Z = 50Ω
xQx
50Ω
VEE = -1.3V ± 0.135V
Output Load Test Circuit
VDD
xCLK, xPCLK
Cross Points
VPP
CLK, PCLK
VEE
Differential Input Level
xQx
Qx
xQy
Qy
tSK(0)
Output Skew
6
VCMR
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION - CONTINUED
80%
80%
VSWING
Clock Outputs
20%
20%
tF
tR
Input and Output Rise and Fall Time
xCLK, xPLK
CLK, PCLK
xQ0, xQ1, xQ2, xQ3, xQ4
Q0, Q1, Q2, Q3, Q4
tPD
Propagation Delay
xQ0, xQ1, xQ2, xQ3, xQ4
Q0, Q1, Q2, Q3, xQ4
Pulse Width
tPERIOD
tW
odc =
tPERIOD
odc and tPERIOD
7
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage VREF ∼ VDD/2 is generated by the
bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to
position the VREF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, VREF should be 1.25V and R2/
R1 = 0.609.
VDD
R1
1K
CLK_IN
+
VREF
C1
0.1uF
-
R2
1K
Single-Ended Signal Driving Differential Input
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
3.3V
Zo = 50Ω
5
2
FOUT
Zo
5
2
Zo
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
FIN
50Ω
Zo = 50Ω
VDD - 2V
RTT
1
RTT =
3
2
Zo
Zo
3
2
Zo
(VOH + VOL / VDD - 2) - 2
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
8
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the IDT85304-01. Equations and example calculations are also provided.
POWER DISSIPATION:
The total power dissipation for the IDT85304-01is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation
for the VDD = 3.3V + 5% = 3.465V, which gives worst case results. Please refer to the following section, Calculations and Equations, for details on calculating
power dissipated in the load.
Power (core)MAX = VDD_MAX * IEE_MAX = 3.465 * 55mA = 190.57mW
Power (outputs)MAX = 30.2mW/Loaded Output Pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW
JUNCTION TEMPERATURE:
Junction temperature (tJ) is the temperature at the junction of the bond wire and bond pad. It directly affects the reliability of the device. The maximum
recommended junction temperature for this device is 125°C.
The equation for is as follows: tJ = θJA * Pd_total + TA
tJ = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Power Dissipation, above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance (θJA) must be used. Assuming a moderate air flow of 200
linear feet per minute and a multi-layer board, the appropriate value is 77.6°C/W per the following Thermal Resistance table. Therefore, tJ for an ambient
temperature of 70°C with all its outputs switching is:
70°C + 0.341W * 77.6°C/W = 96.46°C. This is well below the limit of 125°C.
This calculation is only an example. tJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (singlelayer or multi-layer).
THERMAL RESISTANCE
θJA for 20-pin TSSOP, forced convenction
θJA by Velocity (Linear Feet per mInute)
Multi-Layer PCB, JEDEC Standard Test boards
9
0
200
400
Unit
92.6
77.6
70.9
°C/W
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CALCULATIONS AND EQUATIONS
VDD
Q1
VOUT
RL
50
VDD - 2V
LVPECL Output Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations, which assume a 50Ω load and a termination voltage of VDD – 2V.
For Logic HIGH: VOUT = VOH_MAX = VDD_MAX – 1V.
(VDD_MAX – VOH_MAX) = 1V
For Logic LOW: VOUT = VOL_MAX = VDD_MAX – 1.7V.
(VDD_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives HIGH.
Pd_L is power dissipation when the output drives LOW.
Pd_H = {[ VOH_MAX – (VDD_MAX – 2V)] / RL} * (VDD_MAX – VOH_MAX) = {[ 2V – (VDD_MAX – VOH_MAX)] / RL} * (VDD_MAX – VOH_MAX) = [( 2V – 1V) / 50Ω] *
1V = 20mW.
Pd_L = {[ VOL_MAX – (VDD_MAX – 2V)] / RL} * (VDD_MAX – VOL_MAX) = {[ 2V – (VDD_MAX – VOL_MAX)] / RL} * (VDD_MAX – VOL_MAX) = [( 2V – 1.7V) / 50Ω] *
1.7V = 10.2mW.
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
10
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
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Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
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Thin Shrink Small Outline Package
85304-01
Low Skew, 1-to-5 Differential-to-3.3V LVPECL
Fanout Buffer
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
11
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