ISL28286, ISL28486 ® Data Sheet June 28, 2007 Dual and Quad Micropower Single Supply Rail-to-Rail Input and Output (RRIO) Precision Op Amp The ISL28286 and ISL28486 are dual and quad channel micropower operational amplifiers optimized for single supply operation over the 2.4V to 5V range. They can be operated from one lithium cell or two Ni-Cd batteries. For equivalent performance in a single channel op amp reference EL8186. FN6312.1 Features • Low power 120µA typical supply current (ISL28286) • 600µV maximum offset voltage • 500pA typical input bias current • 400kHz typical gain-bandwidth product • 115dB typical PSRR and CMRR • Single supply operation down to 2.4V These devices feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages 10% above the positive supply rail and down to the negative supply. The output operation is rail to rail. • Input is capable of swinging above V+ and to V- (ground sensing) The ISL28286 and ISL28486 draw minimal supply current while meeting excellent DC-accuracy, AC-performance, noise and output drive specifications. The ISL28286 contains a power down enable pin that reduces the power supply current to less than 4µA max in the disabled state. Applications Pinouts • Medical devices ISL28286 (10 LD MSOP) TOP VIEW IN+_A 1 + EN_A 2 V- 3 EN_B 4 • Battery- or solar-powered systems • 4mA to 25mA current loops • Handheld consumer products • Photodiode pre-amps 10 IN-_A • pH probe amplifiers 9 OUT_A Ordering Information 7 OUT_B IN+_B 5 • Pb-free plus anneal available (RoHS compliant) • Thermocouple amplifiers 8 V+ + - • Rail-to-rail input and output (RRIO) 6 IN-_B PART NUMBER (Note) PART MARKING PACKAGE (Pb-free) PKG. DWG. # ISL28286FUZ* 8286Z 10 Ld MSOP MDP0043 ISL28486FAZ* 28486 FAZ 16 Ld QSOP MDP0040 *Add “-T7” suffix for tape and reel. Please refer to TB347 for details on reel specifications. ISL28486 (16 LD QSOP) TOP VIEW OUT_A 1 16 OUT_D 15 IN-_D IN-_A 2 + + IN+_A 3 14 IN+_D V+ 4 13 V- IN+_B 5 12 IN+_C + - + - IN-_B 6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 11 IN-_C 10 OUT_C OUT_B 7 NC 8 9 NC 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28286, ISL28486 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Output Short-Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance θJA (°C/W) 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 112 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. DESCRIPTION CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT DC SPECIFICATIONS VOS Input Offset Voltage ΔV OS --------------ΔT Input Offset Voltage vs Temperature IOS Input Offset Current -2.5 -2.5 ±0.25 2.5 2.5 nA IB Input Bias Current -2 -2.5 ±0.5 2 2.5 nA CMIR Common-Mode Voltage Range Guaranteed by CMRR 0 5 V CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 80 115 dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5V 90 80 115 dB AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ 275 275 500 V/mV VO = 0.5V to 4.5V, RL = 1kΩ 95 V/mV Output low, RL = 100kΩ 3 6 30 mV 130 175 225 mV VOUT Maximum Output Voltage Swing -600 -650 IS,OFF Supply Current, Enabled Supply Current, Disabled 2 600 650 0.7 Output low, RL = 1kΩ IS,ON ±20 µV µV/°C Output high, RL = 100kΩ 4.990 4.970 4.996 V Output high, RL = 1kΩ 4.800 4.750 4.880 V ISL28286, All channels enabled. 120 156 175 µA ISL28486, All channels enabled. 240 315 350 µA ISL28286, All channels disabled. 4 7 9 µA FN6312.1 June 28, 2007 ISL28286, ISL28486 Electrical Specifications PARAMETER V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) DESCRIPTION CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT ISC+ Short Circuit Sourcing Capability RL = 10Ω 29 23 31 mA ISC- Short Circuit Sinking Capability RL = 10Ω 24 19 26 mA VSUPPLY Supply Operating Range V+ to V- 2.4 VENH EN Pin High Level (ISL28286) VENL EN Pin Low Level (ISL28286 IENH EN Pin Input High Current (ISL28286) VEN = V+ IENL EN Pin Input Low Current (ISL28286) VEN = V- 5 2 V V 0.8 V 0.7 1.3 1.5 µA 0 0.1 µA AC SPECIFICATONS GBW Gain Bandwidth Product AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM 400 kHz en Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 4.5 µVP-P Input Noise Voltage Density fO = 1kHz 50 nV/√Hz in Input Noise Current Density fO = 1kHz 0.18 pA/√Hz CMRR @ 60Hz Input Common Mode Rejection Ratio VCM = 1VP-P, RL = 10kΩ to VCM 78 dB PSRR+ @ 120Hz Power Supply Rejection Ratio (V+) V+, V- = ±12V and ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM -105 dB PSRR- @ 120Hz Power Supply Rejection Ratio (V-) V+, V- = ±12V and ±2.5V VSOURCE = 1VP-P, RL = 10kΩ to VCM -73 dB TRANSIENT RESPONSE ±0.10 ±0.09 ±0.17 ±0.20 ±0.25 V/µs SR Slew Rate tEN Enable to Output Turn-on Delay Time, 10% EN to 10% VOUT, (ISL28286) VEN = 5V to 0V, AV = -1, Rg = Rf = RL = 1k to VCM 2 µs Enable to Output Turn-off Delay Time, 10% EN to 10% VOUT, (ISL28286) VEN = 0V to 5V, AV = -1, Rg = Rf = RL = 1k to VCM 0.1 µs NOTE: 1. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested. 3 FN6312.1 June 28, 2007 ISL28286, ISL28486 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open 45 +1 V+, V- = ±2.5V RL = 1k GAIN (dB) -2 V+, V- = ±2.5V RL = 10k -3 35 V+, V- = ±1.2V RL = 10k 30 GAIN (dB) -1 40 V+, V- = ±1.2V RL = 1k -4 VOUT = 50mVp-p AV = 1 CL = 3pF RF = 0/RG = INF -5 -6 -7 -8 1k 10k 100k FREQUENCY (Hz) 1M 5M 25 V+, V- = ±1.25V 20 AV = 100 V+, V- = ±2.5V 15 RL = 10kΩ CL = 2.7pF 10 R /R = 99.02 F G V+, V- = ±1.0V RF = 221kΩ 5 RG = 2.23kΩ 0 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE 120 80 100 80 40 80 200 150 0 -40 0 PHASE -80 -40 -80 1 100 10 10k 1k 100k 1M 50 40 0 20 GAIN -20 10 -120 10M -100 100 0 10 100 PSRR + 80 CMRR(dB) PSRR (dB) V+ = 5VDC VSOURCE = 1VP-P RL = 100kΩ AV = +1 90 PSRR - 70 60 50 40 V+ = 5VDC VSOURCE = 1VP-P RL = 100kΩ AV = +1 100 -150 1M FREQUENCY (Hz) 80 70 20 10 100k FIGURE 4. AVOL vs FREQUENCY @ 1kΩ LOAD 120 110 40 30 10k 1k FREQUENCY (Hz) 60 50 -50 0 FIGURE 3. AVOL vs FREQUENCY @ 100kΩ LOAD 100 90 100 60 GAIN (dB) 40 PHASE (°) GAIN (dB) PHASE GAIN PHASE (°) 0 30 20 1k 10k 100k FREQUENCY (Hz) FIGURE 5. PSRR vs FREQUENCY 4 1M 10 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 6. CMRR vs FREQUENCY FN6312.1 June 28, 2007 ISL28286, ISL28486 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open 1k VOLTAGE NOISE (nV/√Hz) 10.00 CURRENT NOISE (pA/√Hz) (Continued) 1.00 0.10 100 10 1 0.01 1 10 100 1k 10k 1 100k 10 1k 100 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 7. CURRENT NOISE vs FREQUENCY FIGURE 8. VOLTAGE NOISE vs FREQUENCY VOLTAGE NOISE (1µV/DIV) 2.56 VIN 2.54 VOLTS (V) 2.52 VOUT 2.50 2.48 V+ = 5VDC VOUT = 0.1VP-P RL = 500Ω AV = +1 2.46 4.5µVP-P 2.44 2.42 0 TIME (1s/DIV) FIGURE 9. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE 2 4 6 8 10 12 TIME (µs) 14 16 18 20 FIGURE 10. SMALL SIGNAL TRANSIENT RESPONSE 5.0 VIN 3.0 2.0 1V/DIV VOLTS (V) V+ = 5VDC VOUT = 0.1VP-P RL = 500Ω AV = -2 AV = -1 VIN = 200mVP-P V+ = 5V EN INPUT VOUT 4.0 0 1.0 VOUT 0 100 200 300 TIME (µs) 400 500 FIGURE 11. LARGE SIGNAL TRANSIENT RESPONSE 5 VOUT 0.1V/DIV VIN 0 0 10µs/DIV FIGURE 12. ENABLE TO OUTPUT DELAY TIME FN6312.1 June 28, 2007 ISL28286, ISL28486 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open (Continued) 80 60 60 40 40 I-BIAS (nA) 100 80 VOS (μV) 100 20 0 -20 -40 -80 -100 -1 0 0 -20 -40 V+ = 5V RL = OPEN RF = 100k, RG = 100 AV = +1000 -60 20 V+ = 5V RL = OPEN RF= 100k, RG = 100 AV = +1000 -60 -80 1 2 3 VCM (V) 4 5 -100 -1 6 FIGURE 13. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0 1 2 3 VCM (V) 4 5 6 FIGURE 14. INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE 155 340 320 115 300 MAX CURRENT (μA) SUPPLY CURRENT (µA) N = 1150 135 95 75 55 35 2.0 280 MEDIAN 260 240 MIN 220 2.5 3.0 3.5 4.0 4.5 5.0 200 -40 5.5 -20 0 SUPPLY VOLTAGE (V) FIGURE 15. ISL28286 SUPPLY CURRENT vs SUPPLY VOLTAGE 4.8 80 100 120 N = 1150 600 VOS (μV) 4.2 MAX 4.0 MIN 3.8 200 MEDIAN 0 -200 3.6 -400 3.4 -600 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 17. ISL28286 SUPPLY CURRENT vs TEMPERATURE, V+, V- = ±2.5V DISABLED, RL = INF 6 MAX 400 MEDIAN -20 60 800 N = 12 4.4 CURRENT (μA) 40 FIGURE 16. ISL28486 SUPPLY CURRENT vs TEMPERATURE, V+, V- = ±2.5V ENABLED, RL = INF 4.6 3.2 -40 20 TEMPERATURE (°C) -800 -40 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 18. VOS vs TEMPERATURE, VIN = 0V, V+, V- = ±2.5V FN6312.1 June 28, 2007 ISL28286, ISL28486 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open 800 2.5 N = 1150 MAX IBIAS + (nA) 200 MEDIAN 0 -200 -400 MAX 1.5 400 VOS (μV) N = 1150 2.0 600 1.0 MEDIAN 0.5 0.0 -0.5 MIN -1.0 MIN -600 -800 -40 (Continued) -1.5 -20 0 20 40 60 80 100 -2.0 -40 120 -20 0 TEMPERATURE (°C) FIGURE 19. VOS vs TEMPERATURE, VIN = 0V, V+, V- = ±1.2V 3.0 2.5 2.5 IBIAS + (nA) IBIAS - (nA) 100 120 MAX 1.5 MEDIAN 0.5 0.0 -0.5 MEDIAN 1.0 0.5 0.0 -0.5 -1.0 MIN -1.5 -1.0 -2.0 -1.5 -20 0 20 40 60 80 100 -2.0 -40 120 MIN -20 0 TEMPERATURE (°C) 40 2.5 2.0 2.5 80 100 120 N = 1150 1.5 MAX MAX 1.0 1.5 1.0 60 FIGURE 22. IBIAS + vs TEMPERATURE, V+, V- = ±1.2V N = 1150 2.0 20 TEMPERATURE (°C) FIGURE 21. IBIAS - vs TEMPERATURE, V+, V- = ±2.5V MEDIAN IOS (nA) IBIAS - (nA) 80 N = 1150 2.0 MAX 1.0 0.5 0.0 0.5 MEDIAN 0.0 -0.5 -1.0 -0.5 MIN -1.0 MIN -1.5 -1.5 -2.0 -40 60 3.0 1.5 3.0 40 FIGURE 20. IBIAS + vs TEMPERATURE, V+, V- = ±2.5V N = 1150 2.0 -2.5 -40 20 TEMPERATURE (°C) -2.0 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 23. IBIAS - vs TEMPERATURE, V+, V- = ±1.2V 7 -2.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 24. IOS vs TEMPERATURE, V+, V- = ±2.5V FN6312.1 June 28, 2007 ISL28286, ISL28486 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open 1070 150 N = 1150 N = 1150 970 130 MAX MAX AVOL (V/mV) 870 AVOL (V/mV) (Continued) 770 670 MEDIAN 570 110 90 MEDIAN 70 470 MIN 50 370 MIN 270 -40 -20 0 20 40 60 80 100 30 120 -40 -20 0 20 FIGURE 25. AVOL vs TEMPERATURE, V+, V- = ±2.5V, RL = 100k N = 1150 MAX 130 100 120 MAX 130 120 120 PSRR (dB) CMRR (dB) 80 140 N = 1150 MEDIAN 110 100 MEDIAN 110 100 MIN MIN 90 90 80 -40 -20 0 20 40 60 80 100 80 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 27. CMRR vs TEMPERATURE, VCM = +2.5V TO -2.5V, V+, V- = ±2.5V FIGURE 28. PSRR vs TEMPERATURE, V+, V- = ±1.2V TO ±2.75V 4.9972 4.91 N = 1150 N = 1150 4.9970 4.90 4.9968 MAX 4.88 MAX VOUT (V) 4.89 VOUT (V) 60 FIGURE 26. AVOL vs TEMPERATURE, V+, V- = ±2.5V, RL = 1k 140 MEDIAN 4.87 4.9966 MEDIAN 4.9964 4.9962 MIN MIN 4.9960 4.86 4.85 40 TEMPERATURE (°C) TEMPERATURE (°C) 4.9958 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 29. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V, RL = 1k 8 4.9956 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 30. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V, RL = 100k FN6312.1 June 28, 2007 ISL28286, ISL28486 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open 3.0 170 N = 1150 2.6 150 MAX 140 VOUT (mV) VOUT (mV) N = 1150 2.8 160 MEDIAN 130 MIN 120 MAX 2.4 MEDIAN 2.2 2.0 MIN 1.8 110 1.6 100 90 (Continued) 1.4 -40 -20 0 20 40 60 80 100 1.2 120 -40 -20 0 41 N = 1150 39 37 MAX 35 33 MEDIAN 31 29 MIN 27 -40 -20 0 20 40 60 80 100 120 80 100 120 N = 1150 -23 MAX -25 -27 MEDIAN MIN -29 -31 -33 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 34. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE, VIN = -2.55V, RL = 10, V+, V- = ±2.5V 0.24 0.24 N = 1150 N = 1150 0.22 - SLEW RATE (V/µs) 0.22 + SLEW RATE (V/µs) 60 -21 TEMPERATURE (°C) FIGURE 33. + OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE, VIN = -2.55V, RL = 10, V+, V- = ±2.5V 0.20 MAX 0.18 0.16 MEDIAN MIN 0.14 0.20 MAX 0.18 0.16 MEDIAN MIN 0.14 0.12 0.12 0.10 40 FIGURE 32. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V, RL = 100k + OUTPUT SHORT CIRCUIT CURRENT (mA) + OUTPUT SHORT CIRCUIT CURRENT (mA) FIGURE 31. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V, RL = 1k 25 20 TEMPERATURE (°C) TEMPERATURE (°C) -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 35. + SLEW RATE vs TEMPERATURE, VOUT = 1.5V, AV = +2 9 0.10 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 36. - SLEW RATE vs TEMPERATURE, VOUT = 1.5V, AV = +2 FN6312.1 June 28, 2007 ISL28286, ISL28486 Pin Descriptions ISL28286 ISL28486 (10 LD MSOP) (16 LD QSOP) PIN NAME EQUIVALENT CIRCUIT 1 3 IN+_A Circuit 1 Amplifier A non-inverting input EN_A Circuit 2 Amplifier A enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. V- Circuit 4 Negative power supply EN_B Circuit 2 Amplifier B enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. 2 3 DESCRIPTION 13 4 5 5 IN+_B Circuit 1 Amplifier B non-inverting input 6 6 IN-_B Circuit 1 Amplifier B inverting input 7 7 OUT_B Circuit 3 Amplifier B output 8 4 V+ Circuit 4 Positive power supply 9 1 OUT_A Circuit 3 Amplifier A output 10 2 IN-_A Circuit 1 Amplifier A inverting input 10 OUT_C Circuit 3 Amplifier C output 11 IN-_C Circuit 1 Amplifier C inverting input 12 IN+_C Circuit 1 Amplifier C non-inverting input 14 IN+_D Circuit 1 Amplifier D non-inverting input 15 IN-_D Circuit 1 Amplifier D inverting input 16 OUT_D Circuit 3 Amplifier D output 8, 9 NC - V+ V+ IN- IN+ V+ LOGIC PIN CAPACITIVELY COUPLED ESD CLAMP V- VCIRCUIT 2 10 V+ OUT V- CIRCUIT 1 No internal connection VCIRCUIT 3 CIRCUIT 4 FN6312.1 June 28, 2007 ISL28286, ISL28486 Applications Information Introduction The ISL28286 and ISL28486 are dual and quad BiCMOS rail-to-rail input, output (RRIO) micropower precision operational amplifiers. These devices are designed to operate from a single supply (2.4V to 5.0V) or dual supplies (±1.2V to ±2.5V) while drawing only 120μA (ISL28286) of supply current. This combination of low power and precision performance makes these devices suitable for solar and battery power applications. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28286 and ISL28486 achieve input rail-to-rail without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire commonmode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically down to the negative rail to 10% higher than the V+ rail (0.5V higher than V+ when V+ equals 5V). direction. Both parts with a 100kΩ load will swing to within 4mV of the supply rails. Enable/Disable Feature The ISL28286 offers two EN pins (EN_A and EN_B) which disable the op amp when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 4µA. By disabling the part, multiple parts can be connected together as a MUX. The outputs are tied together in parallel and a channel can be selected by the EN pins. The EN pins also have an internal pull-down. If left open, the EN pins will pull to the negative rail and the op amp will be enabled by default. Using Only One Channel The ISL28286 and ISL28486 are dual and quad channel op amps. If the application only requires one channel when using the ISL28286 or less than 4 channels when using the ISL28486, the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 37). + 1/2 ISL28286 1/4 ISL28486 FIGURE 37. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Input Protection All input terminals have internal ESD protection diodes to positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. Both parts have additional back-to-back diodes across the input terminals. If overdriving the inputs is necessary, the external input current must never exceed 5mA. External series resistors may be used as an external protection to limit excessive external voltage and current from damaging the inputs. Input Bias Current Compensation The ISL28286 and ISL28486 contain an input bias cancellation circuit which reduces the bias currents down to a typical of 500pA while maintaining an excellent bandwidth for a micro-power operational amplifier. The input stage transistors are still biased with adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. Rail-to-Rail Output A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive 11 Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28286 and ISL28486, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 38 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. FN6312.1 June 28, 2007 ISL28286, ISL28486 where: V+ HIGH IMPEDANCE INPUT • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) IN • PDMAX for each amplifier can be calculated as follows: V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL (EQ. 2) where: FIGURE 38. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER • TMAX = Maximum ambient temperature Current Limiting • θJA = Thermal resistance of the package The ISL28286 and ISL28486 have no internal currentlimiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. • PDMAX = Maximum power dissipation of 1 amplifier Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related as follows: T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) 12 • VS = Supply voltage (Magnitude of V+ and V-) • IMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance (EQ. 1) FN6312.1 June 28, 2007 ISL28286, ISL28486 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 13 FN6312.1 June 28, 2007 ISL28286, ISL28486 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6312.1 June 28, 2007