TI ISO3086TDW

ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
Isolated 5V RS-485 Transceiver With Integrated Transformer Driver
Check for Samples: ISO3086T
FEATURES
1
•
•
•
•
•
•
•
•
•
•
3000 VRMS / 4242 VPK Isolation
Bus-Pin ESD Protection
– 11 kV HBM Between Bus-Pins and GND2
– 6 kV HBM Between Bus-Pins and GND1
1/8 Unit Load – Up to 256 Nodes on a Bus
Designed for RS-485 and RS-422 Applications
Signaling Rates up to 20 Mbps
Thermal Shutdown Protection
Typical Efficiency > 60% (ILOAD = 100 mA) - see
SLUU469
Low Bus Capacitance 7 pF (Typ)
50 kV/µs Typical Transient Immunity
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
Approvals Pending
Fail-safe Receiver for Bus Open, Short, Idle
Logic Inputs are 5-V Tolerant
DW PACKAGE
D1
D2
1
16
2
15
GND1
VCC1
R
RE
DE
D
3
4
14
13
5
12
•
•
•
•
•
11
7
10
8
9
VCC2
GND2
A
B
Z
Y
NC
GND2
FUNCTION DIAGRAM
D1
D2
1
2 OSC
5
R
6
RE
7
DE
D
APPLICATIONS
6
8
GALVANIC ISOLATIO N
•
•
14
A
13
12
B
Z
11
Y
Isolated RS-485/RS-422 Interfaces
Factory Automation
Motor/Motion Control
HVAC and Building Automation Networks
Networked Security Stations
DESCRIPTION
The ISO3086T is an isolated differential line transceiver with integrated oscillator outputs that provide the primary
voltage for an isolation transformer. The device is a full-duplex differential line transceiver for RS-485 and
RS-422 applications that can easily be configured for half-duplex operation by connecting pin 11 to pin 14, and
pin 12 to pin 13.
These devices are ideal for long transmission lines since the ground loop is broken to allow for a much larger
common-mode voltage range. The symmetrical isolation barrier of the device is tested to provide 3000 VRMS or
4242 VPK of isolation for 1 minute per VDE between the bus-line transceiver and the logic-level interface.
Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can
cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and
duration. These isolated devices can significantly increase protection and reduce the risk of damage to
expensive control circuits.
The ISO3086T is specified for use from –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
X-FMR
4
8
3
2
7
6
1
5
LDO
D1
1
C4 C5
3
2
C1
IN
OUT
5
EN
C6
GND NC
1
D2
1
2
C2
Control
Circuitry
VCC2
D1
16
C3
D2
4 V
CC1
3
GND1
5
R
6
RE
7
DE
8
D
A
B
Z
Y
Isolated Supply to
other Components
14
13
12
RS-485 Bus
Interface
11
15
GND2
9, 10
ISO3086T
Figure 1. Typical Application Circuit (For Details See SLUU469)
PIN DESCRIPTIONS
NAME
PIN No.
FUNCTION
D1
1
Transformer Driver Terminal 1, Open Drain Output
D2
2
Transformer Driver Terminal 2, Open Drain Output
GND1
3
Logic-side Ground
VCC1
4
Logic-side Power Supply
R
5
Receiver Output
RE
6
Receiver Enable Input. This pin has complementary logic.
DE
7
Driver Enable Input
8
Driver Input
D
GND2
9, 15
Bus-side Ground. Both pins are internally connected.
NC
10
No Connect. This pin is not connected to any internal circuitry.
Y
11
Non-inverting Driver Output
Z
12
Inverting Driver Output
B
13
Inverting Receiver Input
A
14
Non-inverting Receiver Input
VCC2
16
Bus-side Power Supply
2
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VCC1, VCC2
Input supply voltage (2)
VA,VB,VY,VZ Voltage at any bus I/O terminal (A, B, Y, Z)
VD1,VD2
Voltage at D1, D2
V(TRANS)
Voltage input, transient pulse through 100Ω, see Figure 12 (A, B,Y, Z)
VI
Voltage input at D, DE or RE terminal
IO
Receiver output current
ID1, ID2
Transformer Driver Output Current
Human Body Model
ESD
Electrostatic
discharge
Machine Model
TJ
Maximum junction temperature
TSTG
Storage temperature
(2)
UNIT
V
–9 to 14
V
14
V
–50 to +50
V
–0.5 to 7
V
±10
mA
450
mA
Bus pins and
GND1
±6
kV
Bus pins and
GND2
±11
kV
±4
kV
±1.5
kV
All pins
Charged Device Model
(1)
JEDEC Standard 22, Test Method
A114-C.01
VALUE
–0.3 to 6
JEDEC Standard 22, Test Method
C101
All pins
±200
V
170
°C
–65 to 150
°C
ANSI/ESDS5.2-1996
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
3.3 V Operation
VCC1
Logic-side supply voltage
VCC2
Bus-side supply voltage
VI or VIC
Voltage at any bus terminal (separately or common-mode)
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
RL
Differential load resistance
5 V Operation
RE
D, DE
RE
MIN
TYP
MAX
3
3.3
3.6
4.5
5
5.5
4.5
5
5.5
V
–7
12
V
2
VCC1
0.7 VCC1
0
0.8
D, DE
A with respect to B
Dynamic
0.3 VCC1
–12
12
See Figure 15
54
Driver
UNIT
V
V
V
V
Ω
60
–60
60
–8
8
IO
Output Current
TA
Ambient temperature
–40
85
TJ
Operating junction temperature
–40
150
°C
1 / tUI
Signaling Rate
20
Mbps
Copyright © 2011, Texas Instruments Incorporated
Receiver
mA
°C
3
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
SUPPLY CURRENT and COMMON-MODE TRANSIENT IMMUNITY
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP MAX
VCC1 = 3.3 V ±10%
5
8
VCC1 = 5 V ±10%
7
12
RE = 0 V or VCC1, DE = 0 V (driver disabled), No load
10
15
RE = 0 V or VCC1, DE = VCC1 (driver enabled), D = 0 V or VCC1, No Load
10
15
ICC1 (1)
Logic-side quiescent
supply current
DE and RE = 0V or VCC1 (Driver and Receiver
Enabled or Disabled), D = 0 V or VCC1, No load
ICC2 (1)
Bus-side quiescent
supply current
CMTI
Common-mode
transient immunity
(1)
MIN
See Figure 13, VI = VCC1 or 0 V
25
50
UNIT
mA
mA
kV/µs
ICC1 and ICC2 are measured when device is connected to external power supplies, VCC1 and VCC2. In this case, D1 and D2 are open and
disconnected from external transformer.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 0 mA, no load
|VOD|
Differential output voltage magnitude
RL = 54 Ω (RS-485), See Figure 2
RL = 100 Ω (RS-422), See Figure 2
Vtest from –7 V to +12 V, SeeFigure 3
Δ|VOD|
Change in magnitude of the differential
output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode
output voltage
VOC(pp)
Peak-to-peak common-mode output voltage See Figure 4
II
Input current
IOZ
VY or VZ = 12V,
High-impedance state output current, Y or Z VCC2 = 0 V or 5 V, DE = 0 V
pin
VY or VZ = –7 V,
VCC2 = 0 V or 5 V, DE = 0 V
IOS (1)
(1)
TYP
MAX
3
4.3
VCC2
1.5
2.3
2
2.3
See Figure 2 and Figure 3
Figure 4
V
–0.2
0
0.2
V
1
2.6
3
V
0.1
V
10
µA
–0.1
0.5
–7 V ≤ VY or VZ ≤ 12 V
UNIT
1.5
–10
D, DE, VI at 0 V or VCC1
Short-circuit output current
MIN
Other bus pin
at 0 V
Other bus pin
at 0 V
V
1
µA
–1
–250
250
mA
TYP
MAX
UNIT
25
45
1
7.5
This device has thermal shutdown and output current limiting features to protect in short-circuit fault condition.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tPLH, tPHL
Propagation delay
PWD (1)
Pulse width distortion (|tPHL – tPLH|)
tr, tf
Differential output signal rise time and fall time
7
15
tPZH,
tPHZ
Propagation delay, high-impedance-to-high-level output,
Propagation delay, high-level-to-high-impedance output
See Figure 6
DE at 0 V
25
55
ns
tPLZ,
tPZL
Propagation delay, low-level to high-impedance output,
Propagation delay, high-impedance to low-level output
See Figure 7,
DE at 0 V
25
55
ns
(1)
4
See Figure 5
ns
Also known as pulse skew
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT(+)
Positive-going input threshold voltage
IO = -8 mA
VIT(–)
Negative-going input threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
MIN
TYP
MAX
UNIT
–85
–10
mV
–200
–115
mV
30
mV
VCC1–0.4
3.1
4
4.8
VOH
High-level output voltage
VID = 200 mV, IO = –8 mA,
See Figure 8
VCC1 = 3.3 V
VOL
Low-level output voltage
VID = 200 mV, IO = 8 mA,
See Figure 8
VCC1 = 3.3 V
0.15
0.4
VCC1 = 5 V
0.15
0.4
IO(Z)
High-impedance state output current
VO = 0 or VCC1, RE = VCC1
40
100
60
130
VCC1 = 5 V
–1
VA or VB = 12 V
VA or VB = 12 V, VCC2 = 0
V
Other input
at 0 V
1
IA, IB
Bus input current
IIH
High-level input current, RE
VIH = 2. V
–10
10
IIL
Low-level input current, RE
VIL = 0.8 V
–10
10
RID
Differential input resistance
A, B
CID
Differential input capacitance
VI = 0.4 sin (4E6πt) + 0.5 V
VA or VB = –7 V
VA or VB = –7 V, VCC2 = 0
–100
–40
–100
–30
96
V
µA
µA
µA
kΩ
7
pF
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
tPLH, tPHL
Propagation delay
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr, tr
Output signal rise and fall time
tPHZ,
tPZH
Propagation delay, high-level to high-impedance output
Propagation delay, high-impedance to high-level output
See Figure 10, DE at 0 V
11
22
tPLZ,
tPZL
Propagation delay, low-level to high-impedance output
Propagation delay, high-impedance to low-level output
See Figure 11, DE at 0 V
11
22
See Figure 9
103
125
3
15
UNIT
ns
1
ns
TRANSFORMER DRIVER CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
fOSC
RON
Oscillator frequency
Switch on resistance
tr_D
D1, D2 output rise time
tf_D
D1, D2 output fall time
fSt
Startup frequency
tBBM
(1)
Break before make time delay
MIN
TYP MAX
VCC1 = 5V ± 10%, D1 and D2 connected to
transformer
TEST CONDITIONS
350
450
610
VCC1 = 3.3V ± 10%, D1 and D2 connected to
transformer
300
400
550
1
2.5
D1 and D2 connected to 50Ω pull-up resistors
VCC1 = 5V ± 10%, see Figure 14, (1)
VCC1 = 3.3V ± 10%, see Figure 14,
VCC1 = 5V ± 10%, see Figure 14,
(1)
VCC1 = 3.3V ± 10%, see Figure 14,
(1)
VCC1 = 2.4 V, D1 and D2 connected to transformer
VCC1 = 5V ± 10%, see Figure 14,
(1)
VCC1 = 3.3V ± 10%, see Figure 14,
kHz
80
(1)
(1)
UNIT
70
55
80
350
38
140
Ω
ns
ns
kHz
ns
D1 and D2 connected to 50Ω pull-up resistors
Copyright © 2011, Texas Instruments Incorporated
5
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC1
VCC2
IY
DE
0 or
VCC1
Y
RL
VOD
D
D
0 or 3 V
.
Z
GND1
375 W
DE
Y
II
+
VOD
-
Z
60 W
IZ
GND2
VI
375 W
GND2
VY
VZ
GND1
VTEST =
-7 V to 12 V
GND2
Figure 2. Driver VOD Test and Current Definitions
VCC1
IY
DE
27 W
±1%
Y
II
Input
D
VOD
Z
GND2
GND1
VI
27 W
±1%
IZ
VZ
GND1
Figure 3. Driver VOD With Common-Mode Loading
Test Circuit
Y
VY
Z
VZ
VOC
VOC(SS)
VOC(p-p)
VOC
VY
Input Generator: PRR= 100 kHz, 50 % duty
cycle, t r < 6ns , t f <6 ns , ZO = 50 W
GND2
Figure 4. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
3V
DE
VCC1
Y
D
Input
Generator
VI
Z
VOD
RL= 54 W
±1%
50%
VI
CL = 50pF
± 20%
tpLH
50W
C L includes fixture and
instrumentation capacitance
GND1
Generator: PRR = 100 kHz, 50 % duty cycle,
t r < 6ns , t f <6 ns , ZO = 50W
50%
tpHL
90%
50 %
10 %
VOD
VOD(H)
90%
tr
tf
50 %
10%
VOD(L)
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
Y
D
S1
3V Y
0V Z
S1
D
50%
0V
50 W
GND1
Generator: PRR = 50 kHz, 50% duty
cycle, tr <6ns, tf <6ns, ZO = 50 W
tpZH
RL = 110 W
±1 %
C L = 50 pF ± 20 %
VI
50%
VI
Z
DE
Input
Generator
3V
VO
CL includes fixture and
instrumentation
capacitance
90%
VO
VOH
50%
tpHZ
»0V
GND2
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
6
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VCC2
3V
Y
D
S1
3V Y
0V Z
R L = 110 W
± 1%
VO
S1
D
Generator: PRR=50 kHz, 50% duty cycle,
t r < 6ns, t f < 6ns, ZO = 50 W
VI
50%
0V
tpZL
Z
DE
tpLZ
C L = 50 pF ± 20 %
Input
Generator
50%
VI
VO
CL includes fixture and
instrumentation
capacitance
50 W
GND1
VCC2
50%
10%
V OL
GND2
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
A
IA
R
VA
B
VIC
VA + V B
IO
VID
VB
VO
IB
2
Figure 8. Receiver Voltage and Current Definitions
3V
A
Input
Generator
VI
50 W
1.5 V
B
0V
CL includes fixture and
instrumentation capacitance
Generator: PRR =100 kHz , 50 % duty cycle,
t < 6ns , t < 6ns , Z = 50 W
O
r
f
50 %
tpHL
tpLH
CL = 15 pF
± 20 %
RE
50 %
VI
R VO
90 %
50 %
10 %
50 %
VO
tf
tr
V OH
V OL
Figure 9. Receiver Switching Test Circuit and Waveforms
V CC
A
1.5 V
R
B
0 V
RE
VO
1 k W ±1%
VI
VI
50 %
50 %
C L = 15 pF ± 20 %
CL includes fixture
and instrumentation
capacitance
Input
Generator
3V
S1
0V
tpHZ
tpZH
VO
90%
VOH
50 %
50 W
»0V
Generator: PRR =100 kHz , 50 % duty cycle ,
t r<6ns , t f<6ns , Z O = 50 W
Figure 10. Receiver Enable Test Circuit and Waveforms, Data Output High
Copyright © 2011, Texas Instruments Incorporated
7
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
V CC
A
0 V
R
VO
B
1.5 V
1 kW ± 1 %
3V
S1
VI
C L = 15 pF ± 20 %
RE
50%
50%
0V
CL includes fixture
and instrumentation
capacitance
tpLZ
tpZL
VCC
Input
Generator
VI
50 W
50%
VO
10%
Generator : PRR =100 kHz , 50 % duty cycle ,
tr <6ns ,t f <6ns , Z O = 50 W
VOL
Figure 11. Receiver Enable Test Circuit and Waveforms, Data Output Low
0 V or 3 V
DE
A
Y
D
R
Z
100 W
±1%
+
–
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
B
100 W
±1%
RE
0 V or 3 V
+
–
Figure 12. Transient Over-Voltage Test Circuit
C = 0.1 m F
± 1%
2.0 V
V CC2
V CC 1
A
C = 0.1 m F ± 1%
DE
GND 1
D
54 W
S1
V OH or V OL
B
Y
0.8 V
1.5 V or 0 V
R
54 W
RE
V OH or V OL
Z
1 kW
0 V or 1.5 V
GND1
GND2
C L = 15 pF
( includes probe and
jig capacitance
)
V TEST
Figure 13. Common-Mode Transient Immunity Test Circuit
8
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
tf_D
tr_D
90%
D1
10%
tBBM
tBBM
90 %
D2
10 %
tf_D
tr_D
Figure 14. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs
Copyright © 2011, Texas Instruments Incorporated
9
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
DEVICE INFORMATION
1
VID - Differential Input Voltage - pk
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10 12 14
Signaling Rate - Mbps
16
18
20
Figure 15. ISO3086T Recommended Minimum Differential Input Voltage vs Signaling Rate
Table 1. Driver Function Table (1)
(1)
INPUT
ENABLE
(D)
(DE)
Y
OUTPUTS
H
H
H
L
L
H
L
H
X
L
hi-Z
hi-Z
X
OPEN
hi-Z
hi-Z
OPEN
H
H
L
Z
H = High Level, L= Low Level, X = Don’t Care, hi-Z = High Impedance (off)
Table 2. Receiver Function Table (1)
(1)
10
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
(R)
–0.01 V ≤ VID
L
H
–0.2 V < VID –0.01 V
L
?
VID ≤ –0.2 V
L
L
X
H
hi-Z
X
OPEN
hi-Z
Open circuit
L
H
Short Circuit
L
H
Idle (terminated) bus
L
H
H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off), ? = Indeterminate
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
IEC INSULATION AND SAFETY RELATED SPECIFICATIONS FOR 16-DW PACKAGE
over recommended operating conditions (unless otherwise noted)
PARAMETER
(1)
)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (Clearance
Shortest terminal to terminal distance through air
8.3
mm
L(I02)
Minimum external tracking (Creepage (1))
Shortest terminal to terminal distance across the
package surface
8.1
mm
CTI
Tracking resistance(Comparative Tracking
Index)
DIN IEC 60112 / VDE 0303 Part 1
400
V
Minimum Internal Gap (Internal Clearance)
Distance through the insulation
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each
side of the barrier tied together creating a
two-terminal device
CIO
Barrier capacitance Input to output
CI
Input capacitance to ground
(1)
0.008
mm
>1012
Ω
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
2
pF
VIO = 0.4 sin (2πft), f = 1 MHz
2
pF
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques
shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
Installation classification
TEST CONDITIONS
Material group
SPECIFICATION
II
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
Rated mains voltage ≤ 400 VRMS
I-II
IEC 60747-5-2 INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
Maximum working insulation voltage
VPR
Input to output test voltage
TEST CONDITIONS
SPECIFICATION
UNIT
566
VPK
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s,
Partial discharge < 5 pC
1062
VPK
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial discharge < 5pC
906
After Input/Output Safety Test Subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
4242
VPK
VIOTM
Maximum transient overvoltage
t = 60 s
VIOSM
Maximum surge voltage
Tested per IEC 60065 (Qualification Test)
4242
VPK
RS
Insulation resistance
VIO = 500 V at TS
> 109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Copyright © 2011, Texas Instruments Incorporated
11
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
REGULATORY INFORMATION
VDE
UL
Certified according to DIN EN / IEC 60747-5-2 (VDE 0884 Part 2)
Recognized under 1577 Component Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4242 VPK
Maximum Surge Voltage, 4242 VPK
Maximum Working Voltage, 566 VPK
Single / Basic Isolation Voltage, 2500 VRMS (1)
File Number: 40016131 (Approval Pending)
File Number: E181974 (Approval Pending)
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply. Without current limiting, sufficient power is
dissipated to overheat the die; and, damage the isolation barrier—potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
TS
Maximum case temperature
DW-16
MIN
θJA = 80.5°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
TYP
MAX
UNIT
327
mA
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed on a High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
THERMAL INFORMATION
ISO3086T
THERMAL METRIC
(1)
DW
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance
80.5
θJC(TOP)
Junction-to-case(top) thermal resistance
43.8
θJB
Junction-to-board thermal resistance
49.7
ψJT
Junction-to-top characterization parameter
13.8
ψJB
Junction-to-board characterization parameter
41.4
θJC(BOTTOM)
Junction-to-case(bottom) thermal resistance
n/a
PD (2)
VCC1 = VCC2 = 5.5V, TJ = 150°C, RL = 54Ω, CL = 50pF (Driver), CL = 15pF
(Receiver), Input a 10 MHz 50% duty cycle square wave to Driver and Receiver
490
(1)
(2)
12
°C/W
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
PD = Maximum device power dissipation
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
350
VCC1 = VCC2 = 5.5 V
Safety Limiting Current - mA
300
250
200
150
100
50
0
0
50
100
150
TC - Case Temperature - °C
200
Figure 16. DW-16 θJC Thermal Derating Curve per IEC 60747-5-2
Copyright © 2011, Texas Instruments Incorporated
13
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
EQUIVALENT CIRCUIT SCHEMATICS
B Input
A Input
VCC 2
VCC 2
16V
Input
36 kW
16V
36 kW
180 kW
180 k W
Input
16V
36 k W
16V
R Output
36 kW
Y and Z Outputs
VCC 1
VCC 2
16V
4W
Output
output
6 .5 W
14
16V
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
DE Input
D, RE Input
VCC 1
VCC 1
VCC 1
VCC 1
VCC 1
1 MW
input
500 W
input
500 W
1 MW
Copyright © 2011, Texas Instruments Incorporated
15
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SIGNALING RATE (NO LOAD)
SUPPLY CURRENT
vs
SIGNALING RATE (WITH LOAD)
25
60
No Load
TA = 25°C,
16
PRBS Data 2 - 1
ICC2 @ 5 V
50
ICC2 @ 5 V
ICC - Supply Current - mA
ICC - Supply Current - mA
20
15
10
ICC1 @ 5 V
5
5
10
15
Signaling Rate - Mbps
30
20
20
5
10
15
Signaling Rate - Mbps
Figure 17.
Figure 18.
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
20
34
VCC1 = VCC2 = 5 V,
RL = 54 W,
CL = 50 pF
26
24
32
Driver Propagation Delay - ns
Driver Propagation Delay - ns
ICC1 @ 3.3 V
0
0
30
28
ICC1 @ 5 V
10
ICC1 @ 3.3 V
0
0
Driver: RL = 54 W, CL = 50 pF,
Receiver: CL = 15 pF,
TA = 25°C,
16
PRBS Data 2 - 1
40
tPHL
tPLH
VCC1 = 3.3 V,
VCC2 = 5 V,
RL = 54 W,
CL = 50 pF
30
28
26
tPHL
tPLH
24
22
22
20
-40
-15
10
35
60
TA - Free-Air Temperature - °C
Figure 19.
16
85
20
-40
-15
10
35
60
TA - Free-Air Temperature - °C
85
Figure 20.
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RECEIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
RECEIVER PROPAGATION
vs
FREE-AIR TEMPERATURE
105
110
Reveiver Propagation Delay - ns
104
Reveiver Propagation Delay - ns
VCC1 = 3.3 V,
VCC2 = 5 V,
CL = 15 pF
VCC1 = VCC2 = 5 V,
CL = 15 pF
103
102
tPHL
101
100
tPLH
99
108
106
tPHL
104
tPLH
102
98
97
-40
10
-15
10
35
60
TA - Free-Air Temperature - °C
100
-40
85
Figure 21.
Figure 22.
DRIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
DRIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
10
VCC1 = VCC2 = 5 V,
9.5
9
Driver Rise, Fall Time - ns
Driver Rise, Fall Time - ns
9.5 RL = 54 W,
CL = 50 pF
9
8.5
8
7.5
7
tr
tf
6.5
7
Copyright © 2011, Texas Instruments Incorporated
tr
tf
6.5
5.5
Figure 23.
RL = 54 W,
CL = 50 pF
7.5
5.5
85
VCC1 = 3.3 V,
VCC2 = 5 V,
8
6
-15
10
35
60
TA - Free-Air Temperature - °C
85
8.5
6
5
-40
-15
10
35
60
TA - Free-Air Temperature - °C
5
-40
-15
10
35
60
TA - Free-Air Temperature - °C
85
Figure 24.
17
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RECEIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
RECEIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
1200
1400
VCC1 = VCC2 = 5 V,
1300 C = 15 pF
L
1100
Receiver Rise, Fall Time - ps
Receiver Rise, Fall Time - ps
1200
tf
1100
1000
900
800
tr
700
VCC1 = 3.3 V,
VCC2 = 5 V,
CL = 15 pF
1000
600
tf
900
tr
800
700
500
400
-40
-15
10
35
60
TA - Free-Air Temperature - °C
600
-40
85
Figure 25.
Figure 26.
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
LOAD CURRENT
RECEIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3.5
3
TA = 25°C,
VCC1 = 5 V
-90
VCC2 = 5 V
-80
IO - Output Current - mA
VOD - Differential Output Voltage - V
85
-100
TA = 25°C
2.5
VCC2 = 5.5 V
2
100 W
1.5
VCC2 = 4.5 V
1
-70
-60
-50
-40
-30
-20
0.5
0
0
50 W
10
-10
20
30
40
50
IL - Load Current - mA
Figure 27.
18
-15
10
35
60
TA - Free-Air Temperature - °C
60
70
0
0
1
2
3
VO - Output Voltage - V
4
5
Figure 28.
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RECEIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
INPUT BIAS CURRENT
vs
BUS INPUT VOLTAGE
90
60
TA = 25°C,
VCC2 = 5 V
TA = 25°C,
80 VCC1 = 5 V
40
II - Bus Input Current - mA
IO - Output Current - mA
70
60
50
40
30
20
0
-20
20
-40
10
0
0
1
2
3
VO - Output Voltage - V
4
5
-60
-7
-4
-1
2
5
8
VI - Bus Input Voltage - V
Figure 29.
11
Figure 30.
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.1
VCC2 = 5 V,
VOD - Differential Output Voltage - V
RL = 54 W
2.08
2.06
2.04
2.02
2
1.98
-40
Copyright © 2011, Texas Instruments Incorporated
-15
10
35
60
TA - Free-Air Temperature - °C
Figure 31.
85
19
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
REFERENCE DESIGN
ISO3086T Reference design (SLUU469) and miniature evaluation boards are available.
TRANSIENT VOLTAGES
Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation and the transient ratings of the ISO3086T are sufficient for all but the most
severe installations. However, some equipment manufacturers use their ESD generators to test transient
susceptibility of their equipment and can easily exceed insulation ratings. ESD generators simulate static
discharges that may occur during device or equipment handling with low-energy but very high voltage transients.
Figure 32 models the ISO3086T bus IO connected to a noise generator. CIN and RIN is the device and any other
stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and
resistance between GND1 and GND2 of the ISO308x plus those of any other insulation (transformer, etc.), and
we assume stray inductance negligible. From this model, the voltage at the isolated bus return is
Z ISO
vGND2 = vN
ZISO + ZIN and will always be less than 16 V from V . If the ISO3086 are tested as a stand-alone
N
device, RIN= 6 × 104Ω, CIN= 16 × 10-12 F, RISO= 109Ω and CISO= 10-12 F.
spacer for space between the paragraphs
Note from Figure 32 that the resistor ratio determines
the voltage ratio at low frequency and it is the inverse
capacitance ratio at high frequency. In the
stand-alone
case
and
for
low
frequency,
spacer
spacer
A, B, Y, or Z
vGND2
RISO
109
=
=
vN
RISO + RIN
109 + 6 ´ 104
CIN
or essentially all of noise appears across the barrier.
At very high frequency,
v GND2
vN
=
1
CISO
1
CISO
+
RIN
VN
1
CIN
=
1+
1
=
CISO
CIN
1
1+
1
16
16 V
Bus Return (GND2)
= 0.94
CISO
RISO
and 94% of VN appears across the barrier. As long as
RISO is greater than RIN and CISO is less than CIN,
most of transient noise appears across the isolation
barrier, as it should.
We recommend the reader not test equipment
transient susceptibility with ESD generators or
consider product claims of ESD ratings above the
barrier transient ratings of an isolated interface. ESD
is best managed through recessing or covering
connector pins in a conductive connector shell and
installer training.
20
System Ground(GND1)
Figure 32. Noise Model
Copyright © 2011, Texas Instruments Incorporated
ISO3086T
SLLSE27C – JANUARY 2011 – REVISED JULY 2011
www.ti.com
REVISION HISTORY
Changes from Original (January 2011) to Revision A
Page
•
Changed the data sheet From: Preview To: Production ....................................................................................................... 1
•
Changed the Features and Description ................................................................................................................................ 1
•
Added Figure 1 Typical Application Circuit ........................................................................................................................... 2
Changes from Revision A (March 2011) to Revision B
•
Page
Deleted the MIN and MAX values from rows, tr_d, tf_D, and tBBM of the TRANSFORMER DRIVER
CHARACTERISTICS table ................................................................................................................................................... 5
Changes from Revision B (July 2011) to Revision C
Page
•
Added Note 1 to the TRANSFORMER DRIVER CHARACTERISTICS table ...................................................................... 5
•
Changed the TRANSFORMER DRIVER CHARACTERISTICS table - fSt Test Conditions From: .VCC1 = 9V To: VCC1
= 2.4 and Changed the TYP value From: 230 To: 350 kHz ................................................................................................. 5
Copyright © 2011, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
ISO3086TDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ISO3086TDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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