19-2648; Rev 0; 10/02 KIT ATION EVALU E L B AVAILA 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential and one single ended. The selected input is reproduced at five differential outputs. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9316A features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or board. For interfacing to differential HSTL and (LV)PECL signals, this device operates over a 3.0V to 5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. For differential (LV)ECL operation, this device operates with a -3.0V to -5.5V supply. Features ♦ Guaranteed 400mV Differential Output at 1.5GHz ♦ Selectable Single-Ended or Differential Input ♦ 130ps (max) Part-to-Part Skew at +25°C ♦ 20ps Output-to-Output Skew ♦ 365ps Propagation Delay ♦ Synchronous Output Enable/Disable ♦ On-Chip Reference for Single-Ended Inputs ♦ Input Biased to Low when Open ♦ Pin Compatible with MC100EL14 The MAX9316A is offered in a 20-pin wide SO package. Applications Precision Clock Distribution Ordering Information PART Low-Jitter Data Repeaters MAX9316AEWP TEMP RANGE PIN-PACKAGE -40°C to +85°C 20 Wide SO Data and Clock Drivers and Buffers Central-Office Backplane Clock Distribution DSLAM Backplane Base Stations Pin Configuration ATE MAX9316A TOP VIEW Typical Application Circuit Q0 2 RECEIVER MAX9316A ZO = 50Ω Q_ ZO = 50Ω Q_ 50Ω 50Ω 20 VCC QO 1 Q D 19 EN Q1 3 18 VCC Q1 4 17 N.C. Q2 5 16 SCLK Q2 6 15 CLK Q3 7 14 CLK Q3 8 13 VBB Q4 9 12 SEL Q4 10 11 VEE WIDE SO VTT = VCC - 2.0V Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9316A General Description MAX9316A 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS VCC - VEE...............................................................................6.0V Single-Ended Inputs (SCLK, SEL, EN, CLK, CLK) For VCC - VEE ≤ 4.2V.........................VEE - 0.3V to VCC + 0.3V For VCC - VEE > 4.2V ........................VEE - 4.2V to VCC + 0.3V CLK to CLK ........................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................±0.65mA Continuous Power Dissipation (TA = +70°C) Single-Layer PC Board 20-Pin Wide SO (derate 10mW/°C above +70°C) ......800mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin Wide SO… ...................................................+100°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC Board 20-Pin Wide SO… .....................................................+58°C/W Junction-to-Case Thermal Resistance 20-Pin Wide SO…. .....................................................+20°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (Inputs and Outputs) .........................2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN VCC 1.095 VCC VEE (VCC - VEE) > 4.2V VIL(MIN), VIH(MAX) TYP +85°C TYP MAX UNITS MAX MIN VCC 1.125 VCC VCC 1.125 VCC VCC 1.495 VEE VCC 1.495 VEE VCC 1.575 VCC 4.2 VCC 1.495 VCC 4.2 VCC 1.495 VCC 4.2 VCC 1.575 -300 +300 -300 +300 -300 +300 µA CLK connected to VBB, Figure 1 VCC 1.095 VCC VCC 1.125 VCC VCC 1.125 VCC V CLK connected to VBB, Figure 1 (VCC - VEE) ≤ 4.2V VEE VCC 1.495 VEE VCC 1.495 VEE VCC 1.575 CLK connected to VBB, Figure 1 (VCC - VEE) > 4.2V VCC 4.2 VCC 1.495 VCC 4.2 VCC 1.495 VCC 4.2 VCC 1.575 SINGLE-ENDED INPUTS (SCLK, SEL, EN) Input High Voltage VIH (VCC - VEE) ≤ 4.2 Input Low Voltage Input Current VIL IIN V V DIFFERENTIAL INPUTS (CLK, CLK) Single-Ended Input High Voltage Single-Ended Input Low Voltage 2 VIH VIL V High Voltage of Differential Input VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD VEE VCC 0.095 VEE VCC 0.095 VEE VCC 0.095 V _______________________________________________________________________________________ 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3) PARAMETER SYMBOL Differential Input Voltage CONDITIONS IIN TYP +25°C MAX MIN 0.095 3.0 VIH, VIL, VIHD, VILD -300 +300 VIHD VILD Input Current -40°C MIN TYP +85°C TYP MAX UNITS MAX MIN 0.095 3.0 0.095 3.0 V -300 +300 -300 +300 µA OUTPUTS (Q_, Q_) Single-Ended Output High Voltage VOH Figure 1 VCC 1.085 VCC - VCC 0.865 1.025 VCC - VCC 0.865 1.025 VCC 0.865 V Single-Ended Output Low Voltage VOL Figure 1 VCC 1.910 VCC - VCC 1.555 1.840 VCC - VCC 1.620 1.810 VCC 1.620 V VOH VOL Figure 1 550 910 mV VCC 1.22 V 43 mA Differential Output Voltage 910 550 910 550 REFERENCE (VBB) Reference Voltage Output (Note 4) VBB IBB = ±0.5mA VCC 1.40 VCC - VCC 1.19 1.40 VCC - VCC 1.22 1.48 POWER SUPPLY Supply Current (Note 5) IEE 30 40 32 40 34 _______________________________________________________________________________________ 3 MAX9316A DC ELECTRICAL CHARACTERISTICS (continued) MAX9316A 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs are loaded with 50Ω ±1% to VCC - 2V, input frequency ≤ 1.5GHz, input transition time = 125ps (20% to 80%), SEL = high or low, EN = low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3V, unless otherwise noted. Typical values are at VCC - VEE = 5.0V.) (Notes 1, 6) PARAMETER CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS CLK to Q_ Delay (Differential) tPLHD1, tPHLD1 Figure 2 290 400 310 440 300 520 ps SCLK to Q_ Delay tPLHD3, tPHLD3 VIL = VCC - 1.55V, VIH = VCC - 1.09V, Figure 3 290 400 310 440 300 520 ps Output-to-Output Skew (Note 7) tSKOO 50 ps Part-to-Part Skew (Note 8) tSKPP 220 ps 5 30 20 110 40 20 130 Added Random Jitter (Note 9) tRJ fIN = 1.5GHz clock 0.8 1.2 0.8 1.2 0.8 1.2 ps (RMS) Added Deterministic Jitter (Note 9) tDJ 1.5Gbps 2E23 - 1 PRBS pattern 50 70 50 70 50 70 PsP-P Switching Frequency fMAX (VOH - VOL) ≥ 400mV, Figure 2 1.5 Output Rise/Fall Time (20% to 80%) tR , t F Figure 2 80 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 4 SYMBOL 1.5 120 90 1.5 130 90 GHz 145 ps Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range. Use VBB only for inputs that are on the same device as the VBB reference. All pins are open except VCC and VEE. Guaranteed by design and characterization. Limits are set at ±6 sigma. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Device jitter added to a jitter-free input signal. _______________________________________________________________________________________ 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY SUPPLY CURRENT vs.TEMPERATURE 32 28 24 20 800 700 600 500 400 300 200 100 0 -40 -15 10 35 60 85 0 0.5 TEMPERATURE (°C) TRANSITION TIME vs. TEMPERATURE 2.0 2.5 3.0 PROPAGATION DELAY vs. TEMPERATURE 120 tR 110 100 tF 420 PROPAGATION DELAY (ps) MAX9316A toc03 130 TRANSITION TIME (ps) 1.5 FREQUENCY (GHz) 140 90 1.0 400 SCLK MEASUREMENT AT VIH = 2.12V, VCC = +1.82V 380 DIFFERENTIAL CLK MAX9316A toc05 SUPPLY CURRENT (mA) 36 900 MAX9316A toc02 ALL PINS ARE OPEN EXCEPT VCC AND VEE DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9316A toc01 40 360 340 80 320 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9316A Typical Operating Characteristics (VCC = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.15V, input transition time = 125ps (20% to 80%), fIN = 1.5GHz, outputs loaded with 50Ω to (VCC - 2V), TA = +25°C, unless otherwise noted.) 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A Pin Description PIN NAME FUNCTION 1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 2 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 4 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 5 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 6 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 7 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 8 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 9 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 10 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to (VCC - 2V). 11 VEE Negative Supply Voltage 12 SEL Clock Select Input (Single Ended). Drive low to select the CLK, CLK input. Drive high to select the SCLK input. The SEL threshold is equal to VBB. Internal 30kΩ pulldown to VEE and 30kΩ pullup to VCC. 13 VBB Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise, leave it unconnected. 14 CLK Inverting Differential Clock Input. Internal 45kΩ pullup to VCC and 45kΩ pulldown to VEE. 15 CLK Noninverting Differential Clock Input. Internal 30kΩ pulldown to VEE and 45kΩ pullup to VCC. 16 SCLK Single-Ended Clock Input. Internal 30kΩ pulldown to VEE and 45kΩ pullup to VCC. 17 N.C. Not Internally Connected. Solder to PC board for package thermal dissipation. 18, 20 VCC Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 19 EN Output Enable Input. Outputs are synchronously enabled on the falling edge of the clock input when EN is low. Outputs are synchronously set to low on the falling edge of the clock input when EN is high. Internal 30kΩ pulldown to VEE and 30kΩ pullup to VCC. Detailed Description The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock or data distribution. A 2-to-1 MUX selects one of the two clock inputs, CLK, CLK and SCLK. The CLK and CLK inputs are differential while the SCLK is single ended. The MUX is switched by the single-ended SEL input. A logic low selects the CLK input and a logic high selects the SCLK input. The SEL logic threshold is set by the internal voltage reference VBB. SEL input can be driven by VCC and VEE or by a singleended (LV)PECL/(LV)ECL signal. The selected input is reproduced at five differential outputs, Q0 to Q4. Synchronous Enable The MAX9316A is synchronously enabled and disabled with outputs in the low state to eliminate shortened clock pulses. EN is connected to the input of an edgetriggered D flip-flop. After power-up, drive EN low and toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are disabled to a low state on the falling edge of the selected clock input after EN goes high. The threshold for EN is equal to VBB. Power Supply For interfacing to differential HSTL and (LV)PECL signals, the V CC range is from 3.0 to 5.5V (with V EE 6 _______________________________________________________________________________________ 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver Input Bias Resistors When the CLK and CLK inputs are open, the internal bias resistors set the inputs to differential low state. The inverting input (CLK) is biased with a 45kΩ pullup to VCC and a 45kΩ pulldown to VEE. The noninverting input (CLK) and SCLK are biased with a 45kΩ pullup to VCC and a 30kΩ pulldown to VEE. The single-ended inputs (SEL, EN) are each biased with a 30kΩ pulldown to VEE and a 30kΩ pullup to VCC. Differential Clock Input Limits The maximum magnitude of the differential signal applied to the differential clock input is 3.0V. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. Single-Ended Clock Input and VBB The differential clock input can be configured to accept a single-ended input. This is accomplished by connecting the on-chip reference voltage, VBB, to the inverting or noninverting input of the differential input as a reference. For example, the differential CLK, CLK input is converted to a noninverting, single-ended input by connecting VBB to CLK and connecting the single-ended input signal to CLK. Similarly, an inverting configuration is obtained by connecting VBB to CLK and connecting the single-ended input to CLK. With a differential input configured as single ended (using VBB), the singleended input can be driven to VCC and VEE or with a single-ended (LV)PECL/(LV)ECL signal. Note that the single-ended input must be least VBB ±95mV or a differential input of at least 95mV to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. Applications Information Supply Bypassing Bypass VCC to VEE with high-frequency, surface-mount, ceramic, 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC (if the VBB reference is not used, it can be left open). Controlled-Impedance Traces Input and output trace characteristics affect the performance of the MAX9316A. Connect input and output signals with 50Ω characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs with 50Ω to V CC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0. Chip Information TRANSISTOR COUNT: 616 PROCESS: Bipolar When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, leave it open. The V BB reference can source or sink 0.5mA. Use VBB only for an input that is on the same device as the VBB reference. _______________________________________________________________________________________ 7 MAX9316A grounded), allowing high-performance clock or data distribution in systems with a nominal 5.0V supply. For interfacing to differential (LV)ECL, the V EE range is -3.0V to -5.5V (with VCC grounded). Output levels are referenced to VCC and are considered (LV)PECL or (LV)ECL, depending on the level of the V CC supply. With VCC connected to a positive supply and VEE connected to ground, the outputs are (LV)PECL. The outputs are (LV)ECL when VCC is connected to ground and VEE is connected to a negative supply. MAX9316A 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver CLK VIH CLK VBB VIL (CLK IS CONNECTED TO VBB) VOH Q_ VOH - VOL VOL Q_ Figure 1. MAX9316A Switching Characteristics with Single-Ended Input CLK VIHD VIHD - VILD CLK VILD tPLHD1 tPHLD1 Q_ VOH VOH - VOL Q_ VOL 80% 80% 0V (DIFFERENTIAL) 0V (DIFFERENTIAL) 20% 20% Q_ - Q_ tR tF Figure 2. MAX9316A Timing Diagram 8 _______________________________________________________________________________________ 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A VIHD SCLK VILD tPHLD3 tPLHD3 Q_ VOH VOH - VOL Q_ VOL 80% 80% 0V (DIFFERENTIAL) 0V (DIFFERENTIAL) 20% 20% Q_ - Q_ tR tF Figure 3. MAX9316A Timing Diagram for SCLK EN tS tH tS CLK SCLK OR CLK tPLHD Q_ Q_ OUTPUTS ARE LOW OUTPUTS STAY LOW Figure 4. MAX9316A EN Timing Diagram _______________________________________________________________________________________ 9 MAX9316A 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver Functional Diagram VCC VCC Q0 45kΩ 45kΩ Q0 CLK Q1 CLK Q1 30kΩ VEE 45kΩ Q2 VEE 0 Q2 VCC Q3 1 45kΩ Q3 SCLK Q4 VCC 30kΩ VCC VEE Q4 30kΩ SEL 30kΩ EN VBB 30kΩ 30kΩ VEE VCC 10 Q D VEE MAX9316A ______________________________________________________________________________________ 1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver DIM A A1 B C e E H L H E MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.050 0.299 0.291 0.394 0.419 0.050 0.016 SOICW.EPS INCHES N MILLIMETERS MIN 2.35 0.10 0.35 0.23 MAX 2.65 0.30 0.49 0.32 1.27 7.40 7.60 10.00 10.65 0.40 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D D D D A B e MIN 0.398 0.447 0.496 0.598 0.697 MAX 0.413 0.463 0.512 0.614 0.713 MILLIMETERS MIN 10.10 11.35 12.60 15.20 17.70 MAX 10.50 11.75 13.00 15.60 18.10 N MS013 16 AA 18 AB 20 AC 24 AD 28 AE C 0 -8 A1 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .300" SOIC APPROVAL DOCUMENT CONTROL NO. 21-0042 REV. B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9316A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)