Order this document by MC141622EVK/D SEMICONDUCTOR TECHNICAL DATA 1. SUMMARY The MC141622EVK is a development board for evaluation of the MC141622. In addition to the MC141622, the MC141622EVK contains all the analog circuit that is necessary for buffering both the input and output video signal and generation of the 4xfsc clock. By connecting an external signal source, monitor, and power supply, it is possible to evaluate all the operating modes on the MC141622. 2. SPECIFICATION Board Dimensions Y/C Separation LSI Video Input Amplifier Video Output Amplifier Clamp Circuit Clock Generator Clock Buffer Amplifier Analog Input/Output Interface Digital Input/Output Interface Action Mode Regulator Recommended Supply Voltage Operating Temperature Supply Current 100 mm (Length) x 150 mm (Width) MC141622FU Mount MC14577 2SC2002 Use MC14576 Use 2SC2002 2SA953 Use MC1378P Use MC14576 Use BNC Connector x3, S Terminal Output Mount 16 Pin Header Mount MC141622 Supports All Operating Modes MC7805CT Use + 10 V 0 to 50°C 350 mA REV 3 1/97 TN97012000 Motorola, Inc. 1997 MOTOROLA MC141622EVK 1 3. BOARD OPERATION 3.1 ACF–II Operating Mode AFC–II has four operating modes. Any one of these modes can be selected using the digital code input to MODE 0 and MODE 1 using ROTARY SW. The function of each mode is as follows. (1) Normal fsc Mode This is the mode for usual Y/C separation. It separates Y/C from the video signal that is input to the A/D converter. The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 – C3 (block level parameter), C4 – C7 (white level parameter), and D4 – D7 (noise slice level parameter). The clock is a 3.579545 MHz subcarrier input to the CLK connector; the built–in 4x PLL generates 4xfsc clock. (2) Normal 4xfsc Mode This mode is used for Y/C separation. It separates Y/C from the video signal that is input to the A/D converter. The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 – C3 (block level parameter), C4 – C7 (white level parameter), and D4 – D7 (noise slice level parameter). The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector. (3) Digital Input Comb Filter Mode This mode uses the A/D converter, filter, and D/A converter as two independent blocks. The digital data converted by the A/D converter is output on C0 – C7. Data input on D0 – D7 is processed by the ACF–II. Filtering is performed by the algorithm of ACF–II and the Y/C video is output as analog signals from Yout and Cout. These two blocks can operate with input clock signals that have different frequencies or phases and can be operated independently by using the CLK(AD) for the A/D converter, and the CLK input for the D/A converter. The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector and the CLK(AD) connector. (4) Digital Output Comb Filter Mode In addition to the normal Y/C analog outputs, the MC141622EVK can provide the Y/C signals as digital luminance and chrominance signals. The digital luminance data is output on C0 – C7 and the digital chrominance data is output on D0 – D7. This digital data can be modified by other digital processing. MC141622EVK 2 MOTOROLA The following table is the assignment for the operating mode. MODE Switching Function MODE1 MODE0 Rotary SW Normal fsc Mode Mode L L 0 Normal 4xfsc Mode L H 1 Digital Input Comb Filtering Mode H L 2 Digital Output Comb Filtering Mode H H 3 4. BK FUNCTION By setting the BK pin (toggle SW1) to the H level, composite video is output on the Yout pin and the chrominance signal on the Cout pin. The following table is the function of the BK pin. BK Function BK Pin Yout Pin Cout Pin L Luminance Chrominance H Composite Chrominance 4.1 Vertical Enhancer Function By setting the VH pin (toggle SW2) to the L level, the vertical enhancer feature is enabled. The coring parameter of the vertical enhancer can be set up every 1 LSB by the digital code that are input to C0 – C3 (black level parameter), C4 – C7 (white level parameter), and D4 – D7 (noise slice level parameter. The set up level of the coring parameter and characteristics are as follows. Vertical Enhancer Function Coring Characteristics OUT OUT WHITE LEVEL (C4 – C7) (0 – 15 STEP) WHITE IN IN BLACK OUT OUT IN NOISE LEVEL (D4 – D7) (0 – 15 STEP) MOTOROLA IN BLACK LEVEL (C0 – C3) (0 – 16 STEP) VH Pin Vertical Enhancer L On H Off Coring Parameter Set Up C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 L L L L L L L L L L H H L H L H 0 1 2 3 L L L L H H H H L L H H L H L H 4 5 6 7 H H H H L L L L L L H H L H L H 8 9 A B H H H H H H H H L L H H L H L H C D E F Level L l MC141622EVK 3 4.2 Clock Generator Compounding The clock generator (MC1378P) provides the necessary reference oscillator and phase locks the clock to the color subcarrier by inputting the composite video signal. VC1 adjusts the horizontal VCO to synchronize the output of the burst gate (pin 5 on the MC1378P) with the input video signal. VC2 adjusts the chroma VCO for maximum amplitude output from the clock buffer (pin 1 on the MC14576). VR3 adjusts pull–in of the chroma PLL filter. This is usually fixed to the center position. VR4 selects the dc bias for the clock buffer output and is usually 2.25 V. 4.3 Video Amplifier Adjustment On the video amplifier (MC14577), the gain is adjusted by VR1. This sets the input range (3.0 Vp–p) of the A/D converter in MC141622FU. VR2 is the clamp level adjustment. This adjusts the sync tip clamping of the input video signal to the video amplifier. 4.4 Outside Interface The outside interface should provide a composite video input signal to BNC1. The MC141622EVK provides Y/C separation and outputs the luminance from BNC2 and the color signal from BNC3. There is an S output connector on this board for easy connection to instruments having an S input connector. BNC4 and BNC5 are for the external input of each CLK and CLK(AD). However, when using these, it is necessary to modify the board pattern; i.e., cut (J5, J6). There is no filter for bandwidth limitations on this board beyond that imposed by the bandwidth limitations of the MC14577 buffer amplifier. To minimize noise resulting from excessive bandwidth, the bandwidth of input video signal should be limited to no more than one half of the clock frequency. MC141622EVK 4 MOTOROLA 5. MC141622EVK CIRCUIT 47 µF + 40 39 0.1 µF 0.1 µF 0.1 µF 38 37 36 35 34 33 32 31 ADC GND 0.1 µF 1.0 µF 0.0047 µ F 470 kΩ 30 29 11 12 + 1.0 µF 28 27 26 25 160 + 1.0 0.1 µF µF 24 23 22 21 17 18 19 20 MC1378P DAC GND DIGITAL GND 2 3 4 5 6 7 TANTALUM CAPACITOR 0.02 µ F 9 10 0.1 µF 680 MULTI–LAYER CERAMIC CAPACITOR 8 17.7 MHz 14.3 MHz 1 + 4 MHz CER. RES. + 750 kΩ + 1.0 µF 0.001 µ F 1 µF 1 kΩ 30 pF 14 15 0.1 µF 0.1 µF 16 0.1 µF + 0.1 µF 1.0 µF 4.7 µF 2.2 kΩ 1.8 kΩ 13 0.1 µF 10 kΩ x 8 0.1 µF 47 µF + 0.1 µF 7.5 mΩ 30 pF 1 mΩ 0.1 µF 33 µH 4 3 2 1 MC14576 10 kΩ x 8 5 6 7 8 33 µH + 47 µF 0.1 µF 1 mΩ 0.1 µF 47 kΩ x 8 VCC(D) 5V 47 kΩ x 8 5 J5 33 µH + 47 µF 0.1 µF Cout BNC3 MOTOROLA C7 C6 C5 C3 C4 C2 C0 22 MODE1 48 21 MODE0 BK 41 20 CLK(AD) VH 42 19 GND(D) 43 18 VCC(D) VCC(D) 44 17 CLC FSC 45 16 CLout NC 46 15 Vin NC 47 14 RBT NC 48 13 RTP FL IN GND(DA) Yout 8 9 10 11 12 VCC(AD) BIAS 7 GND(AD) 6 + 1 – 8 7 4 + – + 160 33 µH 0.1 µF + 0.1 47 µF 2.2 kΩ µF 750 kΩ 2.2 kΩ C2002 8 C2002 + 1 – 4 1.0 µF 3 2 2.2 kΩ MC14677 0.33 µF 2 kΩ 2 kΩ 1 kΩ 610 610 k A953 GAIN ADJUST 10 µF + 0.1 µF + 10 µF 0.1 µF 33 µH 0.1 µF 47 µF + 47 µF VCC(A) (5 V) 3 2 5 33 µH 47 µF CLK(AD) BNCS VIDEO IN BNC1 1.0 µF VCC(A) 10 V 10 k Ω 5 I bias 4 REF(DA) 3 0.1 µ F 2 VCC(DA) Cout 1 + 1/2MC14678 7 kΩ 39 D0 9.1 kΩ 4 Yout BNC2 D1 + 0.1 µF 47 µF 8 7 kΩ TE0 43 kΩ 33 µH VCC(A) 10 V 23 GND (D) CLK BNC4 VCC(D) 5V 38 MC141622 0.1 µF J6 TE1 D2 PCO 33 µH 29 28 27 26 25 24 37 OVCC VCC(D) 5V SW 30 ROTARY SW CLAMP LEVEL 10 kΩ x 2 33 32 31 D3 200 47 µF 0.1 µF + 47 µF C1 36 35 34 + D7 D6 D5 D4 47 k Ω x 4 33 µH 47 µF + 0.1 µF 33 µH Vout VCC(A) (10 V) Vin MC7805CT 4.7 + 0.1 µF µF 4.7 µF GND + 0.1 µF 6 2/2MC14678 MC141622EVK 5 6. MC141622EVK PARTS LIST Reference Designation IC1 IC2 IC3 IC4 IC5 IC6 Description MC141622FU MC14576CP MC14577CP MC7805CT MC14576CP MC1378P TR1 TR2 TR3 2SC2002 2SC2002 2SA953 R1 R2 R3, R4 R5 R6 R7, R8 R9 R10 R11 R12, R13 R14 R15 R16 R17 R18 R19, R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 9.1 kΩ 62 kΩ 75 Ω 3.6 kΩ 750 kΩ 2.0 kΩ 510 Ω 150 Ω 510 kΩ 2.2 kΩ 47 kΩ x 4 47 kΩ x 8 10 kΩ x 8 47 kΩ x 8 10 kΩ x 8 10 kΩ x 4 200 Ω 1.8 kΩ 680 Ω 750 kΩ 2.2 kΩ 7.5 mΩ 1.0 mΩ 150 Ω 470 kΩ L1 – L9 L10 L11 33 µH 4.7 µH 33 µH VR1 VR2 VR3 VR4 1 kΩ 2.2 kΩ 1 kΩ 1 mΩ VC1, VC2 30 pF SW1, SW2 Toggle Switch DIP SW1, DIP SW2 8 Channel Dip Switch ROTARY SW 16 Channel Switch 4 MHz Cer. Res 14.32 MHz Crystal MC141622EVK 6 Reference Designation Description C1 C2, C3 C4, C5, C6 C7 C8 C9 C10 C11 C12 C13 C14, C15 C16 C17 C18 C19 C20, C21 C22 C23 C24 C25 C26 C27 C28 C29, C30 C31 C32 C33, C34 C35 C36 C37 C38 – C45 C46 C47, C48 C49 – C51 C52 C53 C54 C55 – C57 0.1 µF 47 µF 0.1 µF 47 µF 0.1 µF 10 µF 0.1 µF 10 µF 0.33 µF 1.0 µF 0.1 µF 47 µF 0.1 µF 1.0 µF 47 µF 0.1 µF 47 µF 0.1 µF 47 µF 0.1 µF 47 µF 10 µF 0.1 µF 47 µF 0.1 µF 0.022 µF 1.0 µF 0.1 µF 0.001 µF 47 µF 0.1 µF 1.0 µF 0.1 µF 1.0 µF 0.1 µF 47 µF 0.047 µF 0.1 µF MOTOROLA L11 7. MC141622EVK LAYOUT C52 C29 C49 C48 R28 C51 C50 C57 C56 C55 C54 C53 MC1378P 7805CT C30 IC8 POWER C23 VIDEO IN 14.32 L5 R25 C36 C24 C22 C47 C21 C31 C41 C42 C43 C44 C45 C46 IC4 L10 SETTING CLAMP LEVEL IC3 C16 R7 VR1 R12 MC14577 R8 R9 C18 SETTING VIDEO AMPLITUDE R11 C17 C19 R26 MC14576 IC6 R16–1 J6 C39 VC2 R27 C38 C37 VR3 VR4 C20 C40 L9 R13 BNC1 L4 C34 R24 TR3 VC1 4 MHz R28 C31 L8 R22 C32 C33 VR2 TR2 R6 C13 C15 C10 C11 C8 C9 J3 ROTARY SW BNC5 C12 TR1 CLK(AD) C14 BNC2 J2 C7 L3 L4 R4 S CONNECTOR IC2 R3 C1 MC14576 C4 L1 R5 C2 MC141622 IC1 Yout J1 C6 R15 PIN HEADER C–PORT DIP SW2 R16 R4 PIN HEADER R17 DIP SW1 R18 R2 C3 C25 R20 R1 C27 R21 C28 C29 C26 L6 SW2 SW1 D–PORT R19 MOTOROLA OFF VERTICAL ENHANCE OFF ON BNC3 Cout R7 J4 J5 BK ON CLK BNC4 CLK MC141622EVK 7 Motorola reserves the right to make changes without further notice to any products herein. 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