DATA SHEET MOS FIELD EFFECT TRANSISTOR NP50P06KDG SWITCHING P-CHANNEL POWER MOSFET DESCRIPTION The NP50P06KDG is P-channel MOS Field Effect Transistor designed for high current switching applications. <R> ORDERING INFORMATION PART NUMBER NP50P06KDG-E1-AY Note NP50P06KDG-E2-AY Note LEAD PLATING PACKING PACKAGE Pure Sn (Tin) Tape 800 p/reel TO-263 (MP-25ZK) Note Pb-free (This product does not contain Pb in external electrode.) FEATURES (TO-263) • Super low on-state resistance RDS(on)1 = 17 mΩ MAX. (VGS = −10 V, ID = −25 A) RDS(on)2 = 23 mΩ MAX. (VGS = −4.5 V, ID = −25 A) • Low input capacitance Ciss = 5000 pF TYP. ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS −60 V Gate to Source Voltage (VDS = 0 V) VGSS m20 V Drain Current (DC) (TC = 25°C) ID(DC) m50 A ID(pulse) m150 A 90 W Drain Current (pulse) Note1 Total Power Dissipation (TC = 25°C) PT1 Total Power Dissipation (TA = 25°C) PT2 1.8 W Channel Temperature Tch 175 °C Tstg −55 to +175 °C Storage Temperature Single Avalanche Current Note2 IAS 32 A Single Avalanche Energy Note2 EAS 106 mJ Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1% 2. Starting Tch = 25°C, VDD = −30 V, RG = 25 Ω, VGS = −20 → 0 V THERMAL RESISTANCE Channel to Case Thermal Resistance Rth(ch-C) 1.67 °C/W Channel to Ambient Thermal Resistance Rth(ch-A) 83.3 °C/W The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. D18689EJ3V0DS00 (3rd edition) Date Published May 2007 NS CP(K) Printed in Japan The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 2007 NP50P06KDG ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = −60 V, VGS = 0 V −10 μA Gate Leakage Current IGSS VGS = m20 V, VDS = 0 V m100 nA VGS(th) VDS = −10 V, ID = −1 mA −1.0 −1.6 −2.5 V | yfs | VDS = −10 V, ID = −25 A 15 30 RDS(on)1 VGS = −10 V, ID = −25 A 13.5 17 mΩ RDS(on)2 VGS = −4.5 V, ID = −25 A 15.4 23 mΩ Input Capacitance Ciss VDS = −10 V, 5000 pF Output Capacitance Coss VGS = 0 V, 600 pF Reverse Transfer Capacitance Crss f = 1 MHz 300 pF Turn-on Delay Time td(on) VDD = −30 V, ID = −25 A, 20 ns Rise Time tr VGS = −10 V, 45 ns Turn-off Delay Time td(off) RG = 0 Ω 405 ns Fall Time tf 270 ns Total Gate Charge QG VDD = −48 V, 95 nC Gate to Source Charge QGS VGS = −10 V, 10 nC QGD ID = −50 A 26 nC VF(S-D) IF = −50 A, VGS = 0 V 0.97 Reverse Recovery Time trr IF = −50 A, VGS = 0 V, 50 ns Reverse Recovery Charge Qrr di/dt = −100 A/μs 70 nC Gate to Source Threshold Voltage Note Forward Transfer Admittance Drain to Source On-state Resistance Note Gate to Drain Charge Body Diode Forward Voltage Note S 1.5 V Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2% TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME D.U.T. RG = 25 Ω D.U.T. L RL 50 Ω PG. VGS = −20 → 0 V VDD RG PG. VGS(−) VGS Wave Form 0 VGS 10% 90% VDD VDS(−) − IAS BVDSS VDS ID VGS(−) 0 VDS Wave Form τ VDD Starting Tch τ = 1 μs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. PG. 2 IG = −2 mA RL 50 Ω VDD Data Sheet D18689EJ3V0DS VDS 90% 90% 10% 10% 0 td(on) tr td(off) ton tf toff NP50P06KDG TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 120 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 120 100 80 60 40 20 100 80 60 40 20 0 0 0 25 50 75 100 125 150 175 200 0 25 Tch - Channel Temperature - °C 50 75 100 125 150 175 200 TC - Case Temperature - °C FORWARD BIAS SAFE OPERATING AREA -1000 ID(pulse) PW =1 i DC μs i m -10 00 1i ID(DC) s 1i 0 RDS(on) Limited (VGS = −10 V) i m w Po s D er -1 si is t io pa n d it e m Li -0.1 TC = 25°C Single Pulse -0.01 -0.1 -1 -10 -100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A -100 1000 100 Rth(ch-A) = 83.3°C/Wi 10 1 Rth(ch-C) = 1.67°C/Wi 0.1 Single Pulse 0.01 100 μ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet D18689EJ3V0DS 3 NP50P06KDG DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS -150 -1000 VDS = −10 V Pulsed VGS = −10 V ID - Drain Current - A ID - Drain Current - A -100 -100 −4.5 V -50 -10 Tch = −55°C −25°C 25°C 75°C 125°C 150°C 175°C -1 -0.1 -0.01 Pulsed 0 -0.001 -1 -2 -3 0 -1 -2 -5 GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT -3 -2.5 -2 -1.5 -1 VDS = −10 V ID = −1 mA -0.5 0 -75 -25 25 75 125 175 225 100 Tch = −55°C −25°C 25°C 75°C 10 125°C 150°C 175°C 1 VDS = −10 V Pulsed 0.1 -0.1 -1 40 30 VGS = −4.5 V −10 V 10 Pulsed 0 -1 -10 -100 -100 -1000 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ 50 20 -10 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT RDS(on) - Drain to Source On-state Resistance - mΩ -4 VGS - Gate to Source Voltage - V Tch - Channel Temperature - °C ID - Drain Current - A 4 -3 VDS - Drain to Source Voltage - V | yfs | - Forward Transfer Admittance - S VGS(th) - Gate to Source Threshold Voltage - V 0 30 ID = −50 A −25 A −10 A 20 10 Pulsed 0 0 -5 -10 -15 VGS - Gate to Source Voltage - V Data Sheet D18689EJ3V0DS -20 NP50P06KDG CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 40 10000 Ciss, Coss, Crss - Capacitance - pF 30 VGS = −4.5 V 20 −10 V 10 ID = −25 A Pulsed Ciss Crss 100 VGS = 0 V f = 1 MHz 0 -75 -25 25 75 125 175 Coss 1000 10 -0.1 225 SWITCHING CHARACTERISTICS -100 DYNAMIC INPUT/OUTPUT CHARACTERISTICS -60 VDS - Drain to Source Voltage - V 1000 td(on), tr, td(off), tf - Switching Time - ns -10 VDS - Drain to Source Voltage - V Tch - Channel Temperature - °C td(of f ) tf 100 td(on) tr 10 VDD = −30 V VGS = −10 V RG = 0 Ω 1 -0.1 -12 -50 -10 VDD = −48 V −30 V −12 V -40 -8 -30 -6 VGS -20 -10 -4 -2 VDS ID = −50 A 0 -1 -10 -100 0 ID - Drain Current - A 20 40 60 80 0 100 QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 -10 VGS = −10 V 0V -1 -0.1 Pulsed trr - Reverse Recovery Time - ns -100 IF - Diode Forward Current - A -1 100 10 -0.01 di/dt = −100 A/μs VGS = 0 V 1 0 0.5 1 1.5 VF(S-D) - Source to Drain Voltage - V -0.1 -1 -10 -100 IF - Diode Forward Current - A Data Sheet D18689EJ3V0DS 5 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE NP50P06KDG PACKAGE DRAWING (Unit: mm) 1.35±0.3 TO-263 (MP-25ZK) 4.45±0.2 1.3±0.2 0.025 to 0.25 0.5± 0.75±0.2 0.2 0 to 2.54 2.54±0.25 9.15±0.3 8.0 TYP. 7.88 MIN. 4 15.25±0.5 10.0±0.3 No plating 8o 0.25 1 2 3 1.Gate 2.Drain 2.5 3.Source 4.Fin (Drain) EQUIVALENT CIRCUIT Drain Body Diode Gate Source Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. 6 Data Sheet D18689EJ3V0DS NP50P06KDG • The information in this document is current as of May, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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