MICROSEMI NX2415

Evaluation board available.
NX2415
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH
INTEGRATED FET DRIVER AND DIFFERENTIAL CURRENT SENSE
PRELIMINARY DATA SHEET
Pb Free Product
FEATURES
DESCRIPTION
The NX2415 is a two-phase PWM controller with inte- n Differential inductor DCR sensing eliminates the
problem with layout parasitic
grated FET driver designed for low voltage high current
n
External
programmable voltage droop
application. The two phase synchronous buck converter
n
Low
Impedance
On-board Drivers
offers ripple cancelation for both input and output. The
n
Hiccup
current
limit
NX2415 uses differential remote sensing using either
current sense resistor or inductor DCR sensing to achieve n Power Good for power sequencing
accurate current matching between the two channels. n Enable Signal allows external shutdown as well as
programming the BUS voltage start up threshold
Differential sensing eliminates the error caused by PCB
n
Programmable frequency
board trace resistance that is otherwise is present when
n
Prebias start up
using a single ended voltage sensing. In addition the
n
Over
voltage protection without negative spike at
NX2415 offers high drive current capability especially for
output
keeping the synchronous MOSFET off during SW node
transition, accurate programmable droop allowing to re- n Pb-free and RoHS compliant
duce number of output capacitors, accurate enable circuit provides programmable start up point for Bus volt- n Graphic card High Current Vcore Supply
age, PGOOD output, programmable switching frequency n High Current +40A on board DC to DC converter
and hiccup current limiting circuitry.
applications
APPLICATIONS
TYPICAL APPLICATION
10
31
+5V
1uF
10k
30
PVCC1
VCC
BST1
EN
6.49k
HDRV1
23
+5V
1uF
24
op
7
45.3k
2
ENBUS
SW1
DROOP
LDRV1
RT
NX2415
29
10k
+5V
28
11
VOUT
430
3 PGSEN
10k
3.92k
6.8nF
5.62k
10k
20k
SW2
150pF
10nF
1k
180k
100k
10nF
1nF
PVCC2
HDRV2
5 FB
6 VCOMP
LDRV2
4
VP
8 OCP
1
VREF
14
IOUT
0.68uH
2.15
26
100uF
M1
M2
22
VOUT
+1.2V/50A
2 x (1000uF,7mohm ESR)
620
1uF
21
620
CS+1 9
CS-1 10
BST2
1nF
20k
2N3906
CSCOMP
220nF
2.2nF
1.8nF
PGOOD
PGND1
VIN1
+12V
180uF
0.22uF
25
+12V
1.65k
1uH
2 x 10uF
PGND2
18
1uF
+5V
17
16
15
19
10uF
0.22uF
M3
0.68uH
2.15
M4
620
1uF
20
620
12
CS+2
CS-2 13
AGND
32
Figure1 - Typical application of NX2415
ORDERING INFORMATION
Device
NX2415CMTR
Rev.4.8
05/06/08
Temperature
0 to 70oC
Package
MLPQ-32L
Frequency
200kHz to 1MHz
Pb-Free
Yes
1
NX2415
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 6.5V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC To 150oC
Operating Junction Temperature Range ............... -40oC To 125oC
Lead temperature(Soldering 5s) ........................... 260oC
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
HDRV1
NC
SW1
ENBUS
PGOOD
EN
AGND
VCC
32-LEAD PLASTIC MLPQ 5 x 5
32 31 30 29 28 27 26 25
VREF
1
24 BST1
RT
2
23 PVCC1
PGSEN
3
22 LDRV1
VP
4
FB
5
21 PGnd1
NX2415
20 PGnd2
COMP
6
19 LDRV2
DROOP
7
18 PVCC2
OCP
8
θ JA ≈ 35o C /W
17 BST2
HDRV2
SW2
IOUT
CS-2
CS+2
CSCOMP
CS-1
CS+1
9 10 11 12 13 14 15 16
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, V BST-VSW =5V, EN=HIGH, and TA = 0 to 70oC.
Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures
equal to the ambient temperature.
PARAMETER
Supply Voltage(Vcc)
VCC ,PVCC Voltage Range
SYM
TEST CONDITION
VCC
VCC Supply Current (static)
ICC (Static) EN=LOW
PVCC Supply Current
(Dynamic)
EN&ENBUS HIGH,
ICC
Freq=200Khz per phase
(Dynamic)
CLOAD=2200PF
VBST Voltage Range
VBST to VSW
VBST Supply Current
((Dynamic))
EN&ENBUS HIGH,
VBST
Freq=200Khz per phase
(Dynamic)
CLOAD=2200PF
Rev.4.8
05/06/08
MIN
TYP
MAX
UNITS
4.5
5
5.5
V
-
6.6
mA
4
mA
4.5
5
4
5.5
V
mA
2
NX2415
PARAMETER
Under Voltage, Vcc ,
Enable(EN) & ENBUS
SYM
VCC-Threshold
VCC_UVLO
VCC-Hysteresis
EN Threshold
EN Hysteresis
ENBUS Threshold
ENBUS Hysteresis
Reference Voltage
Ref Voltage
VCC_Hyst
Ref Voltage line regulation
Oscillator (Rt)
Frequency for each phase
Ramp-Amplitude Voltage
MIN
VCC Rising
Vcc Rising
VBUS Rising
VREF
Fs
VRAMP
Ramp Peak
Ramp Valley
Max Duty Cycle
Min Duty Cycle
Transconductance
Amplifiers(CSCOMP)
Open Loop Gain
Transconductance
Voltage Mode Error
Amplifier
Open Loop Gain
Input Offset Voltage
Output Current Source
Output Current Sink
Output HI Voltage
Output LOW Voltage
SS (Internal )
Soft Start time
Power Good(Pgood)
Threshold
TEST CONDITION
4.5V<Vcc<5.5V
Rt=45kohm
200Khz/Phase
TYP
MAX
4
V
0.2
0.6
0.1
1.6
0.16
V
V
V
V
V
0.8
V
1
%
400
1
KHz
V
2.5
1.5
95
V
V
%
%
0
50
65
1600
dB
umoh
50
Vio_v
0
5
5
Vcc-1.5
0.5
Tss
Hysteresis
PGood Voltage Low
UNITS
dB
mV
mA
mA
V
V
200Khz/Phase
20
mS
VSEN Falling
74
%VID
IPGood=-5mA
5
0.5
%
V
High Side Driver(CL=4700pF)
Output Impedance , Sourcing
Current
Output Impedance , Sinking
Current
Rise Time
Rsource(Hdrv)
I=200mA
1.1
ohm
Rsink(Hdrv)
I=200mA
0.8
ohm
THdrv(Rise)
VBST-VSW=4.5V
24
ns
Fall Time
THdrv(Fall)
VBST-VSW=4.5V
24
ns
Deadband Time
Tdead(L to Ldrv going Low to Hdrv going
H)
High, 10%-10%
30
ns
Rev.4.8
05/06/08
3
NX2415
PARAMETER
Low Side Driver
(CL=4700pF)
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time
Fall Time
Deadband Time
Current Sense
Amplifier(CS+, CS-)
Current Sense Amplifier
Mismatch
Voltage Gain
Droop Voltage Current
Source(Droop)
Droop Voltage Current Source
OCP Adjust
Blank time before activating
OCP
Vref
Reference Voltage
Driving current ability
OVP Threshold
OVP Threshold
Rev.4.8
05/06/08
SYM
TEST CONDITION
MIN
Rsource(Ldrv)
I=200mA
1.1
ohm
Rsink(Ldrv)
I=200mA
0.5
ohm
40
36
30
ns
ns
ns
0
mV
TLdrv(Rise)
10% to 90%
TLdrv(Fall)
90% to 10%
Tdead(H to SW going Low to Ldrv going
L)
High, 10% to 10%
K
29.7
TYP
30
MAX
30.3
UNITS
V/V
V(IOUT)=0.6V,feedback
resistor=10kohm,Rdroop=60
kohm
100
uA
200Khz/Phase
15
uS
1.6
5
V
mA
0.96
V
4
NX2415
PIN DESCRIPTIONS
PIN #
SYMBOL
PIN DESCRIPTION
31
VCC
25,
16
HDRV1,
HDRV2
High side gate driver outputs.
22,
19
LDRV1,
LDRV2
Low side gate driver outputs.
30
EN
IC’s supply voltage. This pin biases the internal logic circuits. A minimum 1uF
ceramic capacitor is recommended to connect from this pin to ground plane.
This pin is used to remotely turn off the controller. The pin has a threshold
voltage of 0.6 volts.
24, 17
BST1,BST2 These pins supplies voltage to high side FET drivers.
26,15
SW1,SW2
23,
18
PVCC1,
PVCC2
These pins provide the supply voltage for the lower MOSFET drivers.
28
PGOOD
This pin is an open collector output. If used, it should be pulled to 5V with a
resistor greater than or equal to 10k, otherwise it my be left open. Any fault or
under voltage on the enable pins will cause the signal to be pulled low.
4
VP
Input to the positive pin of the error amplifier. A resistor is connected from the
output of the DAC to this pin. Place a small capacitor from this pin to GND to
filter any noise.
5
FB
This pin is the error amplifier inverting input. It is connected to the output voltage
via a voltage divider.
2
RT
This pin programs the internal oscillator frequency using a resistor from this pin to
ground. The frequency of each phase is 1/2 of this frequency.
9,12
These pins are connected to the source pins of the upper fets.
CS+1,CS+2 Positive input of the differential current sense amplifiers. It is connected directly
to the RC junction of the respective phase’s output inductor.
10,13
CS-1,CS-2
Negative input of the differential current sense amplifiers. It is connected directly
to the negative side of the respective phase’s output inductor.
11
CSCOMP
The output of the transconductance op amp for current balance circuit. An
external RC is connected from this pin to GND to stabilize the current loop.
6
VCOMP
This is the output pin of the error amplifier. The compensation network connection.
7
DROOP
A resistor from this pin to ground programs an internal current source that is fed
into the FB pin. This current source is proportional to the output current of the
regulator. The product of this current times the external resistor RFB provides a
droop voltage.
Rev.4.8
05/06/08
5
NX2415
PIN #
SYMBOL
8
OCP
A resistor divider connected from this pin to Vref programs the current limit threshold. The outputs of the internal current sense differential amplifiers are summed
together to represent the output current. This voltage is then compared to this threshold.
1
VREF
A 1.6V buffered reference is brought out.
29
ENBUS
This pin is used to program the under voltage lockout of the bus supply. A resistor
divider from the bus voltage to this pin programs the under voltage lockout. When
the voltage of this pin is greater than 1.6V, the bus voltage is assumed in operation.
The pin has a 10% hysterisis.
21,
20
PGND1,
PGND2
This is the ground connection for the power stage of the controller.
32
AGND
14
IOUT
Input of OCP amplifier. Place a 10nF to 100nF capacitor from this pin to GND to
filter any noise.
3
PGSEN
Output over voltage and Pgood sensing pin. A resistor divider plus a small capacitor
should be connected to the this pin to set the OVP and Pgood.
Rev.4.8
05/06/08
PIN DESCRIPTION
Controller analog ground pin.
6
NX2415
BLOCK DIAGRAM
VCC
0.8V
1.6V
Bias
generator
UVLO
PVCC1
UVLO
1.25V
PVCC2
Enbus
BST1
1.6/1.44
start
Hiccup
BST2
EN
FET
driver
0.64
/0.53V
Digital
start
Vp
DrvH1
DrvH2
DrvL2
OVP
0.8V
DrvL1
SS_finish
Dis_EA
SW1
SW2
FB
R
S
Droop current
ramp1
PGND2
Set1
VCOMP
K=30
Two phase
OSC
Rt
PGND1
Q
KR
V1.25
R
set2
CS-1
KR
CS02
ramp2
Vref
CS+1
CS01
R
PWM control
logic
and driver
1.6V
KR
V1.25
R
CS+2
CS-2
0.8*120%
R
OVP
KR
Slave channel control
PGsen
V1.25
Σ
0.64/0.6
Pgood
CScomp
Σ
gm*Ri=0.6
gm
IOUT
SS_finished
Ri
Hiccup
32 cycles
filter
÷
2
Hiccup
Logic
6 Cycles
filter
OCP
Current Mirror
AGND
Droop
FB
Rev.4.8
05/06/08
7
NX2415
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN
- Input voltage
VOUT
- Output voltage
IOUT
- Output current
Choose inductor from Vishay IHLP_5050FD-01
with L=0.68uH DCR=1.4mΩ.
Current Ripple is recalculated as
∆IRIPPLE =
DVRIPPLE - Output voltage ripple
FS
L OUT =0.54uH
- Operation frequency for each channel
=
DIRIPPLE - Inductor current ripple
VIN -VOUT VOUT 1
×
×
LOUT
VIN FS
...(2)
12V-1.2V 1.2V
1
×
×
= 3.97A
0.68uH 12V 400kHz
Output Capacitor Selection
Design Example
The following is typical application for NX2415.
Output capacitor value is basically decided by the
VIN = 12V
output voltage ripple, capacitor RMS current rating and
VOUT=1.2V
IOUT_max=60A
load transient.
Based on Voltage Ripple
For electrolytic, POSCAP bulk capacitor, the ESR
DVRIPPLE <=12mV
(equivalent series resistance) and inductor current typi-
DVDROOP<=120mV @30A step
cally determines the output voltage ripple.
IOUT=50A
FS=400kHz
ESRdesire =
Phase number N=2
∆VRIPPLE 12mV
=
= 3.022mΩ
∆IRIPPLE 3.97A
...(3)
If low ESR is required, for most applications, mul-
Output Inductor Selection
tiple capacitors in parallel are better than a big capaci-
The selection of inductor value is based on induc-
tor. For example, for 12mV output ripple, SANYO OS-
tor ripple current, power rating, working frequency and
CON capacitors 2R5SEPC1000MX(1000uF 7mΩ) are
efficiency. Larger inductor value normally means smaller
chosen.
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu-
N =
ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
L OUT =
VIN -VOUT VOUT
1
×
×
∆IRIPPLE
VIN
FS
∆IRIPPLE =k ×
IOUTPUT
N
where k is between 0.2 to 0.4.
Select k=0.2, then
...(1)
E S R E × ∆ IR I P P L E
∆ VR IPPLE
...(4)
Number of Capacitor is calculated as
7m Ω × 3.97A
12mV
N =2.3
For ceramic capacitor, the current ripple is determined by the number of capacitor instead of ESR
N=
COUT =
∆IRIPPLE
8 × FS × ∆VRIPPLE
...(5)
Typically, the calculated capacitance is so small
that the output voltage droop during the transient can
not meet the spec although ripple is small.
12V-1.2V 1.2V
1
L OUT =
×
×
50A 12V 400kHz
0.2 ×
2
Rev.4.8
05/06/08
8
NX2415
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as:
∆VDROOP <∆VTRAN @ step load DISTEP
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, overshoot caused by
DISTEP transient load which is from high load to low load,
can be estimated as the following equation,if assuming
the bandwidth of system is high enough.
∆Vovershoot = ESR × ∆Istep +
VOUT
× τ2
2 × L × COUT
...(6)
where τ is the a function of capacitor, etc.
0 if LEFF ≤ Lcrit

τ =  LEFF ×∆Istep
− ESR × COUT
 V
OUT

...(7)
If the OS-CON capacitors (1000uF, 7mΩ ) is used,
the critical inductance is given as
Lcrit =
The effective inductor value is 0.34uH which is big-
number of capacitors is
in parallel.
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and capacitance is high and L ≤ L crit is true. In that case, the
transient spec is dependent on the ESR of capacitor.
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
+
VOUT
× τ2
2 × L × C E × ∆Vtran
LEFF × ∆Istep
VOUT
− ESR E × CE
0.34µH × 30A
− 7mΩ × 1000µF = 1.5us
1.2V
...(8)
where ESRE and CE represents ESR and capaci-
∆Vtran
ESR E × C E × VOUT
=
∆Istep
7mΩ × 1000µF × 1.2V
= 0.28µH
30A
=
tance of each capacitor if multiple capacitors are used
Rev.4.8
05/06/08
is 120mV for 30A load step.
capacitance.
if LEFF ≥ Lcrit
LOUT 0.68uH
=
= 0.34uH
N
2
ESR × COUT × VOUT ESR E × C E × VOUT
=
=
∆Istep
∆Istep
where
For example, assume voltage droop during transient
τ=
ESR E × ∆Istep
...(10)
age transient not only dependent on the ESR, but also
L EFF =
N=
if LEFF ≥ Lcrit
ger than critical inductance. In that case, the output volt-
where
L crit
0 if LEFF ≤ Lcrit

τ =  LEFF × ∆Istep
− ESR E × CE
 V

OUT
...(9)
N=
ESR E ×∆Istep
∆Vtran
+
VOUT
×τ2
2 × LEFF × CE ×∆Vtran
7mΩ× 30A
+
120mV
1.2V
× (1.5us)2
2 × 0.34µH×1000µF ×120mV
= 1.78
=
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
9
NX2415
Control Loop Compensator Design
NX2415 can control and drive two channel synchro-
nous bucks with 180o phase shift between each other.
One of two channels is called master, the other is called
slave. They are connected together by sharing the same
output capacitors. Voltage loop is designed to regulate
output voltage. In order to achieve the current balance in
these two synchronous buck converters, current loop
FZ1 =
1
2 × π × R 4 × C2
...(11)
FZ2 =
1
2 × π × (R 2 + R3 ) × C3
...(12)
FP1 =
1
2 × π × R3 × C3
...(13)
FP2 =
compensation network is employed to to make sure the
1
2 × π × R4 ×
...(14)
C1 × C2
C1 + C2
currents in slave is following the master.
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
Voltage Loop Compensator Design
the compensator.
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
Zf
C1
Vout
Zin
accurate output voltage and fast transient
response,compensator is employed to provide highest
R3
the Bode plot of the closed loop system has crossover
C2
R2
possible bandwidth and enough phase margin. Ideally,
C3
R4
Fb
frequency between 1/10 and 1/5 of the switching fre-
Ve
o
quency, phase margin greater than 50 and the gain cross-
R1
Vref
ing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II
compensator can be used to compensate the system,
Figure 2 - Type III compensator
because the zero caused by output capacitor ESR is
pensator should be chosen.
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo OSCON and POSCAP, the frequency of ESR zero
Gain(db)
lower than crossover frequency. Otherwise type III compower stage
FLC
40dB/decade
loop gain
FESR
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen-
20dB/decade
sate the system with type III compensator.
In design example, six electrolytic capacitors are
compensator
used as output capacitors. The system is compensated
with type III compensator. The following figures and equations show how to realize the this type III compensator
with electrolytic capacitors.
FZ1 FZ2 FP1
FO FP2
Figure 3 - Bode plot of Type III compensator
Rev.4.8
05/06/08
10
NX2415
The transfer function of type III compensator
6. Calculate R4 by choosing FO=40kHz.
is given by:
Ve
VOUT
(1+ sR4 × C2 ) × [1+ s(R2 + R3 ) × C3 ]
1
=
×
sR2 × (C2 + C1) (1+ sR × C2 × C1 ) × 1+ sR × C
(
4
3
3)
C2 + C1
Use the same power stage requirement as demo
board. The crossover frequency has to be selected as
FLC<FESR<FO, and usually FO<=1/10~1/5FS.
1.Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
1
2 × π × LEFF × COUT
1
=
2 × π × 0.34uH × 2000uF
= 6.1kHz
R4 =
VOSC 2 × π × FO × LEFF R2 × R3
×
×
Vin
ESR
R2 + R3
1V 2 × π × 40kHz × 0.34uH 10kΩ × 3.92kΩ
×
×
12V
3.5mΩ
10kΩ + 3.92kΩ
=5.73kΩ
=
Choose R4=5.62kΩ.
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2 × π × FZ1 × R 4
C2 =
1
2 × π × 0.75 × 6.1kHz × 5.62k Ω
= 6.2nF
=
Choose C2=6.8nF.
8. Calculate C 1 by equation (14) with pole F p2 at
half the switching frequency.
FESR
1
=
2 × π × ESR × COUT
1
2 × π × 3.5mΩ × 2000uF
= 22.7kHz
=
2.Set R2 equal to10kΩ.
R × VREF
10k Ω × 0.8V
R1= 2
=
= 20k Ω
VOUT -VREF
1.2V-0.8V
Choose R1= 20kΩ.
3. Calculate C3 by setting FZ2 = FLC and Fp1 =FESR.
1
2 × π × R 4 × FP2
C1 =
1
2 × π × 5.62kΩ × 200kHz
= 141pF
=
Choose C1=150pF.
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa-
1
1
1
C3 =
)
×(
2 × π × R2
Fz2 Fp1
1
1
1
=
)
×(
2 × π × 10k Ω
6.1kHz 22.7kHz
=1.9nF
tor can be used to compensate the system.
Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 4. R3 and C1
introduce a zero to cancel the double pole effect. C2
introduces a pole to suppress the switching noise. The
Choose C3=1.8nF.
following equations show the compensator pole zero lo-
5. Calculate R 3 by equation (13).
cation and constant gain.
R3 =
1
2 × π × FP1 × C3
1
2 × π × 22.7kHz × 1.8nF
= 3.89k Ω
=
Choose R3=3.92kΩ.
Rev.4.8
05/06/08
Gain=
Fz =
R3
R2
1
2 × π × R3 × C1
Fp ≈
1
2 × π × R 3 × C2
... (15)
... (16)
... (17)
11
NX2415
FLC =
C2
Vout
2 ×π× LEFF × COUT
1
=
C1
R3
1
2 ×π× 0.75uH×10800uF
= 1.768kHz
R2
Fb
Ve
FESR =
R1
Vref
1
2 × π × ESR × COUT
1
2 × π × 13m Ω × 1800uF
= 6.801kHz
=
Figure 4 - Type II compensator
2.Set R2 equal to10kΩ and calculate R1.
R1=
power stage
R 2 × VREF
10k Ω × 0.8V
=
= 20k Ω
VOUT -VREF
1.2V-0.8V
Gain(db)
3. Set crossover frequency FO=15kHz.
40dB/decade
4.Calculate R3 value by the following equation.
V O S C 2 × π × FO × L E F F
×
× R2
V in
ESR
R3=
loop gain
1V
2 × π × 15kHz × 0.75uH
×
× 10kΩ
12V
2.16m Ω
=27.3kΩ
=
20dB/decade
Choose R 3 =27.4kΩ.
5. Calculate C1 by setting compensator zero FZ
compensator
Gain
at 75% of the LC double pole.
1
2 × π × R3 × Fz
C1=
FZ FLC FESR FO FP
Figure 5 - Bode plot of Type II compensator
1
2 × π × 27.4kΩ × 0.75 × 1.768kHz
=4.4nF
=
Choose C1=4.7nF.
6. Calculate C 2 by setting compensator pole Fp
For this type of compensator, FO has to satisfy
at half the swithing frequency.
FLC<FESR<< FO and FO <=1/10~1/5Fs.
Here a type II compensator is designed for the case
C2=
which has six electrolytic capacitors(1800uF, 13mΩ) and
two 1.5uH inductors.
1.Calculate the location of LC double pole F LC
1
π × R 3 × Fs
1
π × 2 7 .4k Ω × 1 0 0 k H z
=116pF
=
and ESR zero FESR.
Choose C2=100pF.
Rev.4.8
05/06/08
12
NX2415
Current Loop Compensator Design
Power stage
Compensation
D(s)
Master
channel
1
d
Vosc
Current Sensing
Amplifier Gain
Vin
s*L+Req
iL
s*L+DCR
Rs*Cs*s+1
Inductor Current
sense
Figure 6 - Current loop control diagram
VIN
master channel
DCR
L
Rs
Vbias
Cs
Rs
VIN
Slave channel 1
DCR
L
PWM control
logic
and driver
Ramp for
slave channel
VOUT
Rs
Cs
Vbias
Rs
Icomp1 Rcc
C1
Slave channel control
C2
Slave channel control
Slave channel
Figure 7 - Function diagram of current loop
Rev.4.8
05/06/08
13
NX2415
Inductor Current Sensing
racy during the transient if droop function is required.
The illustration is shown in the following figure.
VIN
iL
L
Control &
Driver
VOUT
Rs
Current
Sensing
Amplifier
DCR
Rs
Cs
VS_IL
VS_IL----Voltage accross
the sensing
capacitor Cs
Overshoot caused
by inductor
nonlinearity
iL--- inductor current
Figure 8 - Inductor current sensing using RC network.
The inductor current can be sensed through a RC
Output voltage
with droop function
network as shown above. The advantage of the RC network is the lossless comparing with a resistor in series
Droop misbehavoir
caused by
overshoot of VS_IL
with output inductor.
The selection of the resistor sensing network is
chosen by the following equation:
R S × CS =
L
DCR
...(18)
If the above equation is satisfied, the voltage across
Figure 9 - Droop accuracy affected by the nonlinearity
of inductor.
In this case, the sensing resistor has to be chosen
the sensing capacitor Cs will be equal to the inductor
current times DCR of inductor for all frequency domain.
VS _ IL = DCR × iL
If the sensing capacitor is chosen
CS = 1µF
CS must be X7R or COG ceramic capacitor.
The sensing resistor is calculated as
RS =
L
DCR × CS
For example, for 0.68uH inductor with 1.4mΩ
DCR, we have
RS =
0.68µH
= 486Ω
1.4mΩ × 1µF
In most of cases, the selection of sensing resistor based on the above equation will be sufficient. However, for some inductor such as toroid coiled inductor
with micrometal, even the product of sensing resistor
and capacitor is perfectly match with L/DCR, the voltage
across the capacitor still has overshoot due to the
nonlinearity of inductor. This will affect the droop accu-
Rev.4.8
05/06/08
RS ≥
L
DCR × CS
to compensate the overshoot. This selection only affects the small signal mode of current loop. For DC accuracy, there is no effect since the DC voltage across
the sensing capacitor will equal to the DCR times inductor current at DC load no matter what Rs is. In this example, Rs=620Ω.
RS value is preferred to be less than 400Ω in
NX2415's application, therefore we need to reiterate the
calculation, choose CS 2.2uF instead. RS value is finally
chosen as 301Ω .
Powe dissipation of Rs resistor is calculated as
followed:
PD (RS ) =
(VIN − VOUT )2
V 2
× D + OUT × (1 − D)
RS
RS
(12 V − 1.2V)2
(1.2 V)2
× 0. 1 +
× (1 − 0.1)
301Ω
301Ω
= 0.04 W
=
The power rating of Rs should be over 0.04W.
14
NX2415
Current Loop Compensation
FP1 =
Req
2× π ×L
=
7.4mΩ
= 1.7kHz
2 × π × 0.68µH
The current compensation transfer function is
Slave channel
power stage
-20 dB
given as
D(s) =
Current loop
compensation
gm
×
s × ( C1 + C2 )
1 + s × Rcc × C1
R × C1 × C2
1 + s × cc
C1 + C2
It has one zero and one pole. The ideal is to
Loop gain
for slave
channel
choose resistor Rcc to achieve desired loop gain such
-20dB
0 DB
as 50kHz. Rcc can be calculated as
-40dB
Fp1
Fzc Fo
Rcc =
Fpc
2 × π × Fo × L × Vosc
gm × VIN × K C × DCR
...(19)
where
Figure 10 - Bode plot of current loop
The diagram and bode plot for current loop of
KC ≈
60 ⋅ kΩ
= 22.9
2kΩ+ RS
through inductor sensing is amplified by current sensing
60kΩ and 2kΩ is the internal resistance for the current
sensing amplifier.
For fast response, we can set the current loop
differential amplifier. The amplified slave current signal
cross-over frequency one and half times of voltage loop
is compared with the amplified inductor current from
cross-over frequency. Since the voltage loop cross-over
master channel (channel 1 for NX2415) through a
frequency is typically selected as 1/10 of switching fre-
transconductance amplifier, the difference between chan-
quency, we choose FO=50kHz.
NX2415 is shown in above figures. The current signal
nel current will change the output of transconductance
2 × π × 50kHz × 0.68µH × 1V
= 442Ω
1.6mA / V × 12 V × 22.9 ×1.4mΩ
amplifier, which will compare with a internal ramp signal
Rcc =
and changes the duty cycle of slave channel buck con-
Select
verter. If the inductor are perfectly matched and the PWM
Rcc = 430Ω .
controller has no offset, the DC current in slave channel
will equal to the DC current of master channel (channel
1) due to the gain of current loop.
From the bode plot, the power stage has one pole
The selection of capacitor C1 is such that the zero
of compensation will cancel the pole of power stage,
therefore,
C1 =
located at
FP1 =
Req
L
0.68µH
=
= 214nF
Req × Rcc 7.4mΩ × 430Ω
Typically, the capacitor C1 is so big that the cur-
2×π×L
where Req is the equivalent resistor and it is given by
rent loop may start slowly during the start up. There-

VOUT
V 
+ Rdson _ syn × 1 − OUT 
VIN
VIN 

selected capacitor can not reduce too much to cause
R eq ≈ DCR + R dson _ con ×
R dson _ con is the Rdson of control FET and R dson _ syn is
the Rdson of synchronous FET. For this example,
Req = 7.4mΩ
fore, smaller capacitor can be selected. However, the
phase droop.
Select C1=220nF.
The capacitor C2 is an option and it is used to
filter out the switching noise. C2 can be calculated as
The pole is located as
Rev.4.8
05/06/08
15
NX2415
VREF
1
1
C2 =
=
= 1.85nF
π × Rcc × FS π × 430Ω × 400kHz
100k
Select C2=2.2nF.
OCP
ROCP
Frequency Selection
The frequency can be set by external Rt resistor.
The relationship between frequency per phase and RT
Figure 12 - Over current protection
pin is shown as follows.
RT ≈
Output Voltage Droop Operation
18600000
FS
...(20)
The effective output impedance of the controller must
be adjusted to maximize the output voltage fluctuation
range. A program resistor attached to the Droop pin
RDROOP will program this value. The function works by an
frequency(kHz)
FREQUENCY(kHz) vs RT(kohm )
800
internal current source connected to the FB pin. This
700
current flows output of the FB pin and through the Rin
600
resistance from the FB pin to the output.
500
This current source is a function of the sensed
400
output current. As the output current increases, the droop
current will increase and causes the output voltage
300
todroop proportionately. The droop current is programmed
200
by a resistor attached to the Droop pin. The value of the
100
resistor is chosen as follows.
0
0
50
100
150
200
R t(kohm )
Figure 11 - Frequency vs Rt chart
Over Current/Short Circuit Protection
VOUT
RIN
The converter will go into hiccup mode if the
output current reaches a programmed limit V OCP
determined by the voltage at pin OCP.
VOCP = 0.6
ROCP =
VP
...(21)
IOCP pin. RS is the current sensing matching resistor
...(22)
Where RLL is desired load impedance. For example,
if we want Vout droops 60mV @ 20A,
RLL =
level,100kΩ is the resistor connecting VREF pin and
60mV
= 3mΩ
20A
IDROOP =
V(IOUT)
RDROOP
0.6 ×
=
Rev.4.8
05/06/08
COMP
Error Amplifer
∆VOUT = IDROOP × RIN = ∆ILOAD × RLL
Where Iocp is the desired over current protection
when using DCR sensing method.
IDROOP
Figure 13 - Output voltage droop funciton
60kΩ DCR
IOCP
2kΩ + R S 2
VOCP
× 100kΩ
VREF − VOCP
FB
60kΩ
DCR
×
× ILOAD
2kΩ + RS
2
RDROOP
...(23)
16
NX2415
Combine equation 22 and 23,
RDROOP =
0.6 60kΩ DCRILOADRIN
2 2kΩ + RS
∆VOUT
be calculated. From this figure, it is obvious that a multiphase converter can have a much smaller input RMS
...(24)
Where DCR is the sense resistor or the DCR of
the output inductor. RS is the current sensing matching
resistor when using DCR sensing method. ILOAD is the
load current. RIN is the input DC resistor of the master
phase compensator which connect FB pin and PGSEN
pin. For example, to have the DVOUT=60mV when the
load current is 20A, DCR is 1.4mΩ, RIN is 10kΩ, RS is
620Ω.
RDROOP
= 32kΩ
0.6
60kΩ
1.4mΩ × 20A × 10kΩ
=
×
×
2 2kΩ + 0.62kΩ
60mV
current, which results in a lower amount of input capacitors that are required.
For example, Vin=12V, Vout=1.2V. The duty cycle
is D=Vout/Vin=1.2/12=10%. From the figure, for two
phase,
the
RMS
current
is
0.2*Iout=0.2*50A=10A.
A combination of ceramic and electrolytic(SANYO
WG or WF series) or OSCON type capacitors can
achieve both ripple current capability together with having enough capacitance such that input voltage will not
sag too much. In this application, one OSCON
SVPC180M(180uF, 16V, 2.8A) and three 10uF(4A rms
current, X5R) ceramic capacitors are selected.
Choose RDROOP= 32kΩ.
A 1uH input inductor is recommended to slow down
the input current transient. Suppose power stage effi-
Over Voltage Protection
ciency is 0.8, then input current can estimated by
Over voltage protection is achieved by sensing the
output voltage through resistor divider. The sensed volt-
IINPUT =
age on PGSEN pin is compared with 120%*0.8V to generate the OVP signal. A small value capacitor is re-
IO U T × VOUT
60 A × 1 . 2 V
=
= 7 .5 A
0 . 8 × 12 V
η × VIN
In this application, Coilcraft DO3316P_102HC with
RMS rating 10A is chosen.
quired to connect to PGSEN pin also.
VOUT 1.2V
0.5
0.8V*120%
10k
PGSEN
20k
normlized
OVP
1nF
Singlephase
0.4
I RMS (IN ) 0.3
Iout
Two
phase
0.2
Figure 14 - Over voltage protection
Input Filter Selection
The selection criteria of input capacitor are voltage
0.1
0
Three
phase
0
0.1
0.2
0.3
0.4
0.5
D
rating and the RMS current rating. For conservative consideration, the capacitor voltage rating should be 1.5
times higher than the maximum input voltage. The RMS
Figure 15 - Normalized input RMS current vs.
duty cycle.
current rating of the input capacitor for multi-phase converter can be estimated from the above Figure 15.
First, determine the duty cycle of the converter (VO/
VIN). The ratio of input RMS current over output current
can be obtained. Then the total input RMS current can
Rev.4.8
05/06/08
17
NX2415
Power MOSFETs Selection
Soft Start and Enable Signal Operation
The NX2415 requires two N-Channel power
MOSFETs for each channels. The selection of
MOSFETs is based on maximum drain source voltage,
gate source voltage, maximum current rating, MOSFET
on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to
the overall converter efficiency. In this design example,
eight NTD60N02 are used. They have the following parameters: VDS=25V, ID =62A,RDSON =12mΩ,QGATE =9nC.
There are three factors causing the MOSFET power
loss:conduction loss, switching loss and gate driver loss.
The NX2415 will start operation only after Vcc and
PVcc have reached their threshold voltages and EN and
ENBUS have been enabled. The ENBUS pin can be programmed to turn on the converter at any input voltage.
The ENBUS pin has a threshold voltage of 1.6V.
Once the converter starts, there is a soft start sequence of 4082 steps between 0 and Vp. The ramp rate
is determined by the switching frequency.
dVO
VO
=
...(27)
dt
4082 × FS
The softstart time is calculated as followed:
Tstartup =
Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.
4082
FS
...(28)
It is proportional to frequency and is defined as:
Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS
Layout Considerations
...(24)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is
the low side gate source voltage. This power dissipation
should not exceed maximum power dissipation of the
driver device.
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
Conduction loss is simply defined as:
input capacitors, high-side MOSFET, low-side MOSFET,
PHCON =IOUT × D × RDS(ON) × K
2
PLCON =IOUT 2 × (1 − D) × RDS(ON) × K
PTOTAL =PHCON + PLCON
inductor and output capacitors. A noisy environment is
...(25)
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which in-
Where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency and should be selected for the worst case.
Conduction loss should not exceed package rating or
overall system thermal budget.
cludes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
Switching loss is mainly caused by crossover con-
capacitor, inductor, output capacitor and the MOSFETs
duction at the switching transition. The total switching
should be close to each other as possible. This helps to
loss can be approximated.
1
PSW = × VIN × IOUT × TSW × FS
2
reduce the EMI radiated by the power loop due to the
...(26)
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
TSW is the sum of TR and TF which can be found in
ripple current and a high frequency decoupling ceramic
mosfet datasheet, IOUT is output current, and FS is switch-
cap which usually is 1uF need to be practically touching
ing frequency. Swithing loss PSW is frequency depen-
the drain pin of the upper MOSFET, a plane connection
dent.
is a must.
3. The output capacitors should be placed as close
Rev.4.8
05/06/08
18
NX2415
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
12. Inductor current sense line should be connected directly to the inductor solder pad.
Rev.4.8
05/06/08
19
NX2415
MLPQ 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
Rev.4.8
05/06/08
20
NX2415
MLPQ 32 PIN 5 x 5 TAPE AND REEL INFORMATION
NOTE:
1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.
2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
Rev.4.8
05/06/08
21