P4C164L LOW POWER 8K x 8 STATIC CMOS RAM FEATURES Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —28-Pin 300 and 600 mil DIP —28-Pin 330 mil SOP VCC Current (Commercial/Industrial) — Operating: 55 mA — CMOS Standby: 3 µA Access Times —80/100 (Commercial or Industrial) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs DESCRIPTION Memory locations are specified on address pins A0 to A12. Reading is accomplished by device selection (CE1 low CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. The P4C164L is a 64K density low power CMOS static RAM organized as 8Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 80 ns and 100 ns are available. CMOS is utilized to reduce power consumption to a low level. Package options for the P4C164L include 28-pin 300 and 600 mil DIP and 28-pin 330 mil SOP packages. The P4C164L device provides asynchronous operation with matching access and cycle times. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM DIP (P5, P6), SOP (S5) TOP VIEW Document # SRAM116 REV B Revised June 2007 1 P4C164L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 4.5V ≤ VCC ≤ 5.5V Industrial (-40°C to 85°C) 4.5 ≤ VCC ≤ 5.5V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol Parameter Min Max Unit V CC Supply Voltage with Respect to GND -0.5 7.0 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current >200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Symbol Parameter Test Conditions Min 2.4 VOH Output High Voltage (I/O0 - I/O7) IOH = –1mA, VCC = 4.5V VOL Output Low Voltage (I/O0 - I/O7) IOL = 2.1mA VIH Input High Voltage Max Unit V 0.4 V VCC + 0.3 V -0.5 0.8 V 2.2 (3) VIL Input Low Voltage ILI Input Leakage Current GND ≤ VIN ≤ VCC Ind./Com. -2 +2 µA ILO Output Leakage Current GND ≤ VOUT ≤ VCC CE ≥ VIH Ind./Com. -2 +2 µA ISB VCC Current TTL Standby Current (TTL Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL 100 µA ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V or CE2 ≤ 0.2V 3 µA Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM116 REV B 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 11 P4C164L CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, F = 1.0 MHz) Test Conditions Max Unit Input Capacitance VIN = 0V 7 pF Output Capacitance VOUT = 0V 9 pF Symbol Parameter CIN COUT POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range ICC Dynamic Operating Current Ind. & Comm. * -80 -100 55 55 Unit mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -100 -80 Min Max Min Max Unit t RC Read Cycle Time tAA Address Access Time 80 100 ns t AC Chip Enable Access Time Output Hold from Address Change 80 100 ns tOH 80 100 ns 10 10 ns 10 10 ns tLZ Chip Enable to Output in Low Z t HZ Chip Disable to Output in High Z 30 30 ns tOE Output Enable Low to Data Valid 40 40 ns tOLZ Output Enable Low to Low Z t OHZ Output Enable High to High Z t PU Chip Enable to Power Up Time t PD Chip Disable to Power Down Time Document # SRAM116 REV B 5 5 20 20 0 ns 0 80 ns ns 100 ns Page 3 of 11 P4C164L READ CYCLE NO. 1 (OE OE CONTROLLED)(1) READ CYCLE NO. 2 (ADDRESS CONTROLLED) CE1,CE2 CONTROLLED) READ CYCLE NO. 3 (CE NOTES: Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM116 REV B 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. Page 4 of 11 P4C164L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) -80 Symbol Parameter Min Max -100 Min Max Unit tWC Write Cycle Time 80 100 ns tCW Chip Enable Time to End of Write 70 80 ns tAW Address Valid to End of Write 70 80 ns tAS Address Set-up Time 0 0 ns tWP Write Pulse Width 60 60 ns tAH Address Hold Time 0 0 ns tDW Data Valid to End of Write 40 40 ns t DH Data Hold Time 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 30 10 30 10 ns ns WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. Document # SRAM116 REV B 14. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 5 of 11 P4C164L CE CONTROLLED)(6) TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times TRUTH TABLE GND to 3.0V 3ns CE 1 CE2 OE WE I/O Power Standby H X X X High Z Standby Mode Input Timing Reference Level 1.5V Standby X L X X High Z Standby Output Timing Reference Level Output Load 1.5V DOUT Disabled L H H H High Z Active Read L H L H DOUT Active Write L H X L High Z Active See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the high speed of the P4C164L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. Document # SRAM116 REV B To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with DOUT to match 639Ω (Thevenin Resistance). Page 6 of 11 P4C164L DATA RETENTION CHARACTERISTICS Symbol Parameter Test Condition V DR VCC for Data Retention ICCDR Data Retention Current t CDR Chip Deselect to CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V Data Retention Time or VIN ≤ 0.2V tR † Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V 2.0 Operation Recovery Time V 1 CE1 ≥ VCC – 0.2V or Unit 1 3 3 µA 0 ns tRC§ ns *TA = +25°C § tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM116 REV B Page 7 of 11 P4C164L ORDERING INFORMATION SELECTION GUIDE The P4C164L is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Speed (ns) Package 80 100 Plastic DIP (300 mil) -80P3C -100P3C Plastic DIP (600 mil) -80P6C -100P6C Plastic SOP (450 mil) -80SC -100SC Plastic DIP (300 mil) -80P3I -100P3I Plastic DIP (600 mil) -80P6I -100P6I Plastic SOP (450 mil) -80SI -100SI Document # SRAM116 REV B Page 8 of 11 P4C164L Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P5 PLASTIC DUAL IN-LINE PACKAGE (300 mil) 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0° 15° P6 PLASTIC DUAL IN-LINE PACKAGE (600 mil) 28 (600 mil) Min Max 0.090 0.200 0.000 0.070 0.014 0.020 0.015 0.065 0.008 0.012 1.380 1.480 0.485 0.550 0.600 0.625 0.100 BSC 0.600 TYP 0.100 0.200 0° 15° Document # SRAM116 REV B Page 9 of 11 P4C164L Pkg # # Pins Symbol A A1 B C D e E H L α S5 SOIC/SOP SMALL OUTLINE IC PACKAGE (S) 28 (330 mil) Min Max 0.079 0.102 0.000 0.008 0.012 0.020 0.004 0.008 0.701 0.717 0.050 BSC 0.331 0.346 0.457 0.488 0.016 0.050 0° 8° Document # SRAM116 REV B Page 10 of 11 P4C164L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM116 P4C164L LOW POWER 8K x 8 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR Oct-05 JDB New Data Sheet A Aug-06 JDB Added Lead Free Designation B Jun-07 JDB Corrected SOP package details Document # SRAM116 REV B DESCRIPTION OF CHANGE Page 11 of 11