PHILIPS SA7016

INTEGRATED CIRCUITS
SA7016
1.3GHz low voltage fractional-N
synthesizer
Product specification
Supersedes data of 1999 Apr 20
1999 Nov 04
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
GENERAL DESCRIPTION
The SA7016 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 1.3 GHz.
The synthesizer has fully programmable main and reference
dividers. All divider ratios are supplied via a 3-wire serial
programming bus.
Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. VDDCP must be greater than or equal to VDD.
LOCK
1
16 PON
TEST
2
15 STROBE
VDD
3
14 DATA
GND
4
13 CLOCK
RFin+
5
12 REFin+
RFin–
6
11 REFin–
GNDCP
7
10 RSET
PHP
8
9
VDDCP
SR01505
The charge pump current (gain) is set by an external resistance at
the RSET pin. Only passive loop filters could be used; the charge
pump operates within a wide voltage compliance range to provide a
wider tuning range.
Figure 1. Pin Configuration
FEATURES
APPLICATIONS
• Low phase noise
• Low power
• Fully programmable main divider
• Internal fractional spurious compensation
• Hardware and software power down
• Split supply for VDD and VDDCP
• 350–1300 MHz wireless equipment
• Cellular phones
• Portable battery-powered radio equipment.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.7
–
5.5
V
VDD
Supply voltage
VDDCP
Analog supply voltage
2.7
–
5.5
V
IDDCP+IDD
Total supply current
–
6.2
7.3
mA
IDDCP+IDD
Total supply current in power-down mode
–
1
–
µA
fVCO
Input frequency
350
–
1300
MHz
fREF
Crystal reference input frequency
5
–
40
MHz
fPC
Maximum phase comparator frequency
–
4
MHz
Tamb
Operating ambient temperature
+85
°C
VDDCP ≥ VDD
–40
–
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
SA7016DH
1999 Nov 04
NAME
DESCRIPTION
VERSION
TSSOP16
Plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403–1
2
853–2160 22634
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
GND
4
13
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
ADDRESS DECODER
CONTROL
LATCH
CLOCK
DATA
STROBE
14
15
PUMP
CURRENT
SETTING
PUMP
BIAS
10
9
RSET
VDDCP
LOAD SIGNALS
LATCH
COMP
5
RFin+
RFin–
MAIN DIVIDER
6
PHASE
DETECTOR
8
PHP
AMP
7
GNDCP
LATCH
1
12
REFin+
REFin–
REFERENCE
DIVIDER
11
16
TEST
LOCK
PON
2
3
VDD
SR01506
Figure 2. Block Diagram
PINNING
SYMBOL
PIN
DESCRIPTION
LOCK
1
Lock detect output
TEST
2
Test (should be either grounded or
connected to VDD)
VDD
3
Digital supply
GND
4
Digital ground
RFin+
5
RF input to main divider
RFin–
6
RF input to main divider
GNDCP
7
Charge pump ground
PHP
8
Main normal chargepump
VDDCP
9
Charge pump supply voltage
RSET
10
External resistor from this pin to ground
sets the chargepump current
REFin–
11
Reference input
REFin+
12
Reference input
CLOCK
13
Programming bus clock input
DATA
14
Programming bus data input
STROBE
15
Programming bus enable input
PON
16
Power down control
1999 Nov 04
3
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
Digital supply voltage
–0.3
+5.5
V
VDDCP
Analog supply voltage
–0.3
+5.5
V
∆VDDCP–VDD
Difference in voltage between VDDCP and VDD (VDDCP ≥ VDD)
–0.3
+2.8
V
Vn
Voltage at pins 1, 2, 5, 6, 11 to 16
–0.3
VDD + 0.3
V
V1
Voltage at pin 8, 9
–0.3
VDDCP+ 0.3
V
∆VGND
Difference in voltage between GNDCP and GND (these pins should
be connected together)
–0.3
+0.3
V
Tstg
Storage temperature
–55
+125
_C
Tamb
Operating ambient temperature
–40
+85
_C
Tj
Maximum junction temperature
150
_C
Handling
Inputs and outputs are protected against electrostatic discharge in
normal handling. However, to be totally safe, it is desirable to take
normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
Rth j–a
1999 Nov 04
PARAMETER
Thermal resistance from junction to ambient in free air
4
VALUE
UNIT
120
K/W
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
CHARACTERISTICS
VDDCP = VDD = +3.0V, Tamb = +25°C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply; pins 3, 9
VDD
Digital supply voltage
2.7
–
5.5
V
VDDCP
Analog supply voltage
VDDCP = VDD
2.7
–
5.5
V
IDDTotal
Synthesizer operational total supply current
VDD = +3.0V
–
6.2
7.3
mA
IStandby
Total supply current in power-down mode
logic levels 0 or VDD
–
1
TBD
µA
350
–
1300
MHz
–18
–
0
RFin main divider input; pins 5, 6
fVCO
VCO input frequency
VRFin(rms)
AC-coupled input signal level
Rin (external) = Rs = 50Ω;
single-ended drive;
max. limit is indicative
@ 500 to 1300 MHz
ZIRFin
Input impedance (real part)
fVCO = 1.2 GHz
–
625
–
Ω
CIRFin
Typical pin input capacitance
fVCO = 1.2 GHz
–
1.0
–
pF
Nmain
Main divider ratio
512
–
65535
fPCmax
Maximum loop comparison frequency
–
–
4
MHz
5
–
40
MHz
360
–
1300
mVPP
indicative, not tested
dBm
Reference divider input; pins 11, 12
fREFin
Input frequency range from TCXO
VRFin
AC-coupled input signal level
single-ended drive;
max. limit is indicative
ZREFin
Input impedance (real part)
fREF = 20 MHz
–
10
–
kΩ
CREFin
Typical pin input capacitance
fREF = 20 MHz
–
1.0
–
pF
RREF
Reference division ratio
4
–
1023
6
7.5
15
kΩ
–
1.25
–
V
Charge pump current setting resistor input; pin 10
RSET
External resistor from pin to ground
VSET
Regulated voltage at pin
RSET=7.5 kΩ
Charge pump outputs (including fractional compensation pump); pin 8; RSET =7.5kΩ, FC=80
ICP
Charge pump current ratio to ISET1
IMATCH
Sink-to-source current matching
IZOUT
Output current variation versus VPH
ILPH
Charge pump off leakage current
VPH
Charge pump voltage compliance
1999 Nov 04
2
Current gain IPH/ISET
–15
+15
%
VPH=1/2 VDDCP.
–10
+10
%
VPH in compliance range
–10
+10
%
VPH=1/2 VCC
–10
+10
nA
VDDCP–0.8
V
0.7
5
–
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SYMBOL
PARAMETER
SA7016
CONDITIONS
MIN.
TYP.
MAX.
UNIT
GSM
–
–90
–
dBc/Hz
–
–85
–
dBc/Hz
Phase noise (RSET = 7.5 kΩ, CP=00)
Synthesizer’s contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset.
L(f)
Synthesizer’s contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.
fREF = 13MHz, TCXO,
fCOMP = 1MHz
indicative, not tested
TDMA
fREF = 19.44MHz, TCXO,
fCOMP = 240kHz
indicative, not tested
Interface logic input signal levels; pins 13, 14, 15, 16
VIH
HIGH level input voltage
0.7*VDD
–
VDD+0.3
V
VIL
LOW level input voltage
–0.3
–
0.3*VDD
V
ILEAK
Input leakage current
–0.5
–
+0.5
µA
–
–
0.4
V
VDD–0.4
–
–
V
logic 1 or logic 0
Lock detect output signal (in push/pull mode); pin 1
VOL
LOW level output voltage
Isink=2mA
VOH
HIGH level output voltage
Isource=–2mA
NOTES:
1. ISET =
V SET
R SET
bias current for charge pumps.
2. The relative output current variation is defined as:
DI OUT
(I 2–I 1)
+ 2.
; with V 1 + 0.7V, V 2 + V DDCP –0.8V (See Figure 3.)
I(I 2 ) I 1)I
I OUT
CURRENT
IZOUT
I2
I1
V1
V2
VPH
I2
I1
SR00602
Figure 3. Relative Output Current Variation
1999 Nov 04
6
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
fractional accumulator and is nulled by the fractional compensation
charge pump.
FUNCTIONAL DESCRIPTION
Main Fractional-N divider
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from –18 dBm to
0 dBm, and at frequencies as high as 1.3 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65536.
Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see Figure 4) determines which of the 5
output pulses are selected as the main (auxiliary) phase detector
input.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo Q set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1 to N + 1, the average division ratio over Q main divider cycles
(either 5 or 8) will be
Phase detector (see Figure 5)
The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Charge Pump table). The dead
zone (caused by finite time taken to switch the current sources on or
off) is cancelled by forcing the pumps ON for a minimum time at
every cycle (backlash time) providing improved linearity.
NF
Nfrac + N ) Q
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
SM=”000”
SM=”001”
SM=”010”
SM=”011”
TO
MAIN
PHASE
DETECTOR
SM=”100”
REFERENCE
INPUT
DIVIDE BY R
/2
/2
/2
/2
SA=”100”
SA=”011”
SA=”010”
TO
AUXILIARY
PHASE
DETECTOR
SA=”001”
SA=”000”
SR01415
Figure 4. Reference Divider
1999 Nov 04
7
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
VCC
“1”
fREF
REF DIVIDER
P–TYPE
CHARGE PUMP
P
D
Q
CLK
R
R
τ
“1”
AUX/MAIN
DIVIDER
D
IPH
R
N–TYPE
CHARGE PUMP
CLK
Q
X
N
GND
fREF
R
X
τ
P
τ
N
IPH
SR02103
Figure 5. Phase Detector Structure with Timing
1999 Nov 04
8
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 6)
SA7016
The compensation is done by sourcing a small current, ICOMP, see
Figure 7, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, RSET, programming or speed-up operation.
For a given charge pump,
The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin RSET in conjunction with bits CP0,
CP1 in the B-word (see table of charge pump ratios). The fractional
compensation is derived from the current at RSET, the contents of
the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.
Principle of Fractional Compensation
ICOMP = ( IPUMP / 128 ) * ( FDAC / 5*128) * FRD
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If ICOMP is the
compensation current and IPUMP is the pump current, then for each
charge pump:
FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and
80 for FMOD = 0 (modulo 8).
IPUMP_TOTAL = IPUMP + ICOMP.
REFERENCE R
MAIN M
DIVIDE RATIO
N
DETECTOR
OUTPUT
N
N+1
2
N
4
N+1
3
1
0
ACCUMULATOR
FRACTIONAL
COMPENSATION
CURRENT
PULSE
WIDTH
MODULATION
mA
OUTPUT ON
PUMP
µA
PULSE LEVEL
MODULATION
SR01416
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 6. Waveforms for NF = 2 Modulo 5 → fraction = 2/5
fRF
1930.140 MHz
MAIN DIVIDER
N = 8042
FRACTIONAL
ACCUMULATOR
240.016 kHz
NF
ICOMP
IPUMP
fREF
240 kHz
FMOD
LOOP FILTER
& VCO
SR01682
Figure 7. Current Injection Concept
1999 Nov 04
9
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
Charge pump currents
CP0
IPHP
IPHP–SU
0
3xISET
15xlSET
1
1xlSET
5xlSET
NOTES:
1. ISET=VSET/RSET: bias current for charge pumps.
2. IPHP–SU is the total current at pin PHP during speed up condition.
Lock Detect
Power-down mode
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than 1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
‘0’) is indicated when both counters are powered down.
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
1999 Nov 04
10
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
Serial bus timing characteristics. See Figure 8.
VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
tr
Input rise time
–
10
40
ns
tf
Input fall time
–
10
40
ns
Tcy
Clock period
100
–
–
ns
40
–
–
ns
1/fCOMP
–
–
ns
20
–
–
ns
Enable programming; STROBE
tSTART
Delay to rising clock edge
tW
Minimum inactive pulse width
tSU;E
Enable set-up time to next clock edge
Register serial input data; DATA
tSU;DAT
Input data to clock set-up time
20
–
–
ns
tHD;DAT
Input data to clock hold time
20
–
–
ns
Application information
tSU;DAT
tHD;DAT
tr
Tcy
tf
tSU;E
CLK
DATA
ADDRESS
MSB
LSB
STROBE
tw
tSTART
SR01417
Figure 8. Serial Bus Timing Diagram
1999 Nov 04
11
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
SA7016
Data format
Table 1. Format of programmed data
LAST IN
MSB
p23
p22
SERIAL PROGRAMMING FORMAT
p21
p20
../..
FIRST IN LSB
../..
p1
p0
Table 2. A word, length 24 bits
LAST IN
MSB
Address
0
fmod
0
Fractional-N
FIRST IN
LSB
Main Divider ratio
Spare
FM
NF2
NF1
NF0
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
SP1
SP2
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
Default:
A word select
Fixed to 00.
Fractional Modulus select
FM 0 = modulo 8, 1 = modulo 5.
Fractional-N Increment
NF2..0 Fractional N Increment values 000 to 111.
N-Divider
N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
Table 3. B word, length 24 bits
Address
0
1
LOCK
PD
CP
R6
R5
R4
R3
R2
R1
R0
LO
MAIN
CP0
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
SP3
1
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
REFERENCE DIVIDER
R9
R8
R7
0
0
0
Default:
SPARE
FRACTIONAL COMPENSATION DAC
B word select
Fixed to 01
R-Divider
R0..R9, Reference divider values 4 to 1023 allowed for divider ration.
Charge pump current
Ratio
CP0: Charge pump current ratio, see table of charge pump currents.
Lock detect output
L0
0 Main lock detect signal present at the LOCK pin (push/pull).
1 Main lock detect signal present at the LOCK pin (open drain).
When main loop is in power down mode, the lock indicator is low.
Power down
Main = 1: power to main divider, reference divider, main charge pumps, Main = 0 to power down.
Fractional Compensation
FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Table 4. D word, length 24 bits
Address
1
1
Default:
SYNTHESIZER TEST
BITS
0
–
–
–
–
–
Tspu
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Tspu: Speed up = 1
1999 Nov 04
SYNTHESIZER TEST BITS
Forces the main charge pumps in speed-up mode all the time.
NOTE: All test bits must be set to 0 for normal operation.
12
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
600
800
ISET = 206.67 mA
600
ISET = 165.33 mA
400
400
Vdd = 3.0 V
ISET = 165.33 µA
TEMP = 85°C
TEMP = 25°C
ISET = 103.33 mA
200
ISET = 51.67 mA
200
Icp (uA)
Icp (uA)
SA7016
0
–200
ISET = 51.67 mA
–400
ISET = 103.33 mA
–600
ISET = 165.33 mA
0
TEMP = –40°C
–200
–400
ISET = 206.67 mA
–800
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
–600
3
0
0.25 0.5 0.75
1
COMPLIANCE VOLTAGE (V)
1.25 1.5 1.75
2
2.25 2.5 2.75
3
SR01911
SR01912
Figure 9. Php Charge Pump Output vs. ISET
(CP = 0, TEMP = 25_C)
250
200
150
Figure 10. Php Charge Pump Output vs. Temperature
(CP = 0; VDD = 3.0 V; ISET = 165.33 mA)
ISET = 206.67 mA
200
ISET = 165.33 mA
150
ISET = 103.33 mA
100
ISET = 51.67 mA
50
Icp (uA)
Icp (uA)
100
0
–50
ISET = 51.67 mA
–100
–200
50
0
TEMP = –40°C
–100
ISET = 165.33 mA
–150
ISET = 206.67 mA
–250
Vdd = 3.0 V
ISET = 165.33 µA
TEMP = 85°C
TEMP = 25°C
–50
ISET = 103.33 mA
–150
–200
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR01913
SR01914
Figure 11. Php Charge Pump Output vs. ISET
(CP = 1; TEMP = 25_C)
Figure 12. Php Charge Pump Output vs. Temperature
(CP = 1; VDD = 3.0 V; ISET = 165.33 mA)
3000
3500
ISET = 206.67 mA
ISET = 165.33 mA
2500
2000
ISET = 103.33 mA
1500
1000
Icp (uA)
ISET = 51.67 mA
Icp (uA)
3.25 3.5
COMPLIANCE VOLTAGE (V)
500
0
–500
ISET = 51.67 mA
–1500
TEMP = 85_C
TEMP = 25_C
TEMP = –40_C
0
–1000
ISET = 103.33 mA
–2500
–2000
ISET = 165.33 mA
ISET = 206.67 mA
–3500
0
0.25
0.5
0.75
1
–3000
1.25
1.5 1.75
2
2.25 2.5 2.75
3
0
COMPLIANCE VOLTAGE (V)
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5
COMPLIANCE VOLTAGE (V)
SR01915
SR01916
Figure 13. Php–su Charge Pump Output vs. ISET
(CP = 0; TEMP = 25_C)
1999 Nov 04
0.25 0.5 0.75
Figure 14. Php–su Charge Pump Output vs. Temperature
(CP = 0; VDD = 3.0 V; ISET = 165.33 mA)
13
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
1500
1000
1000
ISET = 206.67 mA
800
ISET = 165.33 mA
600
ISET = 103.33 mA
500
ISET = 51.67 mA
Icp (uA)
Icp (uA)
SA7016
0
ISET = 51.67 mA
–500
–1000
400
TEMP = 85_C
TEMP = 25_C
200
TEMP = –40_C
0
–200
ISET = 103.33 mA
–400
ISET = 165.33 mA
ISET = 206.67 mA
–600
–800
–1500
–1000
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25
2.5 2.75
3
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR01917
SR01918
Figure 15. Php–su Charge Pump Output vs. ISET
(CP = 1; TEMP = 25_C)
Figure 16. Php–su Charge Pump Output vs. Temperature
(CP = 1; VDD = 3.0 V; ISET = 165.33 mA)
0
–10
VDD = 5.50 V
VDD = 3.75 V
–15
VDD = 3.00 V
–20
VDD = 2.70 V
MINIMUM SIGNAL INPUT LEVEL (dBm)
MINIMUM SIGNAL INPUT LEVEL (dBm)
0
–5
–25
–30
–35
–40
–45
–50
–55
–60
0
200
400
600
800
1000
1200
1400
1600
1800
–5
–10
–15
–20
+85_C
–25
+25_C
–30
–35
–40_C
–40
–45
–50
2000
0
200
400
600
FREQUENCY (MHz)
800
1000
1200
1400
1600
1800
SR01929
SR01930
Figure 18. Main Divider Input Sensitivity vs. Frequency and
Temperature (VDD = 3.00 V)
MINIMUM SIGNAL POWER LEVEL (dBm)
Figure 17. Main Divider Input Sensitivity vs. Frequency and
Supply Voltage (TEMP = 25_C)
MINIMUM SIGNAL POWER LEVEL (dBm)
2000
FREQUENCY (MHz)
0
–5
–10
VDD = 5.00 V
VDD = 3.75 V
–15
VDD = 3.00 V
–20
VDD = 2.70 V
–25
–30
–35
–40
–45
–50
0
–5
TEMP = +85_C
–10
TEMP = +25_C
–15
TEMP = –40_C
–20
–25
–30
–35
–40
–45
–50
–55
–55
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
70
SR01921
10
15
20
25
30
35
40
45
50
55
60
65
70
SR01922
Figure 19. Reference Divider Input Sensitivity vs. Frequency
and Supply Voltage (TEMP = 25_C)
1999 Nov 04
5
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Reference Divider Input Sensitivity vs. Frequency
and Temperature (VDD = 3.00 V)
14
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N synthesizer
8.5
I TOTAL (mA)
8
7.5
7
6.5
TEMP = +85_C
6
TEMP = +25_C
TEMP = –40_C
5.5
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V)
SR01931
Figure 21. Current Supply Over VDD
1999 Nov 04
15
SA7016
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N frequency
synthesizer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
1999 Nov 04
16
SA7016
SOT403-1
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N frequency
synthesizer
NOTES
1999 Nov 04
17
SA7016
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N frequency
synthesizer
SA7016
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 11-99
Document order number:
1999 Nov 04
18
9397 750 06565