SN74LVC2G66-Q1 www.ti.com SCES829A – JUNE 2011 – REVISED JULY 2012 DUAL BILATERAL ANALOG SWITCH Check for Samples: SN74LVC2G66-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B 1.65-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V High On-Off Output Voltage Ratio High Degree of Linearity High Speed, Typically 0.5 ns • • (VCC = 3 V, CL = 50 pF) Rail-to-Rail Input/Output Low On-State Resistance, Typically ≉6 Ω (VCC = 4.5 V) DCU PACKAGE (TOP VIEW) 1A 1B 2C GND 1 8 VCC 2 7 3 6 4 5 1C 2B 2A DESCRIPTION The design of this dual bilateral analog switch is for 1.65-V to 5.5-V VCC operation. The SN74LVC2G66-Q1 can handle both analog and digital signals. The device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction. Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated SN74LVC2G66-Q1 SCES829A – JUNE 2011 – REVISED JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PACKAGE (1) TA –40°C to 125°C (1) (2) VSSOP – DCU ORDERABLE PART NUMBER Reel of 3000 SN74LVC2G66QDCURQ1 TOP-SIDE MARKING (2) CAY_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DCU: The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE (EACH SECTION) CONTROL INPUT (C) SWITCH L Off H On LOGIC DIAGRAM, EACH SWITCH (POSITIVE LOGIC) 1A 1C 1 2 1B 7 One of Two Switches ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.5 (3) (2) (3) (4) UNIT VO Switch I/O voltage range IIK Control input clamp current VI < 0 –50 mA II/OK I/O port diode current VI/O < 0 or VI/O > VCC –50 mA IT On-state switch current VI/O = 0 to VCC ±50 mA ±100 mA Continuous current through VCC or GND Tstg Storage temperature range ESD ratin gs Human-Body Model (HBM) AEC-Q100 Classification Level H2 (1) (2) (3) (4) 2 –65 Charged-Device Model (CDM) AEC-Q100 Classification Level C3B V 150 °C 2 kV 750 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. Exceeding the input and output negative-voltage ratings is permitted when in observance of the input and output clamp-current ratings. This limit on this value is limited 5.5 V maximum. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 SN74LVC2G66-Q1 www.ti.com SCES829A – JUNE 2011 – REVISED JULY 2012 THERMAL INFORMATION THERMAL METRIC SN74LVC2G66Q1 (1) DCU UNIT 8 PINS (2) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance (3) θJB Junction-to-board thermal resistance (4) (5) 204.4 °C/W 77 °C/W 83.2 °C/W ψJT Junction-to-top characterization parameter 7.1 °C/W ψJB Junction-to-board characterization parameter (6) 82.7 °C/W θJCbot Junction-to-case (bottom) thermal resistance (7) N/A °C/W (1) (2) (3) (4) (5) (6) (7) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS (1) MIN MAX VCC Supply voltage 1.65 5.5 V VI/O I/O port voltage 0 VCC V VCC = 1.65 V to 1.95 V VIH High-level input voltage, control input VCC × 0.65 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC = 1.65 V to 1.95 V VIL Low-level input voltage, control input VI Control input voltage Input transition rise/fall time TA Operating free-air temperature VCC × 0.35 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 V VCC × 0.3 0 5.5 VCC = 1.65 V to 1.95 V 20 VCC = 2.3 V to 2.7 V 20 VCC = 3 V to 3.6 V 10 VCC = 4.5 V to 5.5 V (1) V VCC = 2.3 V to 2.7 V VCC = 4.5 V to 5.5 V Δt/Δv UNIT V ns/V 10 –40 125 °C Hold all unused inputs of the device at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 Submit Documentation Feedback 3 SN74LVC2G66-Q1 SCES829A – JUNE 2011 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ron TEST CONDITIONS On-state switch resistance ron(p) Peak on-state resistance VI = VCC or GND, VC = VIH (see Figure 1 and Figure 2) VI = VCC to GND, VC = VIH (see Figure 1 and Figure 2) VCC MIN TYP (1) MAX IS = 4 mA 1.65 V 12.5 35 IS = 8 mA 2.3 V 9 30 IS = 24 mA 3V 7.5 20 IS = 32 mA 4.5 V 6 15 IS = 4 mA 1.65 V 85 120 (1) IS = 8 mA 2.3 V 22 30 (1) IS = 24 mA 3V 12 25 IS = 32 mA 4.5 V 7.5 20 IS = 4 mA 1.65 V 10 IS = 8 mA 2.3 V 8 IS = 24 mA 3V 6 IS = 32 mA 4.5 V UNIT Ω Ω Difference of on-state resistance between switches VI = VCC to GND, VC = VIH (see Figure 1 and Figure 2) IS(off) Off-state switch leakage current VI = VCC and VO = GND or VI = GND and VO = VCC, VC = VIL (see Figure 3) 5.5 V IS(on) On-state switch leakage current VI = VCC or GND, VC = VIH, VO = Open (see Figure 4) 5.5 V II Control input current VC = VCC or GND 5.5 V ICC Supply current VC = VCC or GND 5.5 V ΔICC Supply-current change VC = VCC – 0.6 V 5.5 V Cic Control input capacitance 5V 3.5 pF Cio(off) Switch input/output capacitance 5V 6 pF Cio(on) Switch input/output capacitance 5V 14 pF Δron (1) Ω 5 ±2 ±0.1 (1) ±2 ±0.1 (1) ±1 ±0.1 (1) 15 1 (1) 500 μA μA μA μA μA TA = 25°C SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5) PARAMETER (1) (2) 4 FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX UNIT ten (1) C A or B 2.3 12 1.6 7.5 1.5 6.4 1.3 5.9 ns tdis (2) C A or B 2.2 12.5 1.2 7.9 2 9.2 1.1 8.3 ns tPZL and tPZH are the same as ten. tPLZ and tPHZ are the same as tdis. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 SN74LVC2G66-Q1 www.ti.com SCES829A – JUNE 2011 – REVISED JULY 2012 ANALOG SWITCH CHARACTERISTICS TA = 25°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC CL = 50 pF, RL = 600 Ω, fin = sine wave (see Figure 6) Frequency response (switch on) A or B B or A CL = 5 pF, RL = 50 Ω, fin = sine wave (see Figure 6) CL = 50 pF, RL = 600 Ω, fin = 1 MHz (sine wave) (see Figure 7) (1) Crosstalk (between switches) A or B B or A CL = 5 pF, RL = 50 Ω, fin = 1 MHz (sine wave) (see Figure 7) Crosstalk (control input to signal output) C CL = 50 pF, RL = 600 Ω, fin = 1 MHz (square wave) (see Figure 8) A or B CL = 50 pF, RL = 600 Ω, fin = 1 MHz (sine wave) (see Figure 9) Feedthrough attenuation (switch off) A or B B or A CL = 5 pF, RL = 50 Ω, fin = 1 MHz (sine wave) (see Figure 9) CL = 50 pF, RL = 10 kΩ, fin = 1 kHz (sine wave) (see Figure 10) Sine-wave distortion A or B B or A CL = 50 pF, RL = 10 kΩ, fin = 10 kHz (sine wave) (see Figure 10) (1) TYP 1.65 V 35 2.3 V 120 3V 175 4.5 V 195 1.65 V >300 2.3 V >300 3V >300 4.5 V >300 1.65 V –58 2.3 V –58 3V –58 4.5 V –58 1.65 V –42 2.3 V –42 3V –42 4.5 V –42 1.65 V 35 2.3 V 50 3V 70 4.5 V 100 1.65 V –58 2.3 V –58 3V –58 4.5 V –58 1.65 V –42 2.3 V –42 3V –42 4.5 V –42 1.65 V 0.1 2.3 V 0.025 3V 0.015 4.5 V 0.01 1.65 V 0.15 2.3 V 0.025 3V 0.015 4.5 V 0.01 UNIT MHz dB mV dB % Adjust fin voltage to obtain 0 dBm at input. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power-dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 8 9 9.5 11 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 UNIT Submit Documentation Feedback pF 5 SN74LVC2G66-Q1 SCES829A – JUNE 2011 – REVISED JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC VCC B or A A or B VI = VCC or GND VO C VC VIH (On) GND IS r on + V VI * VO W IS VI - VO Figure 1. On-State Resistance Test Circuit 100 VCC = 1.65 V ron - Ω VCC = 2.3 V VCC = 3.0 V 10 1 0.0 VCC = 4.5 V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN - V Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC 6 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 SN74LVC2G66-Q1 www.ti.com SCES829A – JUNE 2011 – REVISED JULY 2012 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC VI B or A A or B A VIL VO C VC (Off) GND Condition 1: VI = GND, VO = VCC Condition 2: VI = VCC, VO = GND Figure 3. Off-State Switch Leakage-Current Test Circuit VCC VCC VI = VCC or GND B or A A or B A VO VO = Open VIH C VC (On) GND Figure 4. On-State Leakage-Current Test Circuit Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 Submit Documentation Feedback 7 SN74LVC2G66-Q1 SCES829A – JUNE 2011 – REVISED JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC VCC VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 VCC/2 VCC/2 2 × VCC 2 × VCC 2 × VCC 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM Output VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 5. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 SN74LVC2G66-Q1 www.ti.com SCES829A – JUNE 2011 – REVISED JULY 2012 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC 0.1 µF VO C VC VIH 50 Ω fin B or A A or B RL (On) GND CL VCC/2 RL/CL: 600 Ω/50 pF RL/CL: 50 Ω/5 pF Figure 6. Frequency Response (Switch On) VCC VCC 0.1 µF Rin 600 Ω fin 1B or 1A 1A or 1B RL 600 Ω C VC VIH 50 Ω VO1 CL 50 pF (On) VCC/2 2B or 2A 2A or 2B Rin 600 Ω VO2 RL 600 Ω C VC VIL (Off) GND CL 50 pF VCC/2 20log10(VO2/VI1) or 20log10(VO1/VI2) Figure 7. Crosstalk (Between Switches) Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 Submit Documentation Feedback 9 SN74LVC2G66-Q1 SCES829A – JUNE 2011 – REVISED JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC B or A A or B VCC/2 VO Rin 600 Ω CL 50 pF RL 600 Ω C VC 50 Ω GND VCC/2 Figure 8. Crosstalk (Control Input, Switch Output) VCC VCC 0.1 µF fin 50 Ω B or A A or B RL VIL C VC VO RL (Off) GND VCC/2 CL VCC/2 RL/CL: 600 Ω/50 pF RL/CL: 50 Ω/5 pF Figure 9. Feedthrough (Switch Off) 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 SN74LVC2G66-Q1 www.ti.com SCES829A – JUNE 2011 – REVISED JULY 2012 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC 10 µF fin 600 Ω VIH 10 µF B or A A or B VO RL 10 kΩ C VC (On) GND CL 50 pF VCC/2 VCC = 1.65 V, VI = 1.4 VP-P VCC = 2.3 V, VI = 2 VP-P VCC = 3 V, VI = 2.5 VP-P VCC = 4.5 V, VI = 4 VP-P Figure 10. Sine-Wave Distortion Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC2G66-Q1 Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2012 PACKAGING INFORMATION Orderable Device SN74LVC2G66QDCURQ1 Status (1) Package Type Package Drawing ACTIVE US8 DCU Pins Package Qty 8 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LVC2G66-Q1 : • Catalog: SN74LVC2G66 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC2G66QDCURQ1 Package Package Pins Type Drawing US8 DCU 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 2.25 B0 (mm) K0 (mm) P1 (mm) 3.35 1.05 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC2G66QDCURQ1 US8 DCU 8 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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