RENESAS TBB1008

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
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TBB1008
Twin Build in Biasing Circuit MOS FET IC
VHF/UHF RF Amplifier
ADE-208-1599 (Z)
Rev.0
Jun. 2002
Features
• Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
• Suitable for World Standard Tuner RF amplifier.
• Very useful for total tuner cost reduction.
• Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0
conditions.
• Provide mini mold packages; CMPAK-6
Outline
CMPAK-6
6
5
4
2
1
Notes:
1.
2.
3
1. Gate-1(1)
2. Source
3. Drain(1)
4. Drain(2)
5. Gate-2
6. Gate-1(2)
Marking is “HM”.
TBB1008 is individual type number of HITACHI TWIN BBFET.
TBB1008
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
VDS
6
V
Gate1 to source voltage
VG1S
+6
-0
V
Gate2 to source voltage
VG2S
+6
-0
V
Drain current
ID
30
mA
250
mW
*3
Channel power dissipation
Pch
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Notes: 3. Value on the glass epoxy board (50 mm × 40 mm × 1 mm).
Rev.0, Jun. 2002, page 2 of 12
TBB1008
Electrical Characteristics
The below specification are applicable for UHF unit (FET1)
(Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS
6
—
—
V
ID = 200 µA, VG1S = VG2S = 0
Gate1 to source breakdown
voltage
V(BR)G1SS
+6
—
—
V
IG1 = +10 µA, VG2S = VDS = 0
Gate2 to source breakdown
voltage
V(BR)G2SS
+6
—
—
V
IG2 = +10 µA, VG1S = VDS = 0
Gate1 to source cutoff current IG1SS
—
—
+100
nA
VG1S = +5 V, VG2S = VDS = 0
Gate2 to source cutoff current IG2SS
—
—
+100
nA
VG2S = +5 V, VG1S = VDS = 0
Gate1 to source cutoff voltage VG1S(off)
0.5
0.7
1.0
V
VDS = 5 V, VG2S = 4 V, ID = 100 µA
Gate2 to source cutoff voltage VG2S(off)
0.5
0.7
1.0
V
VDS = 5 V, VG1S = 5 V, ID = 100 µA
Drain current
ID(op)
13
17
21
mA
VDS = 5 V, VG1 = 5 V
VG2S = 4 V, RG = 100 kΩ
Forward transfer admittance
|yfs|
21
26
32
mS
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 100 kΩ, f = 1 kHz
Input capacitance
Ciss
1.4
1.8
2.2
pF
VDS = 5 V, VG1 = 5 V
Output capacitance
Coss
1.0
1.4
1.8
pF
VG2S =4 V, RG = 100 kΩ
Reverse transfer capacitance
Crss
—
0.02
0.04
pF
f = 1 MHz
Power gain
PG
16
21
—
dB
VDS = VG1 = 5 V, VG2S = 4 V
RG = 100 kΩ, f = 900 MHz
Zi = S11*, Zo = S22* (:PG)
Noise figure
NF
—
1.7
2.5
dB
Zi = S11opt (:NF)
Rev.0, Jun. 2002, page 3 of 12
TBB1008
The below specification are applicable for VHF unit (FET2)
(Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS
6
—
—
V
ID = 200 µA, VG1S = VG2S = 0
Gate1 to source breakdown
voltage
V(BR)G1SS
+6
—
—
V
IG1 = +10 µA, VG2S = VDS = 0
Gate2 to source breakdown
voltage
V(BR)G2SS
+6
—
—
V
IG2 = +10 µA, VG1S = VDS = 0
Gate1 to source cutoff current IG1SS
—
—
+100
nA
VG1S = +5 V, VG2S = VDS = 0
Gate2 to source cutoff current IG2SS
—
—
+100
nA
VG2S = +5 V, VG1S = VDS = 0
Gate1 to source cutoff voltage VG1S(off)
0.5
0.75
1.0
V
VDS = 5 V, VG2S = 4 V, ID = 100 µA
Gate2 to source cutoff voltage VG2S(off)
0.5
0.75
1.0
V
VDS = 5 V, VG1S = 5 V, ID = 100 µA
Drain current
ID(op)
16
20
24
mA
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 100 kΩ
Forward transfer admittance
|yfs|
27
32
38
mS
VDS = 5 V, VG1 = 5 V, VG2S =4 V
RG = 100 kΩ, f = 1 kHz
Input capacitance
Ciss
2.3
2.7
3.1
pF
VDS = 5 V, VG1 = 5 V
Output capacitance
Coss
1.4
1.8
2.2
pF
VG2S =4 V, RG = 100 kΩ
Reverse transfer capacitance
Crss
—
0.03
0.05
pF
f = 1 MHz
Power gain
PG
24
29
—
dB
VDS = VG1 = 5 V, VG2S = 4 V
Noise figure
NF
—
1.2
1.7
dB
RG = 100 kΩ, f = 200 MHz
Rev.0, Jun. 2002, page 4 of 12
TBB1008
Test Circuits
• DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG)
• Measurment of FET1
Gate 2
VG2
Open
Open
RG
A
Gate 1
VG1
ID
Drain
VD
Source
• Measurment of FET2
VG2
Gate 2
RG
Drain
Gate 1
A
ID
VD
VG1
Open
Open
Source
Rev.0, Jun. 2002, page 5 of 12
TBB1008
• Equivalent Circuit
No.1
No.6
Gate-1(1)
Gate-1(2)
BBFET-(1)
BBFET-(2)
No.2
No.5
Source
Gate-2
No.3
No.4
Drain(1)
Drain(2)
• 200 MHz Power Gain, Noise Figure Test Circuit
1000 p
1000 p
47 k
Input (50 Ω)
VT
VG2
VT
1000 p
47 k
1000 p
47 k
TWINBBFET
1000 p
L2
L1
10p max
1000 p
1000 p
36 p
Output (50 Ω)
1SV70
RG
RFC
100k
1SV70
1000 p
V D = V G1
L1 : φ1 mm Enameled Copper Wire,Inside dia 10 mm, 2 Turns
L2 : φ1 mm Enameled Copper Wire,Inside dia 10 mm, 2 Turns
RFC : φ 1mm Enameled Copper Wire,Inside dia 5 mm, 2 Turns
Rev.0, Jun. 2002, page 6 of 12
Unit : Resistance (Ω)
Capacitance (F)
Typical Output Characteristics (FET1)
25
200
100
0
50
100
150
Ambient Temperature
kΩ
68
kΩ
kΩ
0
15
10
kΩ
0
12
kΩ
0
15
10
0k
18
5
0
200
G=
20
R
300
V G2S = 4 V
V G1 = VDS
82
I D (mA)
400
Maximum Channel Power
Dissipation Curve
Drain Current
Channel Power Dissipation
Pch* (mW)
TBB1008
Ta (°C)
1
2
3
Drain to Source Voltage
Ω
4
5
V DS (V)
* Value on the glass epoxy board (50mm × 40mm × 1mm)
20
Forward Transfer Admittance |y fs | (mS)
Drain Current
I D (mA)
25
Drain Current vs.
Gate1 Voltage (FET1)
V DS = 5 V
R G = 100 kΩ
4V
15
3V
10
2V
5
VG2S = 1 V
0
1
2
Gate1 Voltage
3
V G1
4
(V)
5
50
40
Forward Transfer Admittance
vs. Gate1 Voltage (FET1)
V DS = 5 V
V G2S = 4 V
30
R G = 68 k Ω
100 kΩ
150 kΩ
20
10
0
1
2
Gate1 Voltage
3
4
5
V G1 (V)
Rev.0, Jun. 2002, page 7 of 12
TBB1008
Drain Current vs.
Gate Resistance (FET1)
4
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
25
20
15
10
5
0
10
20
50
100 200
Input Capacitance Ciss (pF)
Drain Current I D (mA)
30
Input Capacitance vs.
Gate2 to Source Voltage (FET1)
V DS = 5 V
V G1 = 5 V
R G = 100 kΩ
f = 1 MHz
1
0
1
2
3
4
Gate Resistance R G (kΩ)
Gate2 to Source Voltage V G2S (V)
Typical Output Characteristics (FET2)
Drain Current vs.
Gate1 Voltage (FET2)
25
kΩ
0
15 Ω
0k
18
10
5
I D (mA)
Drain Current
12
0
15
kΩ
10
0
kΩ
kΩ
68
82
G=
20
kΩ
V G2S = 4 V
V G1 = VDS
R
I D (mA)
2
0
500 1000
25
Drain Current
3
20
V DS = 5 V
R G = 100 kΩ
4V
3V
15
2V
10
5
VG2S = 1 V
0
1
2
3
Drain to Source Voltage
Rev.0, Jun. 2002, page 8 of 12
4
5
V DS (V)
0
1
2
Gate1 Voltage
3
V G1
4
(V)
5
50
30
V DS = 5 V
V G2S = 4 V
40
R G = 68 k Ω
100 kΩ
30
150 kΩ
20
10
0
1
2
3
Gate1 Voltage
4
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
25
20
15
10
5
0
10
5
V G1 (V)
20
50
100 200
500 1000
Gate Resistance R G (kΩ)
Power Gain vs.
Gate Resistance (FET2)
Input Capacitance vs.
Gate2 to Source Voltage (FET2)
40
4
35
Power Gain PG (dB)
Input Capacitance Ciss (pF)
Drain Current vs.
Gate Resistance (FET2)
Forward Transfer Admittance
vs. Gate1 Voltage (FET2)
Drain Current I D (mA)
Forward Transfer Admittance |y fs | (mS)
TBB1008
3
2
V DS = 5 V
V G1 = 5 V
R G = 100 kΩ
f = 1 MHz
1
0
0
1
30
25
20
15
2
3
Gate2 to Source Voltage V G2S (V)
4
10
10
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
f = 200 MHz
20
50 100 200
500 1000
Gate Resistance R G (kΩ)
Rev.0, Jun. 2002, page 9 of 12
TBB1008
Noise Figure vs.
Gate Resistance (FET2)
Gain Reduction vs.
Gate2 to Source Voltage (FET2)
0
3
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
f = 200 MHz
Gain Reduction GR (dB)
Noise Figure NF (dB)
4
2
1
0
10
10
20
30
40
50
20
50
100 200
500 1000
Gate Resistance R G (kΩ)
Rev.0, Jun. 2002, page 10 of 12
V DS = V G1 = 5 V
R G = 100 kΩ
4
3
2
1
Gate2 to Source Voltage V G2S (V)
0
TBB1008
Package Dimensions
As of January, 2002
(0.65)
+ 0.1
0.15 – 0.05
0 – 0.1
0.9 ± 0.1
+ 0.1
– 0.05
(0.2)
6-0.2
(0.65)
2.1 ± 0.3
2.0 ± 0.2
1.3 ± 0.2
(0.425) 1.25 ± 0.1 (0.425)
Unit: mm
Hitachi Code
JEDEC
JEITA
Mass (reference value)
CMPAK-6
—
Conforms
0.006 g
Rev.0, Jun. 2002, page 11 of 12
TBB1008
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Sales Offices
Hitachi, Ltd.
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
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(America) Inc.
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San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
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Postfach 201, D-85619 Feldkirchen
Germany
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Fax: <49> (89) 9 29 30 00
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(Taipei Branch Office)
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Telex : 23222 HAS-TP
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Fax : <852>-2730-0281
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Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 6.0
Rev.0, Jun. 2002, page 12 of 12