PHILIPS TDA6651ATT/C3/S2

TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer for hybrid
terrestrial tuner (digital and analog)
Rev. 02 — 2 February 2007
Product data sheet
1. General description
The TDA6650ATT; TDA6651ATT is a programmable 3-band mixer/oscillator and low
phase noise PLL synthesizer intended for pure 3-band tuner concepts applied to hybrid
(digital and analog) or digital-only terrestrial and cable TV reception.
Table 1.
Different versions are available, depending on the target application[1]
Application
Type version
Analog and digital (Hybrid ISDB-T/NTSC Japan)
TDA6650ATT/C3
TDA6651ATT/C3
Digital only (ISDB-T)
TDA6650ATT/C3/S2
TDA6651ATT/C3/S2
TDA6651ATT/C3/S3
[1]
See Table 20 “Characteristics” for differences between TDA6651ATT/C3/S2 and TDA6651ATT/C3/S3.
The device includes three double balanced mixers for low, mid and high bands, three
oscillators for the corresponding bands, a switchable IF amplifier, a wideband AGC
detector and a low noise PLL synthesizer. The frequencies of the three bands are shown
in Table 2. Two pins are available between the mixer output and the IF amplifier input to
enable IF filtering for improved signal handling and to improve the adjacent channel
rejection.
Table 2.
Band
Recommended band limits
RF input
Min (MHz)
Oscillator
Max (MHz)
Min (MHz)
Max (MHz)
ISDB-T and NTSC Japan hybrid tuners[1]
Low
91.25
217.25
150
276
Mid
217.25
463.25
276
522
High
463.25
765.25
522
824
ISDB-T tuners for digital-only application[2]
Low
93.00
219.00
150
276
Mid
219.00
465.00
276
522
High
465.00
767.00
522
824
[1]
RF input frequency is the frequency of the corresponding picture carrier for analog standard.
[2]
For bandwidth optimization please refer to Application note AN01014.
The IF amplifier is switchable in order to drive both symmetrical and asymmetrical
outputs. When it is used as an asymmetrical amplifier, the IFOUTB pin needs to be
connected to the supply voltage VCCA.
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
Five open-drain PMOS ports are included on the IC. Two of them, BS1 and BS2, are also
dedicated to the selection of the low, mid and high bands. PMOS port BS5 pin is shared
with the ADC.
The AGC detector provides a control that can be used in a tuner to set the gain of the
RF stage. Six AGC take-over points are available by software. Two programmable AGC
time constants are available for search tuning and normal tuner operation.
The local oscillator signal is fed to the fractional-N divider. The divided frequency is
compared to the comparison frequency into the fast phase detector which drives the
charge pump. The loop amplifier is also on-chip, including the high-voltage transistor to
drive directly the 33 V tuning voltage without the need to add an external transistor.
The comparison frequency is obtained from an on-chip crystal oscillator. The crystal
frequency can be output to the XTOUT pin to drive the clock input of a digital
demodulation IC.
Control data is entered via the I2C-bus; six serial bytes are required to address the device,
select the Local Oscillator (LO) frequency, select the step frequency, program the output
ports and set the charge pump current or enable or disable the crystal output buffer, select
the AGC take-over point and time constant and/or select a specific test mode. A status
byte concerning the AGC level detector and the ADC voltage can be read out on the SDA
line during a read operation. During a read operation, the loop ‘in-lock’ flag, the power-on
reset flag and the automatic loop bandwidth control flag are read.
The device has 4 programmable addresses. Each address can be selected by applying a
specific voltage to pin AS, enabling the use of multiple devices in the same system.
The I2C-bus is fast mode compatible, except for the timing as described in the functional
description and is compatible with 5 V, 3.3 V and 2.5 V microcontrollers depending on the
voltage applied to pin BVS.
2. Features
n Single-chip 5 V mixer/oscillator and low phase noise PLL synthesizer for TV and VCR
tuners, dedicated to hybrid (digital and analog) and pure digital applications for
Japanese standards (NTSC and ISDB-T)
n Five possible step frequencies to cope with different digital terrestrial TV and
analog TV standards
n Eight charge pump currents between 40 µA and 600 µA to reach the optimum phase
noise performance over the bands
n I2C-bus protocol compatible with 2.5 V, 3.3 V and 5 V microcontrollers:
u Address + 5 data bytes transmission (I2C-bus write mode)
u Address + 1 status byte (I2C-bus read mode)
u Four independent I2C-bus addresses
n Five PMOS open-drain ports with 15 mA source capability for band switching and
general purpose; one of these ports is combined with a 5-step ADC
n Wideband AGC detector for internal tuner AGC:
u Six programmable take-over points
u Two programmable time constants
u AGC flag
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
2 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
n
n
n
n
n
n
n
n
n
n
In-lock flag
Crystal frequency output buffer
33 V tuning voltage output
Fractional-N programmable divider
Balanced mixers with a common emitter input for the low band and for the mid band
(each single input)
Balanced mixer with a common base input for the high band (balanced input)
2-pin asymmetrical oscillator for the low band
2-pin symmetrical oscillator for the mid band
4-pin symmetrical oscillator for the high band
Switched concept IF amplifier with both asymmetrical and symmetrical outputs to drive
low impedance or SAW filters i.e. 500 Ω/40 pF
3. Applications
For all applications, the recommendations given in the latest Application note AN10544
must be used.
3.1 Application summary
n
n
n
n
Digital and analog terrestrial tuners (ISDB-T and NTSC Japan)
Cable tuners (QAM)
Digital TV sets
Digital set-top boxes
4. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
TDA6650ATT/C3
TSSOP38
plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
SOT510-1
TDA6650ATT/C3/S2
TDA6651ATT/C3
TDA6651ATT/C3/S2
TDA6651ATT/C3/S3
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
3 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
5. Block diagram
IFOUTA
IFFIL1
VCCA
n.c.
21 (18)
IFFIL2
6 (33)
26 (13)
IFOUTB
7 (32)
28 (11)
27 (12)
(30) 9
IF
AMP
AGC
DETECTOR
TDA6650ATT
(TDA6651ATT)
AGC
flag
AL0, AL1, AL2
ATC
(10) 29
(1) 38
LBIN
4 (35)
LOW
INPUT
BS1
LOW
MIXER
BS1
MID
MIXER
BS2
LOW
OSCILLATOR
(2) 37
(5) 34
MBIN
HBIN1
HBIN2
3 (36)
MID
INPUT
BS2
MID
OSCILLATOR
HIGH
INPUT
BS1 . BS2
BS1 . BS2
HIGH
OSCILLATOR
(7) 32
(6) 33
RFGND
VCCD
5 (34)
(3) 36
24 (15)
N [14:0]
FRACTIONAL
DIVIDER
OUTPUT
BUFFER
R0, R1,
R2
LOOP
AMP
XTAL1
XTAL2
SCL
SDA
AS
BVS
LOSCOUT
MOSCIN1
(21) 18
HOSCIN1
HOSCOUT1
HOSCOUT2
HOSCIN2
OSCGND
XTOUT
T0, T1, T2
PHASE
COMPARATOR
FRACTIONAL
CALCULATOR
LOSCIN
MOSCIN2
(8) 31
HIGH
MIXER
IFGND
(4) 35
(9) 30
1 (38)
2 (37)
AGC
(17) 22
VT
19 (20)
20 (19)
CRYSTAL
OSCILLATOR
15 (24)
16 (23)
17 (22)
13 (26)
BAND SWITCH
OUTPUT PORTS
AGC
POR
ADC
14
(25)
8
(31)
CP
T0, T1, CP0, CP1,
T2
CP2
LOCK
DETECTOR
I2C-BUS
TRANSCEIVER
(16) 23
CHARGE
PUMP
REFERENCE
DIVIDER
10
(29)
BS5BS1
11
(28)
12
(27)
FRACTIONAL
SPURIOUS
COMPENSATION
(14) 25
PLLGND
coa033
ADC/
BS5
BS3
BS4
BS1
BS2
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 1. Block diagram
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
4 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
6. Pinning information
6.1 Pin description
Table 4.
Pin description
Symbol
Pin
Description
TDA6650ATT TDA6651ATT
HBIN1
1
38
high band RF input 1
HBIN2
2
37
high band RF input 2
MBIN
3
36
mid band RF input
LBIN
4
35
low band RF input
RFGND
5
34
RF ground
IFFIL1
6
33
IF filter output 1
IFFIL2
7
32
IF filter output 2
BS4
8
31
PMOS open-drain output port 4 for general
purpose
AGC
9
30
AGC output
BS3
10
29
PMOS open-drain output port 3 for general
purpose
BS2
11
28
PMOS open-drain output port 2 to select the mid
band
BS1
12
27
PMOS open-drain output port 1 to select the low
band
BVS
13
26
bus voltage selection input
ADC/BS5
14
25
ADC input or PMOS open-drain output port 5 for
general purpose
SCL
15
24
I2C-bus serial clock input
SDA
16
23
I2C-bus serial data input and output
AS
17
22
I2C-bus address selection input
XTOUT
18
21
crystal frequency buffer output
XTAL1
19
20
crystal oscillator input 1
XTAL2
20
19
crystal oscillator input 2
n.c.
21
18
not connected
VT
22
17
tuning voltage output
CP
23
16
charge pump output
VCCD
24
15
supply voltage for the PLL part
PLLGND
25
14
PLL ground
VCCA
26
13
supply voltage for the analog part
IFOUTB
27
12
IF output B for symmetrical amplifier and
asymmetrical IF amplifier switch input
IFOUTA
28
11
IF output A
IFGND
29
10
IF ground
HOSCIN1
30
9
high band oscillator input 1
HOSCOUT1
31
8
high band oscillator output 1
HOSCOUT2
32
7
high band oscillator output 2
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
5 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 4.
Pin description …continued
Symbol
Pin
Description
TDA6650ATT TDA6651ATT
HOSCIN2
33
6
high band oscillator input 2
MOSCIN1
34
5
mid band oscillator input 1
MOSCIN2
35
4
mid band oscillator input 2
OSCGND
36
3
oscillators ground
LOSCOUT
37
2
low band oscillator output
LOSCIN
38
1
low band oscillator input
6.2 Pinning
HBIN1
1
38 LOSCIN
LOSCIN
1
38 HBIN1
HBIN2
2
37 LOSCOUT
LOSCOUT
2
37 HBIN2
MBIN
3
36 OSCGND
OSCGND
3
36 MBIN
LBIN
4
35 MOSCIN2
MOSCIN2
4
35 LBIN
RFGND
5
34 MOSCIN1
MOSCIN1
5
34 RFGND
IFFIL1
6
33 HOSCIN2
HOSCIN2
6
33 IFFIL1
IFFIL2
7
32 HOSCOUT2
HOSCOUT2
7
32 IFFIL2
BS4
8
31 HOSCOUT1
HOSCOUT1
8
31 BS4
AGC
9
30 HOSCIN1
HOSCIN1
9
BS3 10
TDA6650ATT
30 AGC
TDA6651ATT
29 IFGND
IFGND 10
BS2 11
28 IFOUTA
IFOUTA 11
28 BS2
BS1 12
27 IFOUTB
IFOUTB 12
27 BS1
BVS 13
26 VCCA
VCCA 13
26 BVS
ADC/BS5 14
25 PLLGND
SCL 15
24 VCCD
SDA 16
AS 17
XTOUT 18
XTAL1 19
29 BS3
PLLGND 14
25 ADC/BS5
VCCD 15
24 SCL
23 CP
CP 16
23 SDA
22 VT
VT 17
22 AS
21 n.c.
n.c. 18
20 XTAL2
001aac086
Fig 2. Pin configuration TDA6650ATT
21 XTOUT
XTAL2 19
20 XTAL1
001aac087
Fig 3. Pin configuration TDA6651ATT
7. Functional description
7.1 Mixer, Oscillator and PLL (MOPLL) functions
Bit BS1 enables the BS1 port, the low band mixer and the low band oscillator. Bit BS2
enables the BS2 port, the mid band mixer and the mid band oscillator. When both BS1
and BS2 bits are logic 0, the high band mixer and the high band oscillator are enabled.
The oscillator signal is applied to the fractional-N programmable divider. The divided
signal fdiv is fed to the phase comparator where it is compared in both phase and
frequency with the comparison frequency fcomp. This frequency is derived from the signal
present on the crystal oscillator fxtal and divided in the reference divider. There is a
fractional calculator on the chip that generates the data for the fractional divider as well as
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
6 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
the reference divider ratio, depending on the step frequency selected. The crystal
oscillator requires a 4 MHz crystal in series with an 18 pF capacitor between pins XTAL1
and XTAL2.
The output of the phase comparator drives the charge pump and the loop amplifier
section. This amplifier has an on-chip high voltage drive transistor. Pin CP is the output of
the charge pump, and pin VT is the pin to drive the tuning voltage to the varicap diodes of
the oscillators and the tracking filters. The loop filter has to be connected between pins CP
and VT. The spurious signals introduced by the fractional divider are automatically
compensated by the spurious compensation block.
It is possible to drive the clock input of a digital demodulation IC from pin XTOUT with the
4 MHz signal from the crystal oscillator. This output is also used to output 1⁄2fdiv and fcomp
signals in a specific test mode (see Table 9). It is possible to switch off this output, which is
recommended when it is not used.
For test and alignment purposes, it is also possible to release the tuning voltage output by
selecting the sinking mode (see Table 9), and by applying an external voltage on pin VT.
In addition to the BS1 and BS2 output ports that are used for the band selection, there are
three general purpose ports BS3, BS4 and BS5. All five ports are PMOS open-drain type,
each with 15 mA drive capability. The connection for port BS5 and the ADC input is
combined on one pin. It is not possible to use the ADC if port BS5 is used.
The AGC detector compares the level at the IF amplifier output to a reference level which
is selected from 6 different levels via the I2C-bus. The time constant of the AGC can be
selected via the I2C-bus to cope with normal operation as well as with search operation.
When the output level on pin AGC is higher than the threshold VRMH, then bit AGC = 1.
When the output level on pin AGC is lower than the threshold VRML, then bit AGC = 0.
Between these two thresholds, bit AGC is not defined. The status of the AGC bit can be
read via the I2C-bus according to the read mode as described in Table 13.
7.2 I2C-bus voltage
The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied to 2.5 V,
3.3 V or 5 V. The choice of the bus input threshold voltages is made with pin BVS that can
be left open-circuit, connected to the supply voltage or to ground (see Table 5).
Table 5.
I2C-bus voltage selection
Pin BVS connection
Bus voltage
Logic level
LOW
HIGH
To ground
2.5 V
0 V to 0.75 V
1.75 V to 5.5 V
Open-circuit
3.3 V
0 V to 1.0 V
2.3 V to 5.5 V
To VCC
5V
0 V to 1.5 V
3.0 V to 5.5 V
7.3 Phase noise, I2C-bus traffic and crosstalk
While the TDA6650ATT; TDA6651ATT is dedicated for hybrid terrestrial applications, the
low noise PLL will clean up the noise spectrum of the VCOs close to the carrier to reach
noise levels at 1 kHz offset from the carrier compatible with e.g. ISDB-T reception.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
7 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Linked to this noise improvement, some disturbances may become visible while they were
not visible because they were hidden into the noise in analog dedicated applications and
circuits.
This is especially true for disturbances coming from the I2C-bus traffic, whatever this traffic
is intended for the MOPLL or for another slave on the bus.
To avoid this I2C-bus crosstalk and be able to have a clean noise spectrum, it is necessary
to use a bus gate that enables the signal on the bus to drive the MOPLL only when the
communication is intended for the tuner part (such a kind of I2C-bus gate is included into
the NXP terrestrial channel decoders), and to avoid unnecessary repeated sending of the
same information.
8. I2C-bus protocol
The TDA6650ATT; TDA6651ATT is controlled via the two-wire I2C-bus. For programming,
there is one device address (7 bits) and the R/W bit for selecting read or write mode. To be
able to have more than one MOPLL in an I2C-bus system, one of four possible addresses
is selected depending on the voltage applied to address selection pin AS (see Table 8).
The TDA6650ATT; TDA6651ATT fulfils the fast mode I2C-bus, according to the NXP
I2C-bus specification, except for the timing as described in Figure 4. The I2C-bus interface
is designed in such a way that the pins SCL and SDA can be connected to 5 V, 3.3 V
or to 2.5 V pulled-up I2C-bus lines, depending on the voltage applied to pin BVS (see
Table 5).
8.1 Write mode; R/W = 0
After the address transmission (first byte), data bytes can be sent to the device (see
Table 6). Five data bytes are needed to fully program the TDA6650ATT; TDA6651ATT.
The I2C-bus transceiver has an auto-increment facility that permits programming the
device within one single transmission (address + 5 data bytes).
The TDA6650ATT; TDA6651ATT can also be partly programmed on the condition that the
first data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The
first bit of the first data byte transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional
data bytes can be entered without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission (STOP condition). Each control
byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider
data are valid only if no new I2C-bus transmission is started (START condition) during the
computation period of 50 µs.
Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the
ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in
the same transmission.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
8 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
50 µs
START
ADDRESS DIVIDER
BYTE
BYTE 1
DIVIDER CONTROL CONTROL CONTROL CONTROL
STOP
BYTE 2
BYTE 1
BYTE 2
BYTE 1
BYTE 2
START
I2C-bus transmission dedicated to
the MOPLL
ADDRESS
BYTE
I2C-bus transmission
dedicated to
another IC
fce921
Fig 4. Example of I2C-bus transmission frame
Table 6.
I2C-bus write data format
Name
Byte
Bit
Ack
MSB[1]
LSB
Address byte
1
1
1
0
0
0
MA1
MA0
R/W = 0 A
Divider byte 1 (DB1)
2
0
N14
N13
N12
N11
N10
N9
N8
A
Divider byte 2 (DB2)
3
N7
N6
N5
N4
N3
N2
N1
N0
A
Control byte 1 (CB1);
see Table 7
4
1
T/A = 1
T2
T1
T0
R2
R1
R0
A
1
T/A = 0
0
0
ATC
AL2
AL1
AL0
A
Control byte 2 (CB2)
5
CP2
CP1
CP0
BS5
BS4
BS3
BS2
BS1
A
[1]
MSB is transmitted first.
Table 7.
Description of write data format bits
Bit
Description
A
acknowledge
MA1 and MA0
programmable address bits; see Table 8
R/W
logic 0 for write mode
N14 to N0
programmable LO frequency;
N = N14 × 214 + N13 × 213 + N12 × 212 + ... + N1 × 21 + N0
T/A
test/AGC bit
T/A = 0: the next 6 bits sent are AGC settings
T/A = 1: the next 6 bits sent are test and reference divider ratio settings
T2, T1 and T0
test bits; see Table 9
R2, R1, and R0
reference divider ratio and programmable frequency step; see Table 10
ATC
AGC current setting and time constant; capacitor on pin AGC = 150 nF
ATC = 0: AGC current = 220 nA; AGC time constant = 2 s
ATC = 1: AGC current = 9 µA; AGC time constant = 50 ms
AL2, AL1 and AL0
AGC take-over point bits; see Table 11
CP2, CP1 and CP0
charge pump current; see Table 12
BS5, BS4, BS3, BS2 PMOS ports control bits
and BS1
BSn = 0: corresponding port is off, high-impedance state (status at
power-on reset)
BSn = 1: corresponding port is on; VO = VCC − VDS(sat)
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
9 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
8.1.1 I2C-bus address selection
The device address contains programmable address bits MA1 and MA0, which offer the
possibility of having up to four MOPLL ICs in one system. Table 8 gives the relationship
between the voltage applied to the AS input and the MA1 and MA0 bits.
Table 8.
Address selection
Voltage applied to pin AS
MA1
MA0
0 V to 0.1VCC
0
0
0.2VCC to 0.3VCC or open-circuit
0
1
0.4VCC to 0.6VCC
1
0
0.9VCC to VCC
1
1
8.1.2 XTOUT output buffer and mode setting
The crystal frequency can be sent to pin XTOUT and used in the application, for example
to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of
material. To output fxtal, it is necessary to set T[2:0] to 001. If the output signal on this pin
is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used
to output 1⁄2fdiv and fcomp in a test mode. At power-on, the XTOUT output buffer is set to
on, supplying the fxtal signal. The relation between the signal on pin XTOUT and the
setting of the T[2:0] bits is given in Table 9.
Table 9.
XTOUT buffer status and test modes
T2
T1
T0
Pin XTOUT
Mode
0
0
0
disabled
normal mode with XTOUT buffer off
0
0
1
fxtal (4 MHz)
normal mode with XTOUT buffer on
0
1
0
1⁄ f
2 div
charge pump off
0
1
1
fxtal (4 MHz)
not used[1]
1
0
0
fcomp
test mode
test mode
1
0
1
1⁄ f
2 div
1
1
0
fxtal (4 MHz)
charge pump sinking current[2]
1
1
1
disabled
charge pump sourcing current
[1]
This is an on-chip function that automatically sets internal values for the PLL. This function is not optimized
for ISDB-T and NTSC Japan and therefore must not be used.
[2]
This is the default mode at power-on reset. This mode disables the tuning voltage.
8.1.3 Step frequency setting
The step frequency is set by three bits, giving five steps to cope with different application
requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The
phase detector works at either 4 MHz, 2 MHz or 1 MHz.
Table 10 shows the step frequencies and corresponding reference divider ratios. When
the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes
DB1 and DB2.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
10 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 10.
Reference divider ratio select bits
R2
R1
R0
Reference divider Frequency
ratio
comparison
Frequency step
0
0
0
2
2 MHz
62.5 kHz
0
0
1
1
4 MHz
142.86 kHz
0
1
0
1
4 MHz
166.67 kHz
0
1
1
4
1 MHz
50 kHz
1
0
0
1
4 MHz
125 kHz
1
0
1
-
-
reserved
1
1
0
-
-
reserved
1
1
1
-
-
reserved
8.1.4 AGC detector setting
The AGC take-over point can be selected out of 6 levels according to Table 11.
Table 11.
AGC programming
AL2
AL1
AL0
0
0
0
[1]
124 dBµV (p-p)
1
[1]
121 dBµV (p-p)
0
[1]
118 dBµV (p-p)
115 dBµV (p-p)
0
0
0
1
Typical take-over point level
0
1
1
[2]
1
0
0
[2]
112 dBµV (p-p)
1
[2]
109 dBµV (p-p)
0
[3]
IAGC = 0 A
1
[4]
VAGC = 3.5 V
1
0
1
1
1
1
[1]
This take-over point is available for both symmetrical and asymmetrical modes.
[2]
This take-over point is available for asymmetrical mode only.
[3]
The AGC current sources are disabled. The AGC output goes into a high-impedance state and an external
AGC source can be connected in parallel and will not be influenced.
[4]
The AGC detector is disabled and IAGC = 9 µA.
8.1.5 Charge pump current setting
The charge pump current can be chosen from 8 values depending on the value of bits
CP2, CP1 and CP0 bits; see Table 12.
Table 12.
Charge pump current
CP2
CP1
CP0
Charge pump current
number
Typical current (absolute
value in µA)
0
0
0
1
38
0
0
1
2
54
0
1
0
3
83
0
1
1
4
122
1
0
0
5
163
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
11 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 12.
Charge pump current …continued
CP2
CP1
CP0
Charge pump current
number
Typical current (absolute
value in µA)
1
0
1
6
254
1
1
0
7
400
1
1
1
8
580
8.2 Read mode; R/W = 1
Data can be read from the device by setting the R/W bit to 1 (see Table 13). After the
device address has been recognized, the device generates an acknowledge pulse and the
first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the
SDA line during a HIGH level of the SCL clock signal.
A second data byte can be read from the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End of transmission will occur if no
master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
Table 13.
I2C-bus read data format
Name
Byte
Bit
Ack
MSB[1]
LSB
Address byte 1
1
1
0
0
0
MA1
MA0
R/W = 1 A
Status byte
POR
FL
0
1
AGC
A2
A1
A0
[1]
2
-
MSB is transmitted first.
Table 14.
Description of read data format bits
Bit
Description
A
acknowledge
POR
power-on reset flag
POR = 0, normal operation
POR = 1, power-on reset
FL
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
AGC
internal AGC flag
AGC = 0 when internal AGC is active (VAGC < VRML)
AGC = 1 when internal AGC is not active (VAGC > VRMH)
digital outputs of the 5-level ADC; see Table 15
A2, A1, A0
Table 15.
ADC levels
Voltage applied to pin ADC[1]
A2
A1
A0
0.6VCC to VCC
1
0
0
0.45VCC to 0.6VCC
0
1
1
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
12 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 15.
ADC levels …continued
Voltage applied to pin ADC[1]
A2
A1
A0
0.3VCC to 0.45VCC
0
1
0
0.15VCC to 0.3VCC
0
0
1
0 V to 0.15VCC
0
0
0
[1]
Accuracy is ±0.03VCC. Bit BS5 must be set to logic 0 to disable the BS5 output port. The BS5 output port
uses the same pin as the ADC and can not be used when the ADC is in use.
8.3 Status at power-on reset
At power on or when the supply voltage drops below approximately 2.85 V (at
Tamb = 25 °C), internal registers are set according to Table 16.
At power on, the charge pump current is set to 580 µA, the test bits T[2:0] are set to 110
which means that the charge pump is sinking current, the tuning voltage output is
disabled. The XTOUT buffer is on, driving the 4 MHz signal from the crystal oscillator and
all the ports are off. As a consequence, the high band is selected by default.
Table 16.
Default setting at power-on reset
Name
Byte
Bit[1]
MSB
LSB
Address byte
1
1
1
0
0
0
MA1
MA0
X
Divider byte 1 (DB1)
2
0
N14 = X
N13 = X
N12 = X
N11 = X
N10 = X
N9 = X
N8 = X
Divider byte 2 (DB2)
3
N7 = X
N6 = X
N5 = X
N4 = X
N3 = X
N2 = X
N1 = X
N0 = X
Control byte 1 (CB1)
4
1
T/A = X[2]
T2 = 1
T1 = 1
T0 = 0
R2 = X
R1 = X
R0 = X
1
T/A = X[3]
0
0
ATC = 0
AL2 = 0
AL1 = 1
AL0 = 0
CP2 = 1
CP1 = 1
CP0 = 1
BS5 = 0
BS4 = 0
BS3 = 0
BS2 = 0
BS1 = 0
Control byte 2 (CB2)
5
[1]
X means that this bit is not set or reset at power-on reset.
[2]
The next six bits are written, when bit T/A = 1 in a write sequence.
[3]
The next six bits are written, when bit T/A = 0 in a write sequence.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
13 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
9. Internal circuitry
Table 17.
Internal pin configuration
Symbol
Pin
Average DC voltage versus band
selection
TDA6650ATT
TDA6651ATT
Low
Mid
High
HBIN1
1
38
n.a.
n.a.
1.0 V
HBIN2
2
37
n.a.
n.a.
1.0 V
Description[1]
(38) 1
2 (37)
fce899
MBIN
3
36
n.a.
1.8 V
n.a.
(36) 3
fce901
LBIN
4
35
1.8 V
n.a.
n.a.
(35) 4
fce898
RFGND
5
34
-
-
5 (34)
fce897
IFFIL1
6
33
3.7 V
3.7 V
3.7 V
IFFIL2
7
32
3.7 V
3.7 V
3.7 V
7 (32)
(33) 6
fce896
BS4
8
31
high-Z or
high-Z or
high-Z or
VCC − VDS VCC − VDS VCC − VDS
8 (31)
fce895
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
14 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 17.
Internal pin configuration …continued
Symbol
AGC
Pin
Average DC voltage versus band
selection
TDA6650ATT
TDA6651ATT
Low
Mid
High
9
30
0 V or
3.5 V
0 V or
3.5 V
0 V or
3.5 V
Description[1]
9 (30)
fce907
BS3
10
29
high-Z or
high-Z or
high-Z or
VCC − VDS VCC − VDS VCC − VDS
10 (29)
fce893
BS2
11
28
high-Z
VCC − VDS high-Z
11 (28)
fce892
BS1
12
27
VCC − VDS high-Z
high-Z
12 (27)
fce891
BVS
13
26
2.5 V
2.5 V
2.5 V
(26) 13
mce163
ADC/BS5
14
25
VCEsat or
high-Z
VCEsat or
high-Z
VCEsat or
high-Z
(25) 14
fce887
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
15 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 17.
Internal pin configuration …continued
Symbol
SCL
Pin
Average DC voltage versus band
selection
TDA6650ATT
TDA6651ATT
Low
Mid
High
15
24
high-Z
high-Z
high-Z
Description[1]
(24) 15
fce889
SDA
16
23
high-Z
high-Z
high-Z
(23) 16
fce888
AS
17
22
1.25 V
1.25 V
1.25 V
(22) 17
001aac102
XTOUT
18
21
3.45 V
3.45 V
3.45 V
18 (21)
mce164
XTAL1
19
20
2.2 V
2.2 V
2.2 V
XTAL2
20
19
2.2 V
2.2 V
2.2 V
19 (20)
20 (19)
fce883
n.c.
21
18
n.a.
n.a.
n.a.
TDA6650ATT_6651ATT_2
Product data sheet
not connected
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
16 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 17.
Internal pin configuration …continued
Symbol
VT
Pin
Average DC voltage versus band
selection
TDA6650ATT
TDA6651ATT
Low
Mid
High
22
17
VVT
VVT
VVT
Description[1]
22 (17)
fce884
CP
23
16
1.8 V
1.8 V
1.8 V
23 (16)
fce885
VCCD
24
15
5V
5V
5V
PLLGND
25
14
-
-
25 (14)
fce882
VCCA
26
13
5V
5V
5V
IFOUTB
27
12
2.1 V
2.1 V
2.1 V
IFOUTA
28
11
2.1 V
2.1 V
2.1 V
28 (11)
fce886
IFGND
29
10
-
-
29 (10)
fce880
HOSCIN1
30
9
2.2 V
2.2 V
1.8 V
HOSCOUT1
31
8
5V
5V
2.5 V
HOSCOUT2
32
7
5V
5V
2.5 V
HOSCIN2
33
6
2.2 V
2.2 V
1.8 V
(8) 31
32 (7)
(6) 33
30 (9)
fce879
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
17 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 17.
Internal pin configuration …continued
Symbol
Pin
Average DC voltage versus band
selection
TDA6650ATT
TDA6651ATT
Low
Mid
High
MOSCIN1
34
5
2.3 V
1.3 V
2.3 V
MOSCIN2
35
4
2.3 V
1.3 V
2.3 V
Description[1]
35 (4)
34 (5)
fce878
OSCGND
36
3
-
-
36 (3)
fce908
LOSCOUT
37
2
1.7 V
1.4 V
1.4 V
LOSCIN
38
1
2.9 V
3.5 V
3.5 V
37 (2)
(1) 38
fce877
[1]
The pin numbers in parenthesis refer to the TDA6651ATT.
10. Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are
entering the IC and negative currents are going out of the IC; all voltages are referenced to ground
(GND)[1].
Symbol
Parameter
VCCA
Conditions
Min
Max
Unit
analog supply voltage
−0.3
+6
V
VCCD
digital supply voltage
−0.3
+6
V
VVT
tuning voltage output
−0.3
+35
V
VSDA
serial data input and output
voltage
−0.3
+6
V
ISDA
serial data output current
0
10
mA
VSCL
serial clock input voltage
−0.3
+6
V
VAS
address selection input
voltage
−0.3
+6
V
during
acknowledge
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
18 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 18. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are
entering the IC and negative currents are going out of the IC; all voltages are referenced to ground
(GND)[1].
Symbol
Parameter
Conditions
[2]
Min
Max
Unit
−0.3
VCC + 0.3
V
−20
0
mA
Vn
voltage on all other inputs,
outputs and combined
inputs and outputs, except
GNDs
4.5 V < VCC < 5.5 V
IBSn
PMOS port output current
corresponding port
on; open-drain
IBS(tot)
sum of all PMOS port output open-drain
currents
−50
0
mA
tsc(max)
maximum short-circuit time
-
10
s
Tstg
storage temperature
−40
+150
°C
−20
Tamb(max)
°C
-
150
°C
Tamb
ambient temperature
Tj
junction temperature
each pin to VCC or
to GND
[3]
[1]
Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage.
Maximum ratings cannot be accumulated.
[2]
VCC refers to the operating supply voltage.
[3]
The maximum allowed ambient temperature Tamb(max) depends on the assembly conditions of the package
and especially on the design of the printed-circuit board. The application mounting must be done in such a
way that the maximum junction temperature is never exceeded. An estimation of the junction temperature
can be obtained through measurement of the temperature of the top center of the package (Tpackage). The
temperature difference junction to case (∆Tj-c) is estimated at about 13 °C on the demo board (PCB 827-3).
The junction temperature Tj = Tpackage + ∆Tj-c.
11. Thermal characteristics
Table 19.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from
junction to ambient
in free air
Typ
Unit
TDA6650ATT
82
K/W
TDA6651ATT
74
K/W
[1]
Measured in free air as defined by JEDEC standard JESD51-2.
[2]
These values are given for information only. The thermal resistance depends strongly on the nature and
design of the printed-circuit board used in the application. The thermal resistance given corresponds to the
value that can be measured on a multilayer printed-circuit board (4 layers) as defined by JEDEC standard.
[3]
The junction temperature influences strongly the reliability of an IC. The printed-circuit board used in the
application contributes in a large part to the overall thermal characteristic. It must therefore be insured that
the junction temperature of the IC never exceeds T j(max) = 150 °C at the maximum ambient temperature.
TDA6650ATT_6651ATT_2
Product data sheet
[1][2][3]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
19 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
12. Characteristics
Table 20. Characteristics
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.5
5.0
5.5
V
Supply
VCC
supply voltage
ICC
supply current
PMOS ports off
80
96
115
mA
one PMOS port on: sourcing 15 mA
96
112
131
mA
two PMOS ports on: one port
sourcing 15 mA and one other port
sourcing 5 mA
101
117
136
mA
power-on reset active if VCC < VPOR
-
2.85
3.5
V
64
-
1024
MHz
-
4.0
-
MHz
350
430
-
Ω
-
70
-
µW
General functions
VPOR
power-on reset supply
voltage
∆flock
frequency range the PLL
is able to synthesize
Crystal oscillator[1]
fxtal
crystal frequency
Zxtal
input impedance
(absolute value)
fxtal = 4 MHz; VCC = 4.5 V to 5.5 V
Tamb = −20 °C to Tamb(max),
see Section 10
Pxtal
crystal drive level
fxtal = 4 MHz
[2]
PMOS ports: pins BS1, BS2, BS3, BS4 and BS5
ILO(off)
output leakage current in VCC = 5.5 V; VBS = 0 V
off state
−10
-
-
µA
VDS(sat)
output saturation voltage only corresponding buffer is on,
sourcing 15 mA; VDS(sat) = VCC − VBS
-
0.2
0.4
V
0
-
5.5
V
ADC input: pin ADC
Vi
ADC input voltage
see Table 15
IIH
HIGH-level input current VADC = VCC
-
-
10
µA
IIL
LOW-level input current
−10
-
-
µA
VADC = 0 V
Address selection input: pin AS
IIH
HIGH-level input current VAS = 5.5 V
-
-
10
µA
IIL
LOW-level input current
−10
-
-
µA
VAS = 0 V
Bus voltage selection input: pin BVS
IIH
HIGH-level input current VBVS = 5.5 V
-
-
100
µA
IIL
LOW-level input current
−100
-
-
µA
-
400
-
mV
-
175
-
Ω
VBVS = 0 V
Buffered output: pin XTOUT
Vo(p-p)
square wave AC output
voltage (peak-to-peak
value)
Zo
output impedance
[3]
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
20 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I2C-bus
Inputs: pins SCL and SDA
fclk
clock frequency
frequency on SCL
-
-
400
kHz
VIL
LOW-level input voltage
VBVS = 0 V
0
-
0.75
V
VBVS = 2.5 V or open-circuit
0
-
1.0
V
VBVS = 5 V
0
-
1.5
V
1.75
-
5.5
V
VIH
IIH
HIGH-level input voltage VBVS = 0 V
VBVS = 2.5 V or open-circuit
2.3
-
5.5
V
VBVS = 5 V
3.0
-
5.5
V
-
-
10
µA
-
-
10
µA
VCC = 0 V; VBUS = 1.5 V
-
-
10
µA
VCC = 5.5 V; VBUS = 0 V
−10
-
-
µA
HIGH-level input current VCC = 0 V; VBUS = 5.5 V
VCC = 5.5 V; VBUS = 5.5 V
IIL
LOW-level input current
Output: pin SDA
ILH
leakage current
VSDA = 5.5 V
-
-
10
µA
VO(ack)
output voltage during
acknowledge
ISDA = 3 mA
-
-
0.4
V
see Table 12
-
-
-
µA
−15
0
+15
nA
Charge pump output: pin CP
Io
output current (absolute
value)
IL(off)
off-state leakage current charge pump off (T[2:0] = 010)
Tuning voltage output: pin VT
IL(off)
leakage current when
switched-off
tuning supply voltage = 33 V
-
-
10
µA
Vo(cl)
output voltage when the
loop is closed
tuning supply voltage = 33 V;
RL = 15 kΩ
0.3
-
32.7
V
digital application:
TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2,
TDA6651ATT/C3/S3
-
0.5
-
deg
hybrid application:
TDA6650ATT/C3, TDA6651ATT/C3
-
0.6
-
deg
Noise performance
Jφ(rms)
phase jitter (RMS value) integrated between 1 kHz and 1 MHz
offset from the carrier
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
21 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Low band mixer, including IF amplifier
fRF
Gv
RF frequency
voltage gain
picture carrier for hybrid application
TDA6650ATT/C3, TDA6651ATT/C3
[4]
91.25
-
219.143 MHz
picture carrier for digital-only
application TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2,
TDA6651ATT/C3/S3
[4]
93.00
-
220.893 MHz
fRF = 91.25 MHz
20
23.5
26
dB
fRF = 219.143 MHz
20
24.0
26
dB
fRF = 91.25 MHz
25
27.5
31
dB
fRF = 219.143 MHz
25
27.5
31
dB
-
7
10
dB
107
110
-
dBµV
107
110
-
dBµV
117
120
-
dBµV
asymmetrical IF output; RL = 75 Ω;
see Figure 14
symmetrical IF output; RL = 1.25 kΩ;
see Figure 15
NF
noise figure
fRF = 150 MHz
Vo
output voltage causing
1 % cross modulation in
channel
asymmetrical application;
see Figure 18
[5]
fRF = 91.25 MHz
fRF = 219.143 MHz
symmetrical application;
see Figure 19
[5]
fRF = 91.25 MHz
fRF = 219.143 MHz
Vi
input voltage causing
750 Hz frequency
deviation pulling in
channel
asymmetrical IF output
Vi(lock)
input level without
lock-out
see Figure 25
Gi
input conductance
fRF = 91.25 MHz; see Figure 5
Ci
input capacitance
[7]
117
120
-
dBµV
-
85
-
dBµV
-
-
120
dBµV
-
0.15
-
mS
fRF = 219.43 MHz; see Figure 5
-
0.20
-
mS
fRF = 91.25 MHz to 219.43 MHz;
see Figure 5
-
1.60
-
pF
for hybrid application
TDA6650ATT/C3, TDA6651ATT/C3
163.25
-
465.143 MHz
picture carrier for digital only
application TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2,
TDA6651ATT/C3/S3
165.00
-
466.893 MHz
Mid band mixer, including IF amplifier
foper
operating frequency
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
22 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
fRF
RF frequency
picture carrier for hybrid application
TDA6650ATT/C3, TDA6651ATT/C3
[4]
223.25
-
465.143 MHz
picture carrier for digital only
application TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2,
TDA6651ATT/C3/S3
[4]
225.00
-
466.893 MHz
fRF = 223.25 MHz
20
23.5
26
dB
fRF = 465.143 MHz
20
24
26
dB
fRF = 223.25 MHz
25
27
31
dB
fRF = 465.143 MHz
25
27.5
31
dB
-
8
11
dB
107
110
-
dBµV
107
110
-
dBµV
fRF = 223.25 MHz
117
120
-
dBµV
fRF = 465.143 MHz
117
120
-
dBµV
-
87
-
dBµV
-
-
120
dBµV
Gv
voltage gain
Unit
asymmetrical IF output; load = 75 Ω;
see Figure 14
symmetrical IF output;
load = 1.25 kΩ; see Figure 15
NF
Vo
noise figure
output voltage causing
1 % cross modulation in
channel
fRF = 300 MHz; see Figure 17
asymmetrical application;
see Figure 18
[5]
fRF = 223.25 MHz
fRF = 465.143 MHz
symmetrical application;
see Figure 19
[5]
Vi
input voltage causing
750 Hz frequency
deviation pulling in
channel
asymmetrical IF output
Vi(lock)
input level without
lock-out
see Figure 25
Gi
input conductance
see Figure 6
-
0.3
-
mS
Ci
input capacitance
see Figure 6
-
1.1
-
pF
for hybrid application
TDA6650ATT/C3, TDA6651ATT/C3
355.25
-
767.143 MHz
picture carrier for digital only
application TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2,
TDA6651ATT/C3/S3
357.00
-
768.893 MHz
[7]
High band mixer, including IF amplifier
foper
operating frequency
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
23 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
fRF
RF frequency
picture carrier for hybrid application
TDA6650ATT/C3, TDA6651ATT/C3
[4]
471.25
-
767.143 MHz
picture carrier for digital only
application TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2,
TDA6651ATT/C3/S3
[4]
473.00
-
768.893 MHz
fRF = 471.25 MHz
31.5
35
37.5
dB
fRF = 767.143 MHz
31.5
33.5
37.5
dB
fRF = 471.25 MHz
35.5
38.5
41.5
dB
fRF = 767.143 MHz
35.5
37
41.5
dB
fRF = 471.25 MHz
-
6
8
dB
fRF = 767.143 MHz
-
7
9
dB
fRF = 471.25 MHz
107
110
-
dBµV
fRF = 767.143 MHz
107
110
-
dBµV
fRF = 471.25 MHz
117
120
-
dBµV
fRF = 767.143 MHz
117
120
-
dBµV
-
-
120
dBµV
-
75
-
dBµV
RS
-
35
-
Ω
LS
-
8
-
nH
RS
-
36
-
Ω
LS
-
8
-
nH
Gv
voltage gain
Unit
asymmetrical IF output; load = 75 Ω;
see Figure 20
symmetrical IF output;
load = 1.25 kΩ; see Figure 21
NF
Vo
noise figure, not
corrected for image
output voltage causing
1 % cross modulation in
channel
see Figure 22
asymmetrical application;
see Figure 23
symmetrical application;
see Figure 24
Vi(lock)
input level without
lock-out
see Figure 26
Vi
input voltage causing
750 Hz frequency
deviation pulling in
channel
asymmetrical IF output
Zi
input impedance
(RS + jLSω)
fRF = 471.25 MHz; see Figure 7
[5]
[5]
[7]
fRF = 767.143 MHz; see Figure 7
Low band oscillator
fosc
∆fosc(V)
oscillator frequency
[7]
150
-
276.143 MHz
oscillator frequency shift
with supply voltage
[8]
-
110
300
TDA6650ATT_6651ATT_2
Product data sheet
kHz
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
24 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V with
compensation
Φosc(dig)
phase noise, carrier to
TDA6650ATT/C3/S2;
sideband noise in digital TDA6651ATT/C3/S2;
application
TDA6651ATT/C3/S3
Φosc(hyb)
RSCp-p
Min
Typ
Max
Unit
-
900
-
kHz
±1 kHz frequency offset;
fcomp = 4 MHz;
see Figure 8, 27 and 28
82
90
-
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range;
see Figure 9, 27 and 28
87
94
-
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range;
see Figure 10, 27 and 28
104
115
-
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range;
see Figure 27 and 28
-
117
-
dBc/Hz
75
81
-
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range;
see Figure 12, 29 and 30
85
92
-
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range;
see Figure 13, 29 and 30
104
115
-
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range;
see Figure 29 and 30
-
117
-
dBc/Hz
15
200
-
mV
222
-
522.143 MHz
[9]
phase noise, carrier to
TDA6650ATT/C3; TDA6651ATT/C3
sideband noise in hybrid
±1 kHz frequency offset;
application
fcomp = 4 MHz; see Figure 11, 29
and 30
ripple susceptibility of
VCC (peak-to-peak
value)
VCC = 5 V ± 5 %; worst case in the
frequency range; ripple frequency
500 kHz
[10]
Mid band oscillator
fosc
oscillator operating
frequency
oscillator frequency
[7]
276
-
522.143 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
[8]
-
300
-
kHz
∆fosc(T)
oscillator frequency drift
with temperature
[9]
-
1500
-
kHz
∆T = 25 °C; VCC = 5 V with
compensation
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
25 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Φosc(dig)
TDA6650ATT/C3/S2;
phase noise, carrier to
sideband noise in digital TDA6651ATT/C3/S2;
TDA6651ATT/C3/S3
application
Φosc(hyb)
RSCp-p
Conditions
Min
Typ
Max
Unit
±1 kHz frequency offset;
fcomp = 4 MHz;
see Figure 8, 27 and 28
85
90
-
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range;
see Figure 9, 27 and 28
87
94
-
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range;
see Figure 10, 27 and 28
104
112
-
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range;
see Figure 27 and 28
-
116
-
dBc/Hz
80
86
-
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figure 12, 29 and 30
85
92
-
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figure 13, 29 and 30
104
115
-
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figure 29 and 30
-
115
-
dBc/Hz
15
140
-
mV
414
-
824.143 MHz
phase noise, carrier to
TDA6650ATT/C3; TDA6651ATT/C3
sideband noise in hybrid
±1 kHz frequency offset;
application
fcomp = 4 MHz; see
Figure 11, 29 and 30
ripple susceptibility of
VCC (peak-to-peak
value)
VCC = 5 V ± 5 %; worst case in the
frequency range; ripple frequency
500 kHz
[10]
High band oscillator
fosc
oscillator operating
frequency
oscillator frequency
[7]
522
-
824.143 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
[8]
-
300
-
kHz
∆fosc(T)
oscillator frequency drift
with temperature
[9]
-
1100
-
kHz
∆T = 25 °C; VCC = 5 V; with
compensation
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
26 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Φosc(dig)
TDA6650ATT/C3/S2;
phase noise, carrier to
sideband noise in digital TDA6651ATT/C3/S2;
TDA6651ATT/C3/S3
application
Φosc(hyb)
RSCp-p
Conditions
Min
Typ
Max
Unit
±1 kHz frequency offset;
fcomp = 4 MHz;
see Figure 8, 27 and 28
80
85
-
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range;
see Figure 9, 27 and 28
85
91
-
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range;
see Figure 11, 27 and 28
104
112
-
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range;
see Figure 27 and 28
-
117
-
dBc/Hz
80
86
-
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range;
see Figure 12, 29 and 30
82
88
-
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range;
see Figure 13, 29 and 30
104
112
-
dBc/Hz
±1.4 MHz frequency offset; worst
case in the frequency range;
see Figure 29 and 30
-
117
-
dBc/Hz
15
40
-
mV
RS at 57 MHz
-
50
-
Ω
LS at 57 MHz
-
4.7
-
nH
RS at 57 MHz
-
100
-
Ω
LS at 57 MHz
-
10
-
nH
phase noise, carrier to
TDA6650ATT/C3; TDA6651ATT/C3
sideband noise in hybrid
±1 kHz frequency offset;
application
fcomp = 4 MHz;
see Figure 11, 29 and 30
ripple susceptibility of
VCC (peak-to-peak
value)
VCC = 5 V ± 5 %; worst case in the
frequency range; ripple frequency
500 kHz
output impedance
asymmetrical IF output
[10]
IF amplifier
Zo
symmetrical IF output
Rejection at the IF output (IF amplifier in asymmetrical mode)
INTdiv
divider interferences in
IF level
worst case
[11]
-
-
20
dBµV
INTxtal
crystal oscillator
interferences rejection
VIF = 100 dBµV; worst case in the
frequency range
[12]
-
-
−50
dBc
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
27 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 20. Characteristics …continued
VCCA = VCCD = 5 V; Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of the IC;
the performances of the circuits are measured in the measurement circuits Figure 27 and 28 for digital application or in the
measurement circuits Figure 29 and 30 for hybrid application; unless otherwise specified.
Symbol
Parameter
Conditions
INTf(step)
step frequency rejection
VIF = 100 dBµV; worst case in the
frequency range
INTXTH
Min
Typ
Max
Unit
digital application
TDA6650ATT/C3/S2,
TDA6651ATT/C3/S2
-
-
−50
dBc
digital application
TDA6651ATT/C3/S3
-
-
−35
dBc
hybrid application
TDA6650ATT/C3, TDA6651ATT/C3
-
-
−57
dBc
-
-
50
dBµV
122.5
124
125.5
dBµV
[13]
[14]
crystal oscillator
harmonics in the
IF frequency
AGC output (IF amplifier in asymmetrical mode): pin AGC
AGCTOP(p-p) AGC take-over point
(peak-to-peak level)
bits AL[2:0] = 000
Isource(fast)
source current fast
7.5
9.0
11.6
µA
Isource(slow)
source current slow
185
220
280
nA
Vo
output voltage
TDA6650ATT/C3;
TDA6651ATT/C3;
TDA6650ATT/C3/S2;
TDA6651ATT/C3/S2
3.45
3.55
3.8
V
TDA6651ATT/C3/S3
3.3
3.55
3.8
V
0
-
0.1
V
3.45
3.55
3.8
V
3.3
3.55
3.8
V
-
-
0.5
dB
maximum level
minimum level
Vo(dis)
output voltage with AGC bits AL[2:0] = 111
disabled
TDA6650ATT/C3;
TDA6651ATT/C3;
TDA6650ATT/C3/S2;
TDA6651ATT/C3/S2
TDA6651ATT/C3/S3
VRF(slip)
RF voltage range to
switch the AGC from
active to not active mode
VRML
low threshold AGC
output voltage
AGC bit = 0 or AGC not active
0
-
2.8
V
VRMH
high threshold AGC
output voltage
AGC bit = 1 or AGC active
3.2
3.55
3.8
V
ILO
leakage current
bits AL[2:0] = 110; 0 < VAGC < 3.5 V
−50
-
+50
nA
[15]
[1]
Important recommendation: to obtain the performances mentioned in this specification, the serial resistance of the crystal used with this
oscillator must never exceed 120 Ω. The crystal oscillator is guaranteed to operate at any supply voltage between 4.5 V and 5.5 V and
at any temperature between −20 °C and Tamb(max), as defined in Section 10.
[2]
The drive level is expected with a 50 Ω series resistance of the crystal at series resonance. The drive level will be different with other
series resistance values.
[3]
The VXTOUT level is measured when the pin XTOUT is loaded with 5 kΩ in parallel with 10 pF.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
28 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
[4]
The RF frequency range is defined by the oscillator frequency range and the Intermediate Frequency (IF).
[5]
The 1 % cross modulation performance is measured with AGC detector turned off (AGC bits set to 110).
[6]
The IF output signal stays stable within the range of the step frequency for any RF input level up to 120 dBµV.
[7]
Limits are related to the tank circuits used in Figure 27 and 28 for digital application or Figure 29 and 30 for hybrid application.
Frequency bands may be adjusted by the choice of external components.
[8]
The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from VCC = 5 V to 4.5 V or from
VCC = 5 V to 5.25 V. The oscillator is free running during this measurement.
[9]
The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from Tamb = 25 °C to 50 °C or
from Tamb = 25 °C to 0 °C. The oscillator is free running during this measurement.
[10] The supply ripple susceptibility is measured in the measurement circuit according to Figure 27 to Figure 30 using a spectrum analyzer
connected to the IF output. An unmodulated RF signal is applied to the test board RF input. A sine wave signal with a frequency of
500 kHz is superimposed onto the supply voltage. The amplitude of this ripple signal is adjusted to bring the 500 kHz sidebands around
the IF carrier to a level of −53.5 dB with respect to the carrier.
[11] This is the level of divider interferences close to the IF frequency. The low and mid band inputs must be left open (i.e. not connected to
any load or cable); the high band inputs are connected to an hybrid.
[12] Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator.
[13] The step frequency rejection is the level of step frequency sidebands related to the carrier. The measurement is done for
VIF = 100 dBµV. This specification point corresponds to the worst case observed in the frequency range. This parameter is specified for
fstep = 142.86 kHz in digital applications and fstep = 62.5 kHz, 50 kHz or 142.86 kHz in hybrid application.
[14] This is the level of the 13rd and 15th harmonics of the 4 MHz crystal oscillator into the IF output.
[15] The AGC pin (pin 9 for TDA6650ATT and pin 30 for TDA6651ATT) must not be connected to a voltage higher than 3.6 V.
1
2
0.5
0.2
5
10
−j
∞
10
5
2
1
0.5
0.2
0
40 MHz
+j
200 MHz
10
5
0.2
2
0.5
1
mce160
Fig 5. Input admittance (s11) of the low band mixer (40 MHz to 200 MHz); Yo = 20 mS
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
29 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
1
2
0.5
0.2
5
10
−j
∞
10
5
2
1
0.5
0.2
0
100 MHz
+j
10
500 MHz
5
2
0.2
0.5
mce161
1
Fig 6. Input admittance (s11) of the mid band mixer (100 MHz to 500 MHz); Yo = 20 mS
1
0.5
2
800 MHz
0.2
5
350 MHz
10
+j
0
0.2
0.5
1
2
5
∞
10
−j
10
5
0.2
2
0.5
1
001aac088
Fig 7. Input impedance (s11) of the high band mixer (350 MHz to 800 MHz); Zo = 100 Ω
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
30 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
001aac089
−80
Φosc
(dBc/Hz)
−85
−90
−95
−100
150
250
350
450
550
650
750
850
fRF (MHz)
For measurement circuit see Figure 27 and Figure 28
Fig 8. 1 kHz phase noise typical performance in digital application
001aac090
−85
Φosc
(dBc/Hz)
−90
−95
−100
−105
150
250
350
450
550
650
750
850
fRF (MHz)
For measurement circuit see Figure 27 and Figure 28
Fig 9. 10 kHz phase noise typical performance in digital application
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
31 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
001aac091
−105
Φosc
(dBc/Hz)
−110
−115
−120
150
250
350
450
550
650
750
850
fRF (MHz)
For measurement circuit see Figure 27 and Figure 28
Fig 10. 100 kHz phase noise typical performance in digital application
001aac092
−75
Φosc
(dBc/Hz)
−80
−85
−90
−95
−100
150
250
350
450
550
650
750
850
fRF (MHz)
For measurement circuit see Figure 29 and Figure 30
Fig 11. 1 kHz phase noise typical performance in hybrid application
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
32 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
001aac093
−85
Φosc
(dBc/Hz)
−90
−95
−100
150
250
350
450
550
650
750
850
fRF (MHz)
For measurement circuit see Figure 29 and Figure 30
Fig 12. 10 kHz phase noise typical performance in hybrid application
001aac094
−105
Φosc
(dBc/Hz)
−110
−115
−120
150
250
350
450
550
650
750
850
fRF (MHz)
For measurement circuit see Figure 29 and Figure 30
Fig 13. 100 kHz phase noise typical performance in hybrid application
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
33 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
signal
50 Ω source
e
LBIN
or
MBIN
Vmeas
50 Ω
V
27 Ω
IFOUTA
spectrum
analyzer
DUT
Vo
Vi
V'meas
50 Ω
IFOUTB
RMS
voltmeter
VCCA
fce747
Zi >> 50 Ω → Vi = 2 × Vmeas = 70 dBµV.
Vi = Vmeas + 6 dB = 70 dBµV.
Vo = V’meas + 3.75 dB.
V
G v = 20 log -----o- .
Vi
ISDB-T and NTSC Japan.
IF = 57 MHz.
Fig 14. Gain (GV) measurement in low and mid band with asymmetrical IF output
signal
50 Ω source
e
Vmeas
LBIN
or
MBIN
V
50 Ω
transformer
IFOUTA
DUT
Vi
spectrum
analyzer
C
N1
Vo
N2
50 Ω
V'meas
IFOUTB
RMS
voltmeter
fce748
Zi >> 50 Ω → Vi = 2 × Vmeas = 70 dBµV.
Vi = Vmeas + 6 dB = 70 dBµV.
Vo = V’meas + 15 dB (transformer ratio N1/N2 = 5 and transformer loss).
V
G v = 20 log -----o- .
Vi
ISDB-T and NTSC Japan.
IF = 57 MHz.
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Fig 15. Gain (GV) measurement in low and mid band with symmetrical IF output
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
34 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
NOISE
SOURCE
BNC
RIM
LBIN
or
MBIN
INPUT
CIRCUIT
27 Ω
NOISE
FIGURE
METER
IFOUTA
DUT
IFOUTB
VCCA
fce750
NF = NFmeas − loss of input circuit (dB).
Fig 16. Noise figure (NF) measurement in low and mid band with asymmetrical IF output
BNC
connector Cs
Lp
Cc
TL
to the IC
mixer input
BNC
connector
Cc
Ls
Lp
Cp
TL
to the IC
mixer input
Cp
mce452
a. Schematic 1
b. Schematic 2
For fRF = 150 MHz
For fRF = 300 MHz
Loss = 0 dB.
Loss = 0.5 dB.
Cs = 0.8 pF to 8 pF trimmer.
Ls = 2 turns, 1.5 mm, 0.4 mm wire air coil.
Cp = 0.4 pF to 2.5 pF trimmer.
Cp = 8.2 pF in parallel with a 0.8 pF to 8 pF trimmer.
Lp = 4 turns, 4.5 mm, 0.4 mm wire air coil.
Lp = 2 turns, 1.5 mm, 0.4 mm wire air coil.
Cc = 4.7 nF.
Cc = 4.7 nF.
TL: 50 Ω semi rigid cable length = 75 mm.
TL: 50 Ω semi rigid cable length = 75 mm.
Fig 17. Input circuit for optimum noise figure measurement
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
35 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
FILTER
AM = 30 %
1 kHz
50 Ω
A
unwanted
signal
source
eu
LBIN
IFOUTA
or
MBIN
C
HYBRID
B
modulation
analyzer
57 MHz
V Vmeas
50 Ω
IFOUTB
D
wanted
signal
source
ew
27 Ω
Vo
DUT
50 Ω
10 dB
attenuator
50 Ω
VCCA
RMS
voltmeter
001aac095
Vo = Vmeas + 3.75 dB.
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
Wanted signal source at fRFpix is 80 dBµV.
Unwanted output signal at fsnd.
The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal.
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Fig 18. Cross modulation measurement in low and mid band with asymmetrical IF output
FILTER
AM = 30 %
1 kHz
50 Ω
A
eu
unwanted
signal
source
LBIN
or
MBIN
C
HYBRID
transformer
IFOUTA
DUT
modulation
analyzer
C
N1
N2 V V'meas
57 MHz
50 Ω
Vo
50 Ω
B
ew
6 dB
attenuator
wanted
signal
source
D
IFOUTB
50 Ω
RMS
voltmeter
001aac096
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
Wanted signal source at fRFpix is 80 dBµV.
The level of unwanted signal Vo at fsnd is measured by causing 0.3 % AM modulation in the wanted output signal.
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Fig 19. Cross modulation measurement in low and mid band with symmetrical IF output
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
36 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
signal
50 Ω source
A
e
Vmeas
50 Ω
V
Vi
HBIN1
C
DUT
HYBRID
B
IFOUTA
HBIN2
D
27 Ω
spectrum
analyzer
Vo
V'meas
50 Ω
IFOUTB
RMS 50 Ω
voltmeter
VCCA
fce751
Loss in hybrid = 1 dB.
Vi = Vmeas − loss = 70 dBµV.
Vo = V’meas + 3.75 dB.
V
G v = 20 log -----o- .
Vi
ISDB-T and NTSC Japan.
IF = 57 MHz.
Fig 20. Gain (GV) measurement in high band with asymmetrical IF output
signal
50 Ω source
A
e
Vmeas
V
50 Ω
Vi
C
HBIN1
DUT
HYBRID
B
D
HBIN2
transformer
IFOUTA
spectrum
analyzer
C
N1
Vo
N2
50 Ω
V'meas
IFOUTB
RMS 50 Ω
voltmeter
fce752
Loss in hybrid = 1 dB.
Vi = Vmeas − loss = 70 dBµV.
Vo = V’meas + 15 dB (transformer ratio N1/N2 = 5 and transformer loss).
V
G v = 20 log -----o- .
Vi
ISDB-T and NTSC Japan.
IF = 57 MHz.
Fig 21. Gain (GV) measurement in high band with symmetrical IF output
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
37 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
NOISE
SOURCE
27 Ω
A
C
HBIN1
DUT
HYBRID
B
D
NOISE
FIGURE
METER
IFOUTA
HBIN2
IFOUTB
50 Ω
VCCA
fce753
Loss in hybrid = 1 dB.
NF = NFmeas − loss.
Fig 22. Noise figure (NF) measurement in high band with asymmetrical IF output
FILTER
AM = 30 %
1 kHz
50 Ω
A
eu
unwanted
signal
source
A
C
C
HYBRID
HYBRID
B
B
27 Ω
HBIN1
10 dB
attenuator
IFOUTA
modulation
analyzer
DUT
Vo
57 MHz
V Vmeas
50 Ω
50 Ω
ew
wanted
signal
source
D
50 Ω
50 Ω
D
HBIN2
IFOUTB
VCCA
RMS
voltmeter
001aac097
Vo = Vmeas + 3.75 dB.
Wanted signal source at fRFpix is 70 dBµV.
Unwanted output signal at fsnd.
The level of unwanted signal is measured by causing 0.3 % AM modulation in the wanted signal.
Fig 23. Cross modulation measurement in high band with asymmetrical IF output
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
38 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
AM = 30 %
1 kHz
50 Ω
eu
unwanted
signal
source
50 Ω
ew
transformer
A
A
C
HYBRID
B
B
D
wanted
signal
source
HBIN1 IFOUTA
C
HYBRID
DUT
D
modulation
analyzer
N1
Vo
C
N2
57 MHz
V V'meas
50 Ω
HBIN2 IFOUTB
RMS
voltmeter
50 Ω
50 Ω
FILTER
6 dB
attenuator
001aac098
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
Wanted signal source at fRFpix is 70 dBµV.
The level of unwanted signal Vo at fsnd is measured by causing 0.3 % AM modulation in the wanted output signal.
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Fig 24. Cross modulation measurement in high band with symmetrical IF output
signal
50 Ω source
e
LBIN
or
MBIN
Vmeas
spectrum
analyzer
DUT
50 Ω
V
27 Ω
IFOUTA
50 Ω
IFOUTB
RMS
voltmeter
VCCA
fce755
Zi >> 50 Ω → Vi = 2 × Vmeas.
Vi = Vmeas + 6 dB.
Fig 25. Maximum RF input level without lock-out in low and mid band with asymmetrical IF output
signal
50 Ω source
27 Ω
A
e
Vmeas
V
50 Ω
Vi
D
IFOUTA
HBIN1
spectrum
analyzer
DUT
HYBRID
B
RMS
voltmeter
C
HBIN2
50 Ω
50 Ω
IFOUTB
VCCA
fce756
Loss in hybrid = 1 dB.
Vi = Vmeas − loss.
Fig 26. Maximum RF input level without lock-out in high band with asymmetrical IF output
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
39 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
The TDA6650ATT; TDA6651ATT PLL loop stability is guaranteed in the configuration of
the Figure 27 to Figure 30. In this configuration, the external supply source is 30 V
minimum, the pull-up resistor, R19 is 15 kΩ and all of the local oscillators are aligned to
operate at a maximum tuning voltage of 26 V. If the configuration is changed, there might
be an impact on the loop stability.
For any other configurations, a stability analysis must be performed. The conventional PLL
AC model used for the stability analysis, is valid provided the external source (DC supply
source or DC-to-DC converter) is able to deliver a minimum current that is equal to the
charge pump current in use.
The delivered current can be simply calculated with the following formula:
V DC – V T
I delivered =  ------------------------ > I CP
 R pu 
(1)
where:
Idelivered is the delivered current.
VDC is the supply source voltage or DC-to-DC converter output voltage.
VT is the tuning voltage.
Rpu is the pull-up resistor between the DC supply source (or the DC-to-DC converter
output) and the tuning line (R19 in Figure 27 to Figure 30).
ICP is the charge pump current in use.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
40 of 54
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
J3
MID
J1
HIGH1
J2
HIGH2
C7
1.5 pF
N750
C6
C4
4.7 nF
6
1
12 pF
2
3
C26
12 pF
R21
1 kΩ
R22
1 kΩ
D7
R10
330 Ω
R9
330 Ω
R23
R11
330 Ω
1 kΩ
D8
1 (38)
(1) 38
2 (37)
(2) 37
(3) 36
3 (36)
(4) 35
4 (35)
(5) 34
5 (34)
(6) 33
6 (33)
7 (32)
TDA6650ATT (7) 32
8 (31) (TDA6651ATT) (8) 31
(9) 30
9 (30)
(10) 29
10 (29)
11 (28)
(11) 28
(12) 27
12 (27)
(13) 26
13 (26)
(14) 25
14 (25)
(15) 24
15 (24)
(16) 23
16 (23)
(17) 22
17 (22)
(18) 21
18 (21)
(19) 20
19 (20)
C19
Y1
18 pF
4 MHz
5 V bus
R24
C5
BB182
15 pF
N750
ST2
ADC
R27
3.3 kΩ
VCC
R14
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
L1
25 nH
R28
3.3 kΩ
SCL
SDA
R3
33 pF
N750
5.6 kΩ
D2
BB178
R4
5.6 kΩ
33 pF
N750
C11 1 pF
N750
C12 1 pF
N750
C13 1 pF
PLLGND
VCCD
D3
BB179
L2
16 nH
R02255
R5
5.6 kΩ
C18
N750
VCC
CP
VT
n.c.
XTAL2
C14 1 pF
R6
27 Ω
N750
8.2 pF
N470
R8
C17
3.9 nF
5.6 kΩ
VCC
VCC
C15
4.7 nF
C34
C33
R13
6.8 kΩ
VCC
C23
4.7 nF
C21
47 nF
C16
4.7 nF
5 V bus
1 kΩ
ST1
R2
R7
1 kΩ
C20
470 pF
30 V
AS
C29
4.7 nF
1 kΩ
J8
1 2 3 4 5 6
C31
10 µF
J7
C32
10 µF
C30
10 µF
1 2 3 4
J5
R19
15 kΩ
R26
27 Ω
J6
41 of 54
© NXP B.V. 2007. All rights reserved.
test
5 V bus
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 27. Measurement circuit for digital application, with asymmetrical IF output and ISDB-T compliant loop filter
30 V
IF out
001aac099
TDA6650ATT; TDA6651ATT
Rev. 02 — 2 February 2007
R20
1 kΩ
D6
D1
5 V mixer/oscillator and low noise PLL synthesizer
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
C28
150 nF
D5
1 pF
N750
R1
12 Ω
5.6 kΩ
AGC
D4
C2
4.7 nF
* 4t
C27
TP1
C1
4.7 nF
4
2
L4
TOKO
500 nH
C3
4.7 nF
L3
88 nH
R07254
NXP Semiconductors
TDA6650ATT_6651ATT_2
Product data sheet
J4
LOW
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
J3
MID
J1
HIGH1
J2
HIGH2
C7
1.5 pF
N750
C6
C4
4.7 nF
6
C1
4.7 nF
1
12 pF
2
3
C26
12 pF
R21
1 kΩ
R22
1 kΩ
R9
330 Ω
R23
R10
330 Ω
R11
330 Ω
1 kΩ
D8
C5
BB182
15 pF
N750
1 (38)
2 (37)
3 (36)
4 (35)
5 (34)
6 (33)
7 (32)
8 (31)
TDA6651ATT
9 (30)
10 (29)
11 (28)
12 (27)
13 (26)
14 (25)
15 (24)
16 (23)
17 (22)
18 (21)
19 (20)
ST2
ADC
Y1
18 pF
4 MHz
R27
3.3 kΩ
VCC
ST1
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
L1
25 nH
R28
3.3 kΩ
SCL
SDA
R3
33 pF
N750
5.6 kΩ
D2
BB178
R4
5.6 kΩ
33 pF
N750
C11 1 pF
N750
C12 1 pF
D3
BB179
L2
16 nH
R02255
N750
C13 1 pF
PLLGND
VCCD
C14 1 pF
R6
27 Ω
N750
VCC
R13
6.8 kΩ
8.2 pF
N470
R8
C17
3.9 nF
5.6 kΩ
R7
1 kΩ
C23
4.7 nF
C24
4.7 nF
C21
47 nF
C16
4.7 nF
R5
5.6 kΩ
C18
N750
VCC
CP
VT
n.c.
XTAL2
C15
4.7 nF
C34
C33
5 V bus
1 kΩ
R14
(1) 38
(2) 37
(3) 36
(4) 35
(5) 34
(6) 33
(7) 32
(8) 31
(9) 30
(10) 29
(11) 28
(12) 27
(13) 26
(14) 25
(15) 24
(16) 23
(17) 22
(18) 21
(19) 20
C19
5 V bus
R24
R2
C25
C20
470 pF
12 pF
VCC
C29
4.7 nF
1 kΩ
J8
1 2 3 4 5 6
C31
10 µF
C32
10 µF
C30
10 µF
1
R19
15 kΩ
30 V
AS
1 2 3 4
J5
2
3
TR1
TOKO
7451
30 V
6
4
J6
J7
42 of 54
© NXP B.V. 2007. All rights reserved.
test
5 V bus
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 28. Measurement circuit for digital application, with symmetrical IF output and ISDB-T compliant loop filter
IF out
001aac100
TDA6650ATT; TDA6651ATT
Rev. 02 — 2 February 2007
R20
1 kΩ
D7
D1
5 V mixer/oscillator and low noise PLL synthesizer
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
C28
150 nF
D6
R1
12 Ω
5.6 kΩ
AGC
D5
1 pF
N750
4
C27
D4
C2
4.7 nF
2 * 4t
L4
TOKO
500 nH
TP1
C3
4.7 nF
L3
88 nH
R07254
NXP Semiconductors
TDA6650ATT_6651ATT_2
Product data sheet
J4
LOW
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
J3
MID
J1
HIGH1
J2
HIGH2
C7
1.5 pF
N750
C6
C4
4.7 nF
6
1
12 pF
2
3
C26
12 pF
R21
1 kΩ
R22
1 kΩ
D7
R10
330 Ω
R9
330 Ω
R23
R11
330 Ω
1 kΩ
D8
1 (38)
(1) 38
2 (37)
(2) 37
(3) 36
3 (36)
(4) 35
4 (35)
(5) 34
5 (34)
(6) 33
6 (33)
7 (32)
TDA6650ATT (7) 32
8 (31) (TDA6651ATT) (8) 31
(9) 30
9 (30)
(10) 29
10 (29)
11 (28)
(11) 28
(12) 27
12 (27)
(13) 26
13 (26)
(14) 25
14 (25)
(15) 24
15 (24)
(16) 23
16 (23)
(17) 22
17 (22)
(18) 21
18 (21)
(19) 20
19 (20)
C19
Y1
18 pF
4 MHz
5 V bus
R24
C5
BB182
15 pF
N750
ST2
ADC
R27
3.3 kΩ
VCC
R14
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
L1
25 nH
C11 1 pF
R28
3.3 kΩ
SCL
SDA
R3
33 pF
N750
5.6 kΩ
D2
BB178
R4
5.6 kΩ
33 pF
N750
N750
C12 1 pF
N750
C13 1 pF
PLLGND
VCCD
D3
BB179
L2
16 nH
R02255
C14 1 pF
N750
R5
5.6 kΩ
C18
N750
VCC
CP
VT
n.c.
XTAL2
R6
27 Ω
8.2 pF
N470
R8
C17
4.7 nF
5.6 kΩ
VCC
VCC
C15
4.7 nF
C34
C33
R13
1.8 kΩ
VCC
C23
4.7 nF
C21
100 nF
C16
4.7 nF
5 V bus
1 kΩ
ST1
R2
R7
1 kΩ
C20
2.7 nF
30 V
AS
C29
4.7 nF
1 kΩ
J8
1 2 3 4 5 6
C31
10 µF
J7
C32
10 µF
C30
10 µF
1 2 3 4
J5
R19
15 kΩ
R26
27 Ω
J6
43 of 54
© NXP B.V. 2007. All rights reserved.
test
30 V
5 V bus
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 29. Measurement circuit for hybrid application, with asymmetrical IF output and loop filter for NTSC Japan and ISDB-T standards
IF out
001aac044
TDA6650ATT; TDA6651ATT
Rev. 02 — 2 February 2007
R20
1 kΩ
D6
D1
5 V mixer/oscillator and low noise PLL synthesizer
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
C28
150 nF
D5
1 pF
N750
R1
12 Ω
5.6 kΩ
AGC
D4
C2
4.7 nF
* 4t
C27
TP1
C1
4.7 nF
4
2
L4
TOKO
500 nH
C3
4.7 nF
L3
88 nH
R07254
NXP Semiconductors
TDA6650ATT_6651ATT_2
Product data sheet
J4
LOW
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
J3
MID
J1
HIGH1
J2
HIGH2
C7
1.5 pF
N750
C6
C4
4.7 nF
6
C1
4.7 nF
1
12 pF
2
3
C26
12 pF
R21
1 kΩ
R22
1 kΩ
R11
330 Ω
R10
330 Ω
R9
330 Ω
R23
1 kΩ
D8
C5
BB182
15 pF
N750
1 (38)
2 (37)
3 (36)
4 (35)
5 (34)
6 (33)
7 (32)
8 (31)
TDA6651ATT
9 (30)
10 (29)
11 (28)
12 (27)
13 (26)
14 (25)
15 (24)
16 (23)
17 (22)
18 (21)
19 (20)
ST2
ADC
Y1
18 pF
4 MHz
R27
3.3 kΩ
VCC
ST1
LOSCIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
IFOUTA
IFOUTB
VCCA
L1
25 nH
R28
3.3 kΩ
SCL
SDA
R3
33 pF
N750
5.6 kΩ
D2
BB178
R4
5.6 kΩ
33 pF
N750
C11 1 pF
N750
C12 1 pF
D3
BB179
L2
16 nH
R02255
N750
C13 1 pF
PLLGND
VCCD
C14 1 pF
R6
27 Ω
N750
VCC
C21
100 nF
C16
4.7 nF
R13
1.8 kΩ
R5
5.6 kΩ
C18
N750
VCC
CP
VT
n.c.
XTAL2
C15
4.7 nF
C34
C33
5 V bus
1 kΩ
R14
(1) 38
(2) 37
(3) 36
(4) 35
(5) 34
(6) 33
(7) 32
(8) 31
(9) 30
(10) 29
(11) 28
(12) 27
(13) 26
(14) 25
(15) 24
(16) 23
(17) 22
(18) 21
(19) 20
C19
5 V bus
R24
R2
8.2 pF
N470
R8
C17
4.7 nF
5.6 kΩ
R7
1 kΩ
C23
4.7 nF
C24
4.7 nF
C25
C20
2.7 nF
12 pF
VCC
C29
4.7 nF
1 kΩ
J8
1 2 3 4 5 6
C31
10 µF
C32
10 µF
C30
10 µF
1
R19
15 kΩ
30 V
AS
1 2 3 4
J5
2
3
TR1
TOKO
7451
30 V
6
4
J6
J7
44 of 54
© NXP B.V. 2007. All rights reserved.
test
IF out
5 V bus
The pin numbers in parenthesis represent the TDA6651ATT.
Fig 30. Measurement circuit for hybrid application, with symmetrical IF output and loop filter for NTSC Japan and ISDB-T standards
001aac101
TDA6650ATT; TDA6651ATT
Rev. 02 — 2 February 2007
R20
1 kΩ
D7
D1
5 V mixer/oscillator and low noise PLL synthesizer
HBIN1
HBIN2
MBIN
LBIN
RFGND
IFFIL1
IFFIL2
BS4
AGC
BS3
BS2
BS1
BVS
ADC/BS5
SCL
SDA
AS
XTOUT
XTAL1
C28
150 nF
D6
R1
12 Ω
5.6 kΩ
AGC
D5
1 pF
N750
4
C27
D4
C2
4.7 nF
2 * 4t
L4
TOKO
500 nH
TP1
C3
4.7 nF
L3
88 nH
R07254
NXP Semiconductors
TDA6650ATT_6651ATT_2
Product data sheet
J4
LOW
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
13. Application information
13.1 Tuning amplifier
The tuning amplifier is capable of driving the varicap voltage without an external transistor.
The tuning voltage output must be connected to an external load of 15 kΩ which is
connected to the tuning voltage supply rail. The loop filter design depends on the oscillator
characteristics and the selected reference frequency as well as the required PLL loop
bandwidth.
Applications with the TDA6650ATT; TDA6651ATT have a large loop bandwidth, in the
order of a few tens of kHz. The calculation of the loop filter elements has to be done for
each application, it depends on the reference frequency and charge pump current.
13.2 Crystal oscillator
The TDA6650ATT; TDA6651ATT needs to be used with a 4 MHz crystal in series with a
capacitor with a typical value of 18 pF, connected between pin XTAL1 and pin XTAL2.
Philips crystal 4322 143 04093 is recommended. When choosing a crystal, take care to
select a crystal able to withstand the drive level of the TDA6650ATT; TDA6651ATT without
suffering from accelerated ageing. For optimum performances, it is highly recommended
to connect the 4 MHz crystal without any serial resistance.
The crystal oscillator of the TDA6650ATT; TDA6651ATT should not be driven (forced)
from an external signal. Do not use the signal on pins XTAL1 or XTAL2, or the signal
present on the crystal, to drive an external IC or for any other use as this may dramatically
degrade the phase noise performance of the TDA6650ATT; TDA6651ATT.
13.3 Examples of I2C-bus program sequences
Table 21 to Table 26 show various sequences where:
S = START
A = acknowledge
P = STOP.
The following conditions apply:
LO frequency is 800 MHz
fcomp = 142.86 kHz
N = 5600
BS3 output port is on and all other ports are off: thus the high band is selected
Charge pump current ICP = 600 µA
Normal mode, with XTOUT buffer on
IAGC = 220 nA
AGC take-over point is set to 112 dBµV (p-p)
Address selection is adjusted to make address C2 valid.
To fully program the device, either sequence of Table 21 or Table 22 can be used, while
other arrangements of the bytes are also possible.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
45 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 21.
Complete sequence 1
Start
Address
byte
Divider
byte 1
Divider
byte 2
Control
byte 1[1]
Control
byte 2
Control
byte 1[2]
Stop
S
C2
15
E0
C9
E4
84
P
A
A
A
A
A
[1]
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1
and R0.
[2]
Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits
AL2, AL1 and AL0.
Table 22.
Complete sequence 2
Start
Address
byte
Control
byte 1[1]
Control
byte 2
Divider
byte 1
Divider
byte 2
Control
byte 1[2]
Stop
S
C2
C9
E4
15
E0
84
P
A
A
A
A
A
A
[1]
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1
and R0.
[2]
Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits
AL2, AL1 and AL0.
Table 23.
Sequence to program only the main divider ratio
Start
Address byte
Divider byte 1
Divider byte 2
Stop
S
C2
15
E0
P
Table 24.
A
A
A
Sequence to change the charge pump current, the ports and the test mode. If the
reference divider ratio is changed, it is necessary to send the DB1 and DB2 bytes
Start
Address byte
Control byte 1[1]
Control byte 2
Stop
S
C2
C9
E4
P
[1]
A
A
Sequence to change the test mode. If the reference divider ratio is changed, it is
necessary to send the DB1 and DB2 bytes
Start
Address byte
S
C2
[1]
A
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1
and R0.
Table 25.
A
Control byte 1[1]
Stop
C9
P
A
Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1
and R0.
Table 26.
Sequence to change the charge pump current, the ports and the AGC data
Start
Address byte
Control byte 1[1]
Control byte 2
Stop
S
C2
82
E4
P
[1]
A
A
A
Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits
AL2, AL1 and AL0.
TDA6650ATT_6651ATT_2
Product data sheet
A
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
46 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
Table 27.
Sequence to change only the AGC data
Start
Address byte
S
C2
[1]
A
Stop
84
P
A
Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits
AL2, AL1 and AL0.
TDA6650ATT_6651ATT_2
Product data sheet
Control byte 1[1]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
47 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
14. Package outline
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
SOT510-1
E
D
A
X
c
HE
y
v M A
Z
20
38
A2
(A 3)
A
A1
pin 1 index
θ
Lp
L
1
19
bp
e
detail X
w M
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.85
0.25
0.27
0.17
0.20
0.09
9.8
9.6
4.5
4.3
0.5
6.4
1
0.7
0.5
0.2
0.08
0.08
0.49
0.21
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT510-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-02-18
05-11-02
MO-153
Fig 31. Package outline SOT510-1 (TSSOP38)
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
48 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
49 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 28 and 29
Table 28.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 29.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
50 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Abbreviations
Table 30.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AGC
Automatic Gain Control
ISDB-T
Integrated Services Digital Broadcasting - Terrestrial
NTSC
National Telecommunications Standards Committee
PLL
Phase-Locked Loop
PMOS
Positive Channel Metal Oxide Semiconductor
QAM
Quadrature Amplitude Modulation
VCO
Voltage-Controlled Oscillator
VCR
Video Cassette Recorder
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
51 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
18. Revision history
Table 31.
Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
TDA6650ATT_6651ATT_2
20070202
Product data sheet
-
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
•
TDA6650ATT_6651ATT_1
(9397 750 14179)
Created Table 1 and updated Table 3 and 20 with new type numbers, emphasizing the
different types for hybrid and digital only applications.
Two values changed in Table 20; page 27 VAGC < VCC replaced with VAGC < 3.5 V and for
Vo(dis) new minimum value of 3.3 V added.
20041214
Product data sheet
TDA6650ATT_6651ATT_2
Product data sheet
TDA6650ATT_6651ATT_1
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
52 of 54
TDA6650ATT; TDA6651ATT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
TDA6650ATT_6651ATT_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 2 February 2007
53 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
21. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.2
7.3
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.2
8.3
9
10
11
12
13
13.1
13.2
13.3
14
15
16
16.1
16.2
16.3
16.4
17
18
19
19.1
19.2
19.3
19.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Application summary . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 6
Mixer, Oscillator and PLL (MOPLL) functions. . 6
I2C-bus voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7
Phase noise, I2C-bus traffic and crosstalk . . . . 7
2
I C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write mode; R/W = 0 . . . . . . . . . . . . . . . . . . . . 8
I2C-bus address selection. . . . . . . . . . . . . . . . 10
XTOUT output buffer and mode setting . . . . . 10
Step frequency setting . . . . . . . . . . . . . . . . . . 10
AGC detector setting . . . . . . . . . . . . . . . . . . . 11
Charge pump current setting . . . . . . . . . . . . . 11
Read mode; R/W = 1 . . . . . . . . . . . . . . . . . . . 12
Status at power-on reset. . . . . . . . . . . . . . . . . 13
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal characteristics. . . . . . . . . . . . . . . . . . 19
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application information. . . . . . . . . . . . . . . . . . 45
Tuning amplifier. . . . . . . . . . . . . . . . . . . . . . . . 45
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 45
Examples of I2C-bus program sequences . . . 45
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48
Handling information. . . . . . . . . . . . . . . . . . . . 49
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Introduction to soldering . . . . . . . . . . . . . . . . . 49
Wave and reflow soldering . . . . . . . . . . . . . . . 49
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 49
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 50
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 52
Legal information. . . . . . . . . . . . . . . . . . . . . . . 53
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 53
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 February 2007
Document identifier: TDA6650ATT_6651ATT_2