TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 D D D D D D applications Dual 8-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time – 2.5 µs in Fast Mode – 12 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity <0.2 LSB Max Monotonic Over Temperature D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices D PACKAGE (TOP VIEW) DIN SCLK CS OUTA description The TLV5625 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface is compatible with TMS320, SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 8 data bits. 1 8 2 7 3 6 4 5 VDD OUTB REF AGND The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE TA SOIC (D) 0°C to 70°C TLV5625CD – 40°C to 85°C TLV5625ID Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright 2000, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW features TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 functional block diagram REF AGND VDD Power and Speed Control Power-On Reset 2 x2 OUTA x2 OUTB DIN 8 PRODUCT PREVIEW SCLK Serial Interface and Control CS 8-Bit DAC A Latch 8 8 Buffer 8 8-Bit DAC B Latch 8 Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs. DIN 1 I Digital serial data input OUTA 4 O DAC A analog voltage output OUTB 7 O DAC B analog voltage output REF 6 I Analog reference voltage input SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5625C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5625I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VDD = 5 V VDD = 3 V Power on reset, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal Reference voltage, Vref to REF terminal NOM MAX 4.5 5 5.5 2.7 3 3.3 0.55 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V 2 2 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) Load resistance, RL UNIT V V V AGND 2.048 AGND 1.024 0.8 V VDD –1.5 VDD – 1.5 V 2 V kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz Operating free-air free air temperature, temperature TA TLV5625C TLV5625I PRODUCT PREVIEW Supply voltage voltage, VDD MIN 0 70 –40 85 °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER IDD TEST CONDITIONS No load, All inputs = AGND or VDD, DAC latch = 0x800 supply Power su lyy current TYP MAX Fast MIN 1.8 2.3 Slow 0.8 1 1 3 Power-down supply current PSRR Power supply rejection ratio Zero scale, See Note 2 –65 Full scale, –65 See Note 3 UNIT mA µA dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN PRODUCT PREVIEW Resolution TYP MAX UNIT 8 bits INL Integral nonlinearity See Note 4 ± 0.3 ± 0.5 LSB DNL Differential nonlinearity See Note 5 ± 0.07 ± 0.2 LSB EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 EG TC Gain-error temperature coefficient See Note 9 ± 12 10 mV ppm/°C ± 0.5 10 % full scale V ppm/°C NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale, excluding the effects of zero-code and full-scale errors. 5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ. 9. Gain temperature coefficient is given by: EG TC = [EG (Tmax) – Eg (Tmin)]/2Vref × 106/(Tmax – Tmin). output specifications PARAMETER VO TEST CONDITIONS Output voltage range RL = 10 kΩ Output load regulation accuracy VO = 4.096 V, 2.048 V RL = 2 kΩ MIN TYP 0 MAX UNIT VDD–0.4 ± 0.29 % FS MAX UNIT V reference input PARAMETER VI RI Input voltage range CI Input capacitance TEST CONDITIONS TYP 0 Input resistance Reference input bandwidth 0 2 Vpp + 1.024 1 024 V dc REF = 0.2 Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. 4 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VDD–1.5 V 10 MΩ 5 pF Fast 1.3 MHz Slow 525 kHz – 80 dB TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP MAX 1 UNIT µA µA –1 8 pF analog output dynamic performance TEST CONDITIONS CL = 100 pF,, MIN TYP Fast 2.5 Slow 12 Fast 1 Slow 2 Fast 3 Slow 0.5 ts(FS) (FS) Output settling time, time full scale RL = 10 kΩ,, See Note 11 ts(CC) (CC) time code to code Output settling time, RL = 10 kΩ,, See Note 12 CL = 100 pF,, SR Slew rate RL = 10 kΩ,, See Note 13 CL = 100 pF,, Glitch energy DIN = 0 to 1, CS = VDD FCLK = 100 kHz, Signal-to-noise ratio 52 54 SINAD Signal-to-noise + distortion 48 49 THD Total harmonic distortion SFDR Spurious free dynamic range –50 48 UNIT µs µs V/µs 5 SNR fs = 102 kSPS,, fout = 1 kHz,, RL = 10 kΩ, CL = 100 pF MAX nV–s –48 dB 50 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PRODUCT PREVIEW PARAMETER TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 digital input timing requirements MIN NOM MAX UNIT tsu(CS–CK) tsu(C16-CS) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge before CS rising edge 10 ns 10 ns twH twL SCLK pulse width high 25 ns SCLK pulse width low 25 ns tsu(D) th(D) Setup time, data ready before SCLK falling edge 10 ns Hold time, data held valid after SCLK falling edge 5 ns timing requirements twL SCLK X 1 2 PRODUCT PREVIEW tsu(D) DIN X twH 3 4 5 15 X 16 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT VO – Output Voltage – V 2.048 2.046 4.105 VDD=3 V VREF=1 V Full scale 3 V Fast Mode, SOURCE 5 V Slow Mode, SOURCE 4.100 2.044 2.042 2.040 2.038 2.036 4.095 5 V Fast Mode, SOURCE 4.090 4.085 4.080 4.075 4.070 0.00 –0.01 –0.02–0.05 –0.10 –0.20 –0.51 –1.02 –2.05 0.00 –0.02 –0.04–0.10 –0.20 –0.41 –1.02 –2.05 –4.10 Load Current - mA Load Current - mA Figure 2 Figure 3 OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 0.20 VO – Output Voltage – V 0.16 0.35 VDD=3 V VREF=1 V Zero scale 0.30 3 V Slow Mode, SINK 0.14 0.12 0.10 0.08 0.06 3 V Fast Mode, SINK VO – Output Voltage – V 0.18 VDD=5 V VREF=2 V Full scale PRODUCT PREVIEW 3 V Slow Mode, SOURCE VO – Output Voltage – V 2.050 OUTPUT VOLTAGE vs LOAD CURRENT VDD=5 V VREF=2 V Zero scale 5 V Slow Mode, SINK 0.25 0.20 0.15 5 V Fast Mode, SINK 0.10 0.04 0.05 0.02 0.00 0.00 0.01 0.02 0.05 0.10 0.20 0.51 1.02 2.05 0.00 0.00 0.02 0.04 0.10 0.20 0.41 1.02 2.05 4.09 Load Current - mA Load Current - mA Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.80 1.80 VDD=3 V VREF=1 V Full scale 1.60 Fast Mode I DD – Supply Current – mA 1.40 1.20 1.00 0.80 Slow Mode 0.60 0.40 1.40 VDD=5 V VREF=2 V Full scale 1.00 0.80 Slow Mode 0.60 0.40 0.20 0.20 0.00 –40.00–20.00 0.00 20.00 40.00 60.00 80.00 100.00120.00 0.00 –40.00–20.00 0.00 20.00 40.00 60.00 80.00 100.00120.00 TA - Free-Air Temperature - C TA - Free-Air Temperature - C Figure 7 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 0.00 0.00 VREF = 1 V + 1 VP/P Sinewave, Output Full Scale VREF = 1 V + 1 VP/P Sinewave, Output Full Scale –10.00 THD - Total Harmonic Distortion - dB –10.00 –20.00 –20.00 –30.00 –30.00 –40.00 –40.00 –50.00 3 V Slow Mode –50.00 3 V Fast Mode –60.00 5 V Slow Mode –60.00 –70.00 –70.00 5 V Fast Mode –80.00 –80.00 –90.00 –90.00 1 10 100 1 f - Frequency - kHz 10 f - Frequency - kHz Figure 8 8 Fast Mode 1.20 Figure 6 THD - Total Harmonic Distortion - dB PRODUCT PREVIEW I DD – Supply Current – mA 1.60 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 0 64 128 192 255 PRODUCT PREVIEW Digital Output Code Figure 10 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.5 0.4 0.3 0.2 0.1 –0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 64 128 192 255 Digital Output Code Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 APPLICATION INFORMATION general function The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by the reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0. A power-on reset initially puts the internal latches to a defined state (all bits zero). serial interface PRODUCT PREVIEW A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 2 shows examples of how to connect the TLV5625 to TMS320, SPI, and Microwire. TMS320 DSP FSX DX CLKX TLV5625 CS DIN SCLK SPI TLV5625 CS DIN SCLK I/O MOSI SCK Microwire I/O SO SK TLV5625 CS DIN SCLK Figure 12. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be performed to program the TLV5625. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax +t )t 1 whmin wlmin + 20 MHz The maximum update rate is: f updatemax + 16 ǒt 1 whmin )t Ǔ+ 1.25 MHz wlmin Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5625 should also be considered. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 APPLICATION INFORMATION data format The 16-bit data word for the TLV5625 consists of two parts: D D Program bits (D15..D12) New data (D11..D4) D15 D14 D13 D12 D11 R1 SPD PWR R0 MSB D10 D9 D8 D7 D6 D5 8 Data bits D4 D3 D2 D1 D0 LSB 0 0 0 0 SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation On power up, SPD and PWD are reset to 0 (slow mode and normal operation) The following table lists all possible combination of register-select bits: R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Reserved The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: examples of operation D Set DAC A output, select fast mode: Write new DAC A value and update DAC A output: D15 D14 D13 D12 1 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 New DAC A output value D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 0 0 0 0 The DAC A output is updated on the rising clock edge after D0 is sampled. D Set DAC B output, select fast mode: Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 New BUFFER content and DAC B output value The DAC A output is updated on the rising clock edge after D0 is sampled. D Set DAC A value, set DAC B value, update both simultaneously, select slow mode: 1. Write data for DAC B to BUFFER: D15 D14 D13 D12 0 0 0 1 D11 D10 D9 D8 D7 D6 D5 D4 New DAC B value 2. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 1 0 0 0 D11 D10 D9 D8 D7 D6 D5 New DAC A value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D4 11 PRODUCT PREVIEW register-select bits TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 APPLICATION INFORMATION examples of operation (continued) Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. D Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don’t care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. PRODUCT PREVIEW The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13. Output Voltage 0V DAC Code Negative Offset Figure 13. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 14 shows the ground plane layout and bypassing technique. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 APPLICATION INFORMATION Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 14. Power-Supply Bypassing definitions of specifications and terminology integral nonlinearity (INL) differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PRODUCT PREVIEW The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane PRODUCT PREVIEW 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 14 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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