TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 D D D D D D D D D D Organization TM124BBK32 . . . 1 048 576 × 32 TM248CBK32 . . . 2 097 152 × 32 Single 5-V Power Supply (±10 % Tolerance) 72-pin Single In-Line Memory Module (SIMM) for Use With Sockets TM124BBK32-Utilizes Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248CBK32-Utilizes Sixteen 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Distributed Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines, In Four Blocks Presence Detect D D D D D Performance Ranges: TM124BBK32-60 TM124BBK32-70 TM124BBK32-80 TM248CBK32-60 TM248CBK32-70 TM248CBK32-80 ACCESS TIME tRAC ACCESS TIME tCAC (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns (MAX) 15 ns 18 ns 20 ns 15 ns 18 ns 20 ns READ OR WRITE CYCLE (MIN) 110 ns 130 ns 150 ns 110 ns 130 ns 150 ns Low Power Dissipation Operating Free-Air-Temperature Range 0°C to 70°C Gold-Tabbed Versions Available:† – TM124BBK32 – TM248CBK32 Tin-Lead (Solder) Tabbed Versions Available: – TM124BBK32S – TM248CBK32S description TM124BBK32 The TM124BBK32 is a dynamic random-access memory (DRAM) organized as four times 1 048 576 × 8 in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44400, 1 048 576 × 4-bit DRAMs, each in 20/26-lead plastic SOJ packages, mounted on a substrate together with decoupling capacitors. Each TMS44400 is described in the TMS44400 data sheet. The TM124BBK32 is available in the single-sided BK leadless module for use with sockets. The TM124BBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from 0°C to 70°C TM248CBK32 The TM248CBK32 is a dynamic random-access memory organized as four times 2 097 152 × 8 in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS44400, 1 048 576 × 4-bit dynamic RAMs, each in 20/26-lead plastic SOJ packages SOJs, mounted on a substrate together with decoupling capacitors. Each TMS44400 is described in the TMS44400 data sheet. The TM248CBK32 is available in the double-sided BK leadless module for use with sockets. The TM248CBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from 0°C to 70°C operation TM124BBK32 The TM124BBK32 operates as eight TMS44400DJs connected as shown in the functional block diagram. Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM124BBK32 dictates the use of early write cycles to prevent contention on D and Q. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 TM248CBK32 The TM248CBK32 operates as sixteen TMS44400DJs connected as shown in the functional block diagram. Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM248CBK32 dictates the use of early write cycles to prevent contention on D and Q. refresh Refresh period is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS in order to retain data. A0-A9 address lines must be refreshed every 16 ms as required by the TMS44400 DRAM. CAS can remain high during the refresh sequence to conserve power. single in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124BBK32 AND TM248CBK32: Nickel plate and gold plate over copper. Contact area for TM124BBK32S AND TM248CBK32S: Nickel plate and tin-lead over copper. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 BK SINGLE IN-LINE MEMORY MODULE TM124BBK32† TM248CBK32† (TOP VIEW) (SIDE VIEW) (SIDE VIEW) VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN NOMENCLATURE A0–A9 CAS0–CAS3 DQ0–DQ31 NC PD1– PD4 RAS0–RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) VSS VSS VSS VSS 80 ns VSS NC VSS NC 70 ns NC NC 60 ns NC NC 80 ns TM124BBK32 70 ns 60 ns TM248CBK32 PD3 (69) PD4 (70) NC VSS NC VSS NC NC VSS NC NC VSS NC NC † The packages shown here are not drawn to scale. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 10 RAS0 RAS2 W CAS0 CAS1 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 1M × 4 A0 – A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ0 – DQ3 10 DQ4– DQ7 CAS3 CAS2 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ8 – DQ11 10 DQ12 – DQ15 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ16 – DQ19 10 DQ20 – DQ23 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 DQ24 – DQ27 DQ28 – DQ31 Template Release Date: 7–11–94 A0 – A9 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 4 functional block diagram (for TM124BBK32 and TM248CBK32, Side 1) functional block diagram (for TM248CBK32, Side 2) 10 A0 – A9 RAS1 RAS3 W CAS0 CAS1 10 DQ0 – DQ3 10 DQ4 – DQ7 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ8 – DQ11 10 DQ12 – DQ15 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ16 – DQ19 10 DQ20 – DQ23 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 DQ24 – DQ27 DQ28 – DQ31 5 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 SMMS132D – JANUARY 1991 – REVISED JUNE 1995 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 CAS3 CAS2 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS ’124BBK32-60 IOH = – 5 mA IOL = 4.2 mA MIN MAX 2.4 ’124BBK32-70 MIN MAX 2.4 ’124BBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ±10 ±10 ±10 µA II Input current (leakage) VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC IO Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ±10 ±10 ±10 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 840 720 640 mA 16 16 16 Standby current After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) After 1 memory cycle, RAS and CAS high, VIH = VCC – 0.2 V (CMOS) ICC2 mA 8 8 8 ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 840 720 640 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 720 640 560 mA tPC = minimum, CAS cycling NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS High-level output voltage Low-level output voltage ’248CBK32-60 MIN IOH = – 5 mA IOL = 4.2 mA MAX 2.4 ’248CBK32-70 MIN MAX 2.4 ’248CBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ±20 ±20 ±20 µA II Input current (leakage) VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC IO Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ±20 ±20 ±20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 856 736 656 mA 32 32 32 ICC2 After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) Standby current ICC3 Average refresh current (RAS only or CBR) (see Note 3) ICC4 Average page current (see Note 4) mA After 1 memory cycle, RAS and CAS high, VIH = VCC – 0.2 V (CMOS) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = minimum, CAS cycling 16 16 16 1680 1440 1280 mA 736 656 576 mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature f = 1 MHz (see Note 5) ’124BBK32 ’248CBK32 MIN MIN MAX MAX UNIT Ci(A) Input capacitance, address inputs 40 80 pF Ci(R) Input capacitance, RAS 28 28 pF Ci(C) Input capacitance, CAS 14 28 pF Ci(W) Input capacitance, W 56 112 pF Co(DQ) Output capacitance on DQ pins 7 14 pF NOTE 5: VCC = 5 V ± 0.5 V and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124BBK32-60 ’248CBK32-60 PARAMETER MIN MAX ’124BBK32-70 ’248CBK32-70 MIN MAX ’124BBK32-80 ’248CBK32-80 MIN UNIT MAX tAA tCAC Access time from column-address 30 35 40 ns Access time from CAS low 15 18 20 ns tCPA tRAC Access time from column precharge 35 40 45 ns 80 ns tCLZ tOFF CAS to output in low Z 0 Output disable time after CAS high (see Note 6) 0 Access time from RAS low 60 70 0 15 0 0 18 0 ns 20 ns NOTE 6: tOFF is specified when the output is no longer driven. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 timing requirements over recommended range of supply voltage and operating free-air temperature ’124BBK32-60 ’248CBK32-60 MIN tRC tPC Cycle time, random read or write (see Note 7) tCP tCAS MAX ’124BBK32-70 ’248CBK32-70 MIN MAX ’124BBK32-80 ’248CBK32-80 MIN UNIT MAX 110 130 150 ns Cycle time, page-mode read or write (see Note 8) 40 45 50 ns Pulse duration, CAS high 10 10 10 Pulse duration, CAS low 15 tRP tRASP Pulse duration, RAS high (precharge) 40 50 60 Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS tWP Pulse duration, nonpage mode, RAS low 60 70 80 ns Pulse duration, write 15 15 15 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data 0 0 0 ns Setup time, read before CAS low 0 0 0 ns tWCS tWSR Setup time, W low before CAS low 0 0 0 ns Setup time, W high (CBR refresh only) 10 10 10 ns tCWL tRWL Setup time, W low before CAS high 15 18 20 ns Setup time, W low before RAS high 15 18 20 ns tWTS tCAH Setup time, W low (test mode only) 10 10 10 ns Hold time, column address after CAS low 10 15 15 ns tRAH tAR Hold time, row address after RAS low 10 10 10 ns Hold time, column address after RAS low (see Note 9) 50 55 60 ns tDHR tDH Hold time, data after RAS low (see Note 9) 50 55 60 ns Hold time, data 10 15 15 ns tRCH tRRH Hold time, read after CAS high (see Note 10) 0 0 0 ns Hold time, read after RAS high (see Note 10) 0 0 0 ns tWCH tWHR Hold time, write after CAS low 15 15 15 ns Hold time, W high (CBR refresh only) 10 10 10 ns tWCR tWTH Hold time, write after RAS low 50 55 60 ns Hold time, W low (test mode only) 10 10 10 ns tCSH tCRP Delay time, RAS low to CAS high 60 70 80 ns Delay time, CAS high to RAS low 0 0 0 ns tRCD tCHR Delay time, RAS low to CAS low (see Note 11) 20 Delay time, RAS low to CAS high (CBR refresh only) 15 tCSR tRAD Delay time, CAS low to RAS low (CBR refresh only) 10 Delay time, RAS low to column address (see Note 11) 15 10 000 10 000 45 POST OFFICE BOX 1443 20 10 000 10 000 52 15 • HOUSTON, TEXAS 77251–1443 15 35 20 20 ns 10 000 10 000 60 15 40 ns ns 10 35 ns ns 20 10 30 tRAL Delay time, column address to RAS high 30 NOTES: 7. All cycle times assume tT = 5 ns. 8. To assure tPLmin, tASC should be ≥ 5 ns. 9. The minimum value is measured when tRCD is set to tRCD min as a reference. 10. Either tRRH or tRCH must be satisfied for a read cycle. 11. Maximum value specified only to assure access time. 8 18 ns 40 ns ns TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 timing requirements over recommended range of supply voltage and operating free-air temperature (concluded) ’124BBK32-60 ’248CBK32-60 MIN tCAL tRPC Delay time, column address to CAS high 0 tRSH tTAA Delay time, CAS low to RAS high 15 Access time from address (test mode) 35 tTRAC tTCPA Access time from RAS (test mode) Access time from column precharge (test mode) tREF tT Refresh time interval ’124BBK32-70 ’248CBK32-70 MAX 30 Delay time, RAS high to CAS low (CBR refresh only) MIN 35 MIN UNIT MAX 40 ns 0 0 ns 18 20 ns 40 45 ns 65 75 85 ns 40 45 50 16 Transition time MAX ’124BBK32-80 ’248CBK32-80 2 50 16 2 50 2 ns 16 ms 50 ns device symbolization (TM124BBK32 illustrated) TM124BBK36B –SS YY MM T –SS = = = = YYMMT Year Code Month Code Assembly Site Code Speed Code NOTE: Location of symbolization may vary. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated