ETC TMP96C031F

TOSHIBA
TLCS-900 Series
CMOS 16-bit Microcontrollers
TMP96C031N/TMP96C031F
1.
Outline and Device Characteristics
The TMP96C031 are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. TMP96C031N comes in a 64-pin shrink DIP; the
TMP96C031F, in a 64-pin flat package.
(1) Original 16-bit CPU
• TLCS-90 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed micro DMA
- 4 channels (1.6µs/2 bytes @ 20MHz)
(2) Minimum instruction execution time
- 200ns @ 20MHz
TMP96C031N/F
(3) External memory expansion
• Can be expanded up to 16M-bytes (for both programs and
data).
• External data bus width selection pin (AM8/16)
• Can mix 8- and 16-bit external data buses.
…
Dynamic data bus sizing
(4) 8-bit timer: 2 channels
(5) 16-bit timer: 2 channels
(6) Pattern generator: 4 bits, 2 channels
(7) Serial interface: 2 channels
(8) 8-bit A/D converter: 4 channels
(9) DRAM controller
(10) Watchdog timer
(11) Chip select/wait controller: 4 blocks
(12) Interrupt functions
• 3 CPU interrupts… …SWI instruction, privileged violation,
and Illegal instruction
• 12 internal interrupts
7-level priority can be set.
• 9 external interrupts
(13) I/O ports: 37 pins
(14) Standby function : 3 HALT modes (RUN, IDLE, STOP)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP96C031N/F
Figure 1. TMP96C031F Block Diagram
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TMP96C031N/F
2.
Pin Assignment and Functions
2.1 Pin Assignment
Figure 2.1 shows pin assignment of TMP96C031N.
Figure 2.1 (1). Pin Assignment (64-SDIP)
Figure 2.1 (2) shows pin assignment of TMP96C031F.
Figure 2.1 (2). Pin Assignment (64QFP)
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TMP96C031N/F
2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
Table 2.2. Pin Names and Functions
Pin Name
AD0 ~ AD7
I/O
Functions
8
Tri-state
Address/data (lower): 0 - 7 for address/data bus
AD8 ~ AD15
A8 ~ A15
8
Tri-state
Output
Address data (upper): 8 - 15 for address/data bus
Address: 8 to 15 for address bus
P20 ~ P27
A0 ~ A7
A16 ~ A23
8
I/O
Output
Output
Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)
Address: 0 - 7 for address bus
Address: 16 - 23 for address bus
P30
TO5
HWR
1
I/O
Output
Output
Port 30: Output port (with pull-up register)
Timer output 5: Timer 4 output pin
High write: Strobe signal for writing data on pins AD8 - 15
P31
TI0
WAIT
1
I/O
Output
Output
Port 31: Output port (with pull-up register)
Timer output 0: Timer 0 input
Write: Pin used to request CPU bus wait
P32
BUSRQ
1
I/O
Input
Port 32: I/O port (with pull-up register)
Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,
CS1, and CS2 pins. (For external DMAC)
P33
BUSAK
1
I/O
Input
Port 33: I/O port (with pull-up register)
Bus acknowledge: Strobe indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2
pins are at high impedance after receiving BUSRQ.
P34
R/W
NMI
1
I/O
Output
Input
Port 34: I/O (with pull-up register)
Read/write: 1 represents read or dummy cycle 0, write cycle.
Non-maskable interrupt request pin; Interrupt request pin with falling edge. Can also be operated at rising
edge by program.
P35
RAS
INT7
1
I/O
Output
Input
Port 35: I/O (with pull-up register)
Row address strobe: Outputs RAS strobe for DRAM.
Interrupt request pin 7: Interrupt request pin with rising edge.
P40
CS0
1
Output
Output
Port 40: I/O port
Chip select 0: Outputs 0 when address is within specified address area.
P41
CS1
1
Output
Output
Port 41: Output port
Chip select 1: Outputs 0 if address is within specified address area.
P42
CS2
1
Output
Output
Port 42: Output port
Chip select 2: Outputs 0 if address is within specified address area.
P43
CS3
CAS
1
Output
Output
Output
Port 43: Output port
Chip select 3: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.
Input
Input
Input
Port 50 ~ 53: Input port
Analog input: Input to A/D converter
Interrupt request pin 0: Interrupt request pin with programmable level/rising edge.
Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge.
Interrupt request pin 2 ~ 3: Interrupt request pin with rising edge.
P50 ~ P53
AN0 ~ AN3
INT1 ~ INT3
4
P60
TxD0
PG00
1
I/O
Output
Output
Port 60: I/O port
Serial send data 0
Pattern generator port 00
P61
RxD0
PG01
1
I/O
Output
Output
Port 61: I/O port
Serial receive data 0
Pattern generator port 01
Note:
4
Number
of Pins
The internal I/O of this device cannot be accessed using the external DMA controller.
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TMP96C031N/F
Number
of Pins
I/O
P62
CTS0
PG02
1
I/O
Output
Output
Port 62: I/O port
Serial data send enable 0 (Clear to Send)
Pattern generator port 02
P63
RFSH
PG03
1
I/O
Output
Output
Port 63: I/O port
Refresh out: This is a state signal output pin which indicates that the DRAM controller is in refresh cycle.
Pattern generator port 03
P64
PG10
1
I/O
Output
Port 64: I/O port
Pattern generator port 10
P65
PG11
1
I/O
Output
Port 65: I/O port
Pattern generator port 11
P66
INT6
PG12
1
I/O
Input
Output
Port 66: I/O port
Interrupt request pin 6: Interrupt request pin with rising edge.
Pattern generator port 12
P67
WDTOUT
PG13
1
I/O
Output
Output
Port 71: I/O port
Watchdog timer output pin
Pattern generator port 13
P70
TO1
TO4
1
I/O
Output
Output
Port 70: I/O port
Timer output 1: Timer 0 or 1 output pin
Timer output 4: Timer 4 output pin
P71
T03
DMUX
1
I/O
Output
Output
Port 71: I/O port
Timer output 3: Timer 2 or Timer 3 output pin
DRAM address multiplexor: This pin outputs row address, column address, and selector select signal.
P72
INT4
TI4
1
I/O
Input
Input
Port 72: I/O port
Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge.
Timer input 4: Timer 4 count/capture trigger signal input
P73
INT5
TI5
1
I/O
Input
Input
Port 73: I/O port
Interrupt request pin 5: Interrupt request pin with programmable rising edge.
Timer input 5: Timer 4 count/capture trigger signal input
P74
TxD1
1
I/O
Output
Port 74: I/O port
Serial send data 1
P75
RxD1
1
I/O
Input
Port 75: I/O port
Serial receive data 1
P76
SCLK1
1
I/O
I/O
CLK
1
Output
Clock output: Outputs X1÷ 4 clock. Pulled-up during reset.
RD
1
Output
Read: Strobe signal for reading external memory.
WR
1
Output
Write: Strobe signal for writing data on pins AD0 - 7.
1
Input
Address mode: External data bus width selection pin. Set to “0” for fixed external 16-bit bus or for mixed
external 8/16 bit bus and to “1” for fixed external 8-bit bus.
RESET
1
Input
Reset: Initializes LSI. (With pull-up resistor)
ALE
1
Output
Address latch enable
X1/X2
1
I/O
VCC
1
Power supply pin (-5V)
VSS
1
GND pin (0V)
Pin Name
AM8/16
Note:
Functions
Port 76: I/O port
Serial clock I/O 1
Oscillator connecting pin
Pull-up/pull-down resistor can be released from the pin by software.
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TMP96C031N/F
3.
Operation
This section describes in blocks the functions and basic operations of the TMP96C031F device.
Check the chapter Guidelines and Restrictions for proper
care of the device.
3.1 CPU
The TMP96C031F device has a built-in high-performance 16bit CPU. (For CPU operation, see TLCS-900 CPU in the book
Core Manual Architecture User Manual.)
This section describes CPU functions unique to
TMP96C031F that are not described in the previous section.
3.1.1 Reset
To reset the TMP96C031F, the RESET input must be kept at 0
for at least 10 system clocks (10 states: 1µs with a 20MHz
system clock) within an operating voltage range and with a stable oscillation.
When reset is accepted, the CPU sets as follows:
• Program counter (PC) to 8000H.
• Stack pointer (XSP) for system mode to 100H.
• SYSM bit of status register (SR) to 1. (Sets to system mode.)
• IFF2 to 0 bits of status register to 111. (Sets mask register to
interrupt level 7.)
• MAX bit of status register to 0. (Sets to minimum mode.)
• Bits RFP2 to 0 of status register to 000. (Sets register banks
to 0.)
When reset is released, instruction execution starts from
address 8000H. CPU internal registers other than the above
are not changed.
When reset is accepted, processing for built-in I/Os,
ports, and other pins is as follows:
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• Initializes built-in I/O registers as per specifications.
• Sets port pins (including pins also used as built-in I/Os) to
general-purpose input/output port mode (sets I/O ports to
input ports).
• Sets the WDTOUT pin to 0. (Watchdog timer is set to enable
after reset.)
• Pulls up the CLK pin to 1.
• Sets the ALE pin to 0.
3.1.2 External Data Bus Width Selection Pin (AM8/16)
The TMP96C031F automatically operates in 8-bit bus/16-bit
bus mode after reset depending on how the AM8/16 pin is set.
The TMP96C031F have altogether the following 23 interrupt sources:
• For mixed external 8/16-bit data bus or fixed 16-bit data bus
Set this pin to “0”. Then the AD8 to 15/A8 to 15 pins are
fixed to functions AD8 to 15.
The external data bus width is set by the chip select/wait
control register described in section 3.6.1.
• For fixed external 8-bit data bus
Set this pin to “1”. Then the AD8 to 15/A8 to 15 pins are
fixed to functions A8 to 15.
The value of chip select/wait control register bit 4
(<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS>) described in
Section 3.6.1 is ignored and the bus is fixed external 8-bit data
bus.
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3.2 Memory Map
Figure 3.2 is a memory map of the TMP96C031F.
Note: The start address after reset is 8000H. Resetting sets the stack pointer (XSP) on the system mode side to 100H.
Figure 3.2. Memory Map
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TMP96C031N/F
3.3 Interrupts
TLCS-900 interrupts are controlled by the CPU interrupt mask
flip-flop (IFF2 to 0) and the built-in interrupt controller.
TMP96C031F have altogether the following 24 interrupt
sources:
• Interrupts from the CPU…3
(Software interrupts, privileged violations, and Illegal (undefined) instruction execution)
• Interrupts from external pins (NMI, INT0, and INT0 to 7)…9
• Interrupts from built-in I/Os…12
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TMP96C031N/F
A fixed individual interrupt vector number is assigned to
each interrupt source; six levels of priority (variable) can also be
assigned to each maskable interrupt. Non-maskable interrupts
have a fixed priority of 7.
When an interrupt is generated, the interrupt controller
sends the value of the priority of the interrupt source to the
CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest
priority (7 for non-maskable interrupts is the highest) to the
CPU.
The CPU compares the value of the priority sent with the
value in the CPU interrupt mask register (IFF2 to 0). If the value
is greater than that of the CPU interrupt mask register, the
interrupt is accepted. The value in the CPU interrupt mask register (IFF2 to 0) can be changed using the EI instruction (contents of the EI num/IFF <2:0> = num). For example,
programming EI 3 enables acceptance of maskable interrupts
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with a priority of 3 or greater, and non-maskable interrupts
which are set in the interrupt controller. The DI instruction (IFF
<2:0> = 7) operates in the same way as the EI 7 instruction.
Since the priority values for maskable interrupts are 0 to 6, the
DI instruction is used to disable maskable interrupts to be
accepted. The EI instruction becomes effective immediately
after execution. (With the TLCS-90, the EI instruction becomes
effective after execution of the subsequent instruction.)
In addition to the general-purpose interrupt processing
mode described above, there is also a high-speed µDMA processing mode. High-speed µDMA is a mode used by the CPU
to automatically transfer byte or word data. It enables the CPU
to process interrupts such as data saves to built-in I/Os at high
speed.
Figure 3.3 (1) is a flowchart showing overall interrupt
processing.
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TMP96C031N/F
Figure 3.3 (1). Interrupt Processing Flowchart
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3.3.1 General-Purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows:
(1) The CPU reads the interrupt vector from the interrupt
controller. When more than one interrupt with the same
level is generated simultaneously, the interrupt controller
generates interrupt vectors in accordance with the
default priority (which is fixed as follows: the smaller the
vector value, the higher the priority), then clears the interrupt request.
(2) The CPU pushes the program counter and the status
register to the system stack area (area indicated by the
system mode stack pointer).
(3) The CPU sets a value in the CPU interrupt mask register
<IFF2 to 0> that is higher by 1 than the value of the
accepted interrupt level. However, if the value is 7, 7 is
set without an increment.
(4) The CPU sets the <SYSM> flag of the status register to 1
and enters the system mode.
(5) The CPU jumps to address 8000H + interrupt vector,
then starts the interrupt processing routine.
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The table below shows the number of execution states
for the above processing times.
Bus Width of Stack Area
Interrupt Processing State Number
MAX mode
Min mode
8-bit
23
19
16-bit
17
15
To return to the main routine after completion of the interrupt processing, the RETI instruction is usually used. Executing
this instruction restores the contents of the program counter
and the status registers.
Though acceptance of non-maskable interrupts cannot
be disabled by program, acceptance of maskable interrupts
can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority
higher than the value in the CPU mask register <IFF2 to 0>.
The CPU mask register <IFF2 to 0> is set to a value higher by
1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is
generated, the CPU accepts the interrupt with the higher level,
causing interrupt processing to nest. The CPU does not
accept an interrupt request of the same level as that of the
interrupt being processed.
Resetting initializes the CPU mask registers <IFF2 to 0>
to 7; therefore, maskable interrupts are disabled.
The addresses 008000H to 0081FFH (512 bytes) of the
TLCS-900 are assigned for interrupt processing entry area.
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Table 3.3 (1) TMP96C031F Interrupt Table
Default Priority
Type
Interrupt Source
Start Address
High-Speed
Micro DMA
Start to Vector
1
Reset
, or SWI0 instruction
0 0 0 0 H
8 0 0 0 H
–
2
INTPREV:
Privileged violation, or SWI1
0 0 1 0 H
8 0 1 0 H
–
3
INTUNDEF:
Illegal instruction, or SWI2
0 0 2 0 H
8 0 2 0 H
–
4
SWI 3 Instruction
0 0 3 0 H
8 0 3 0 H
–
SWI 4 Instruction
0 0 4 0 H
8 0 4 0 H
–
5
6
NonMaskable
SWI 5 Instruction
0 0 5 0 H
8 0 5 0 H
–
7
SWI 6 Instruction
0 0 6 0 H
8 0 6 0 H
–
8
SWI 7 Instruction
0 0 7 0 H
8 0 7 0 H
–
0 0 8 0 H
8 0 8 0 H
08H
0 0 9 0 H
8 0 9 0 H
09H
9
NMI Pin
10
INTWD:
11
INTO pin
0 0 A 0 H
8 0 A 0 H
0AH
12
INT4 pin
0 0 B 0 H
8 0 B 0 H
0BH
13
INT5 pin
0 0 C 0 H
8 0 C 0 H
0CH
14
INT6 pin
0 0 D 0 H
8 0 D 0 H
0DH
15
INT7 pin
0 0 E 0 H
8 0 E 0 H
0EH
-
(Reserved)
0 0 F 0 H
8 0 F 0 H
0FH
16
INTT0:
8-bit timer 0
0 1 0 0 H
8 1 0 0 H
10H
17
INTT1:
8-bit timer 1
0 1 1 0 H
8 1 1 0 H
11H
18
INTT2:
8-bit timer 2/PWM0
0 1 2 0 H
8 1 2 0 H
12H
19
INTT3:
8-bit timer 3/PWM1
0 1 3 0 H
8 1 3 0 H
13H
20
INTTR4:
16-bit timer 4 (TREG4)
0 1 4 0 H
8 1 4 0 H
14H
INTTR5:
16-bit timer 4 (TREG5)
21
Maskable
Watchdog timer
0 1 5 0 H
8 1 5 0 H
15H
22
(Reserved)
0 1 6 0 H
8 1 6 0 H
16H
23
(Reserved)
0 1 7 0 H
8 1 7 0 H
17H
24
INTRX0:
Serial receive (Channel.0)
0 1 8 0 H
8 1 8 0 H
18H
25
INTTX0:
Serial send (Channel.0)
0 1 9 0 H
8 1 9 0 H
19H
26
INTRX1:
Serial receive (Channel.1)
0 1 A 0 H
8 1 A 0 H
1AH
27
INTTX1:
Serial send (Channel.1)
0 1 B 0 H
8 1 B 0 H
1BH
28
INTAD:
A/D conversion completion
0 1 C 0 H
8 1 C 0 H
1CH
29
INT1 pin
0 1 D 0 H
8 1 D 0 H
1DH
30
INT2 pin
0 1 E 0 H
8 1 E 0 H
1EH
31
INT3 pin
0 1 F 0 H
8 1 F 0 H
1FH
3.3.2 High-Speed µDMA
In addition to the conventional interrupt processing, the TLCS900 also has a high-speed µDMA function. When an interrupt
is accepted, in addition to an interrupt vector, the CPU receives
data indicating whether processing is high-speed µDMA mode
or general-purpose interrupt. If high-speed µDMA mode is
requested, the CPU performs high-speed µDMA processing.
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Vector Value
“V”
The TLCS-900 can process at very high speed compared with the TLCS-90 µDMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated
registers are assigned as CPU control registers, they can only
be accessed by the LDC (privileged) instruction.
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(1) High-Speed µDMA Operation
High-speed µDMA operation starts when the accepted interrupt vector value matches the µDMA start vector value set in
the interrupt controller. The high-speed µDMA has four channels so that it can be set for up to four types of interrupt
source.
When a high-speed µDMA interrupt is accepted, data is
automatically transferred from the transfer source address to
the transfer destination address set in the control register, and
the transfer counter is decremented. If the value in the counter
after decrementing is other than 0, high-speed µDMA processing is completed. If the value in the counter after decrementing
is 0, general-purpose interrupt processing is performed. In
read-only mode, which is provided for DRAM refresh, the value
in the counter is ignored and dummy read is repeated.
The 32-bit control registers are used for setting transfer
source/destination addresses. However, the TLCS-900 has
only 24 address pins for output. A 16M-byte space is available
for the high-speed µDMA. Also in normal mode operation, the
all address space (in other words, the space for system mode
which is set by the CS/WAIT controller) can be accessed by
high-speed µDMA processing.
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There are two data transfer modes: one-byte mode and
one-word mode. Incrementing, decrementing, and fixing the
transfer source/destination address after transfer can be done
in both modes. Therefore data can easily be transferred
between I/O and memory and between I/Os. For details of
transfer modes, see the description of transfer mode registers.
The transfer counter has 16-bit, so up to 65536 transfers
(the maximum when the initial value of the transfer counter is
0000H) can be performed for one interrupt source by highspeed µDMA processing.
After transferring data using the high-speed µDMA and
the transfer counter has been decremented to 0, the program
goes to a general-purpose interrupt processing. Note that after
interrupt processing, when an interrupt for the same channel is
generated, if the system requires resetting the transfer counter
starts from 65536.
The following section illustrates the high-speed µDMA
cycle when the transfer destination address is in INC mode.
(MIN mode, 16-bit bus for all address areas, 0 wait).
Interrupt sources processed by high-speed µDMA processing are those with the high-speed µDMA start vectors
listed in Table 3.3 (1).
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(2) Register Configuration (CPU Control Register)
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(3) Transfer Mode Register Details
Execution time: When 16-bit bus width and 0 wait are set for the transfer destination/source address.
Note:
n: corresponds to high-speed µDMA channels 0 - 3.
DMADn +/DMASn + : Post-increment (Increments register value after transfer.)
DMADn -/DMASn - :
Post-decrement (Decrement register value after transfer.)
All address space (the space for system mode) can be
accessed by high-speed µDMA. Do not use undefined codes
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for transfer mode control.
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TMP96C031N/F
3.3.3 Interrupt Controller
Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The
left half of the diagram shows the interrupt controller; the right
half includes the CPU interrupt request signal circuit and the
HALT release signal circuit.
Each interrupt channel (total of 20 channels) in the interrupt controller has an interrupt request flip-flop, interrupt priority setting register, and a register for storing the high-speed
micro DMA start vector. The interrupt request flip-flop is used
to latch interrupt requests from peripheral devices. The flip-flop
is cleared to 0 at reset, when the CPU reads the interrupt
channel vector after the acceptance of interrupt, or when the
CPU executes an instruction that clears the interrupt of that
channel (writes 0 in the clear bit of the interrupt priority setting
register).
For example, to clear the INT0 interrupt request, set the
register after the DI instruction as follows.
INTE0AD←---- 0 ---
Zero-clears the INT0 Flip Flop.
The status of the interrupt request flip-flop is detected by
reading the clear bit. Detects whether there is an interrupt
request for an interrupt channel.
The interrupt priority can be set by writing the priority in
the interrupt priority setting register (e.g., INTE0AD, INTE45,
etc.) provided for each interrupt source. Interrupt levels to be
set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-
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ables the corresponding interrupt request. The priority of the
non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed
to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance
with the default priority (the smaller the vector value, the higher
the priority).
The interrupt controller sends the interrupt request with
the highest priority among the simultaneous interrupts and its
vector address to the CPU. The CPU compares the priority
value <IFF2 to 0> set in the Status Register by the interrupt
request signal with the priority value sent; if the latter is higher,
the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR <IFF2 to 0>. Interrupt requests where the priority value equals or is higher than
the set value are accepted simultaneously during the previous
interrupt routine. When interrupt processing is completed (after
execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to
the CPU SR <IFF2 to 0>.
The interrupt controller also has four registers used to
store the high-speed other µDMA start vector. These are I/O
registers; unlike other DMA registers (DMAS, DMAD, DMAM,
and DMAC), they can be accessed in either normal or system
mode. Writing the start vector of the interrupt source for the
µDMA processing (see Table 3.3 (1)), enables the corresponding interrupt to be processed by µDMA processing. The values
must be set in the µDMA parameter registers (e.g., DMAS and
DMAD) prior to the µDMA processing.
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Figure 3.3.3 (1). Block Diagram of Interrupt Controller
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TMP96C031N/F
(1) Interrupt Priority Setting Register
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TMP96C031N/F
(2) External Interrupt Control
Setting of External Interrupt Pin Functions
Interrupt
Pin Name
NMI
P34
INT0
P50
INT1
P51
INT2
P52
INT3
P53
Mode
Setting Method
Falling edge
IIMC <NMIREE> = 0
Rising and falling edge
IIMC <NMIREE> = 1
Rising edge
IIMC <I0LE> = 0, <I0IE> = 1
Level
IIMC <I0LE> = 1, <I0IE> = 1
Rising edge
IIMC <I1EM> = 0
Falling edge
IIMC <I1EM> = 1
Rising edge
IIMC <I2EM> = 1
Rising edge
IIMC <I3EM> = 1
Rising edge
T4MOD <CAP12M1, 0> = 0, 0 or 0, 1 or 1, 1
Falling edge
T4MOD <CAP12M1, 0> = 1, 0
INT4
P72
INT5
P73
Rising edge
INT6
P66
Rising edge
IIMC <I6IIE> = 1
INT7
P35
Rising edge
IIMC <I7IIE> = 1
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–
19
TMP96C031N/F
(3) High-Speed µDMA Start Vector
When the CPU reads the interrupt vector after accepting an
interrupt, it simultaneously compares the interrupt vector with
each channel’s µDMA start vector (bits 4 to 8 of the interrupt
vector). When both match, the interrupt is processed in µDMA
(4) Notes
The instruction execution unit and the bus interface unit of this
CPU operate independently of each other. Therefore, if the instruction used to clear an interrupt request flag of an interrupt is fetched
before the interrupt is generated, it is possible that the CPU might
execute the fetched instruction to clear the interrupt request flag
20
mode for the channel whose value matched.
If the interrupt vector matches more than one channel,
the channel with the lower channel number has a higher priority.
while reading the interrupt vector after accepting the interrupt. If so, the CPU would read the default vector 00A0H
and start the interrupt processing from the address
80A0H.
To avoid this, make sure that the instruction used to
clear the interrupt request flag comes after the DI instruction.
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TMP96C031N/F
3.4 Standby Function
When the HALT instruction is executed, the TMP96C031
enters RUN, IDLE, or STOP mode depending on the contents
of the HALT mode setting register.
(1) RUN:
(2) IDLE:
Only the CPU halts; power consumption remains
unchanged.
Only the built-in oscillator operates, while all other
built-in circuits halt. Power consumption is
Bit Symbol
WDMOD
(005CH) Read/Write
reduced to 1/10 or less than that during normal
operation.
(3) STOP:
All internal circuits including the built-in oscillator
halt. This greatly reduces power consumption.
The states of the port pins in STOP mode can be set as
listed in Table 3.4 (1) using the I/O register WDMOD <DRVE>
bit.
7
6
5
4
3
2
1
0
WDTE
WDTP1
WDTP0
WARM
HALTM1
HALTM0
RESCR
DRVE
0
0
0
0
Warming up
time
0 : 216 /fc
1 : 218 /fc
Standby mode
00 : RUN
01 : STOP
10 : IDLE
11 : Don’t care
R/W
After reset
1
0
1 : WDT
Enable
Function
0
00 : 216 / fc
01 : 2 18 / fc
10 : 220/ fc
11 : 222/ fc
Detection time
When STOP mode is released by other than a reset, the
system clock output starts after allowing some time for warming up set by the warming-up counter fro stabilizing the built-in
oscillator. To release STOP mode by reset, it is necessary to
1: Connects
watchdog
mode
timer
mode
output to
mode
RESET pin
internally.
0
1: Drive pin
even in
STOP
mode.
allow the oscillator to stabilize.
To release standby mode, a reset or an interrupt is used.
To release IDLE or STOP mode, only an interrupt by the NMI or
INT0 pin, or a reset can be used. The details are described
below:
Standby Release by Interrupt
Interrupt Level
Standby Mode
RUN
Interrupt Mask (IFF2 to 0)
≤ Interrupt Request Level
Can be released by any interrupt.
After standby mode is released, interrupt processing starts.
Interrupt Mask (IFF2 to 0)
> Interrupt Request Level
Can only be released by INT0 pin.
Processing resumes from address next to HALT instruction.
IDLE
Can only be released by NMI or INT0 pin. After standby mode
is released, interrupt processing starts.
↑
STOP
↑
↑
Note 1: When releasing standby setting INT0 to high level input mode, keep it high until interrupt processing starts. If the level drops to low, interrupt processing cannot be started correctly.
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21
TMP96C031N/F
Table 3.4 (1) Pin States in STOP Mode
Pin Name
I/O
DRVE = 0
DRVE = 1
AD0 ~ AD7
AD0 ~ 7
–
–
AD8 ~ AD15
AD8 ~ 15
A8 ~ 15
–
–
–
P20 ~ P27
Input mode
Output mode/A16 ~ 23
PD*
PD*
PD
Output
P30 ~ P33
Input mode
Output mode
PD*
PD*
PD
Output
Input mode
Output mode
PU*
PU*
PU
Output
NMI
Input
Input
P35 (RAS/INT7)
Input mode
Output mode
RAS
PU*
PU*
Output
PU
Output
Output
P40 ~ P42 (CS0 ~ CS2)
Output
PU*
Output
P43 (CS3/CAS)
Output
CAS
PU*
Output
Output
Output
P50 (AN0/INT0)
Input
INT0
–
Input
Input
Input
P51 ~ P53
Input
–
Input
P60 ~ P66
Input mode
Output mode
–
–
Input
Output
P67 (P13/WDTOUT)
Input mode
Output mode
WDTOUT
–
–
Output
Input
Output
Output
P70 ~ P76
Input mode
Output mode
–
–
Input
Output
ALE
Output
“0”
“0”
CLK
Output
–
“1”
RESET
Input
Input
Input
P34 (R/W/NMI)
WR
Output
–
“1” Output
RD
Output
–
“1” Output
AM8/16
Input
Input
Input
X1
Input
–
–
X2
Output
“1”
“1”
–:
Input:
Input:
Output:
PU:
PD:
*:
Input for input mode/input pin is invalid; output mode/output pin is at high impedance.
Input enable state
Input gate in operation. Fix input voltage to 0 or 1 so that input pin stays constant.
Output state
Programmable pull-up pin. Fix the pin to avoid through current since the input gate operates when a pull-up resistor is not set.
Programmable pull-down pin. Fix the pin like a pull-up pin when a pull-down resistor is not set.
Input gate disable state. No through current even if the pin is set to high impedance.
Note:
Port registers are used for controlling programmable pull-up/pull-down. If a pin is also used for an output function (e.g., TO1) and the output function
is specified, whether pull-up or pull-down is selected depends on the output function data. If a pin is also used for an input function, whether pull-up or
pull-down is selected depends on the port register setting value only.
22
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TMP96C031N/F
3.5 Port Functions
The input/output ports of the TMP96C031F consist of a total
of 37 bits.
In addition to general purpose input/output port func-
tions, these port pins also function as input/outputs for internal
CPU and built-in I/O. Table 3.5 (1) shows the function of each
port pin.
(R:
Table 3.5 (1) Port Function
Port Name
Pin Name
Number of
Pins
Direction
R
↑ = With programmable pull-up resistor
↓ = WIth programmable pull-down resistor)
Direction Setting Unit
Pin Name for Built-in Function
Port2
P20 to P27
8
Input/Output
↓
Bit
A0 to A7/ A16 to A23
Port3
P30
P31
P32
P33
P34
P35
1
1
1
1
1
1
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
↑
↑
↑
↑
↑
↑
Bit
Bit
Bit
Bit
Bit
Bit
TO5/HWR
TI0/WAIT
BUSRQ
BUSAK
R/W/RAS
RAS/INT7
Port4
P40
P41
P42
P43
1
1
1
1
Output
Output
Output
Output
↑
↑
↑
↑
(Fixed)
(Fixed)
(Fixed)
(Fixed)
CS0
CS1
CS2
CS3/CAS
Port5
P50 to P53
4
Input
–
(Fixed)
AN0 ~ AN3
Port6
P60
P61
P62
P63
P64
P65
P66
P67
1
1
1
1
1
1
1
1
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
–
–
–
–
–
–
–
–
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
PG00/TxD0
PG01/RxD0
PG02/CTS0
PG03/RSFH
PG10
PG11
PG12/INT6
PG13/WDTOUT
Port7
P70
P71
P72
P73
P74
P75
P76
1
1
1
1
1
1
1
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
–
–
–
–
–
–
–
Bit
Bit
Bit
Bit
Bit
Bit
Bit
TO1/TO4
TO2/DMUX
INT4/TI4
INT5/TI5
TxD1
RxD1
SCLK1
3.5.1 Programmable Pull-up/Pull-down
PORT2 has a built-in pull-down resistor and PORT3 and
PORT4 have a built-in pull-up resistor. Normally, their load can
be turned on or off from software by setting the value of the
output latch (registers P2, P3, and P4) during input mode.
They can also be set in stand-by (STOP) mode and the load
can be turned on or off when the immediately preceding setting is the value of output latch in input mode or is the value of
output data in output mode.
Table 3.5 (2) Pull-up/down Function Setting
Programmable
Pull-up/down
PORT2 (I/O)
Pull-down
PORT3 (I/O)
Pull-up
PORT4 (Output)
Pull-up
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Setting
Output latch
Output data
ON/OFF
0
ON
1
OFF
0
ON
1
OFF
0
ON
1
OFF
Normal
Setting enabled only in
input mode
↑
Setting disabled
Standby (STOP) mode
Setting enabled in input/
output mode
↑
Setting enabled only in
output mode
23
TMP96C031N/F
3.5.2 Bus Release Function
The pull-up/down function explained in section 3.5.1 is also
used to stabilize bus control signal at bus release.
Table 3.5 (2) shows pin states at bus release (BUSAK = 0).
Pin state at bus release
Pin Name
Port mode
AD0 - AD15
AD0 - AD7
(A8 ~ A15)
P20 - P27
(A16 ~ 23)
–
No status change.
(Does not become high impedance.)
RD
WR
–
Function mode
Becomes high impedance.
First sets all bits to low, then sets output buffer to off.
Internal pull-down is added regardless to output latch
value.
First sets all bits to high, then sets them to high impedance.
P30 (HWR)
P34 (R/W)
No status change.
(Does not become high impedance.)
First sets all bits to high, then sets output buffer to off.
Internal pull-down is added regardless to output latch
value.
P40 (CS0)
P41 (CS1)
P42 (CS2)
P43 (CS3)
No status change.
(Does not become high impedance.)
First sets all bits to high, then sets output buffer to off.
Internal pull-down is added regardless to output latch
value.
P71 (DMUX)
P63 (RFSH)
No status change.
(Does not become high impedance.)
First sets all bits to high, then sets them to high impedance.
P35 (RAS)
P43 (CAS)
No status change.
(Does not become high impedance.)
No status change.
(Does not become high impedance.)
Figure 3.5 (2) shows the external bus interface when the
bus release function is in use. The internal I/O of this device
cannot be accessed when the bus is released.
Figure 3.5 (1). External bus interface example when bus release function is in use
24
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TMP96C031N/F
3.5.3 Port 2 (P20 - P27)
Port 2 is an 8-bit general-purpose I/O port. I/O can be set on
bit basis using the control register P2CR and function register
P2FC. Resetting resets all bits of output latch P2, control register P2CR and function register P2FC to 0. It also sets Port 2 to
input mode and connects a pull-down resistor.
In addition to functioning as a general-purpose I/O port,
Port 2 also functions as an address bus (A16 to 23).
Figure 3.5 (2). Port 2
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25
TMP96C031N/F
Figure 3.5 (3). Registers for Port 2
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TMP96C031N/F
3.5.4 Port 3 (P30 - P35)
Port 3 is a 6-bit general-purpose I/O port. I/O can be set bit by
bit using control registers P3CRL and P3CRH. Resetting sets
all bits of P3 to 0; P30 to P35 to input mode and connects a
pull-up resistor. In addition to functioning as a general-purpose I/O port, port 3 is also used for CPU control/status signal
interrupt input, and timer I/O.
Figure 3.5 (4). Port 3 (P30)
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27
TMP96C031N/F
Figure 3.5 (5). Port 3 (P31, P32)
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TMP96C031N/F
Figure 3.5 (6). Port 3 (P33, P35)
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29
TMP96C031N/F
(1) P34/NMI/R/W
Port 34 is a general-purpose I/O port, shared with nonmaskable interrupt input pin (NMI). The NMI pin is selected by
the control register P3CRH <P34C1,P34C0>. By setting
<P34C1,P34C0> = <0,0>, it turns to the NMI input pin. Since
the NMI pin is specified only once, the NMI pin cannot be
switched to the general-purpose port. The <P34C1,P34C0>
should be initialized to “0” by resetting in order to switch to the
general-purpose I/O port mode. Port3 register (P34) is set to
be “1” when the pull-up resistor is attached.
Figure 3.5 (6). Port 3 (P33, P34)
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TMP96C031N/F
Figure 3.5 (8). Port 3 Registers
Note:
There is no port/function switch register for pin P31 (TIO/WAIT). For example, if pin P31 is used as an input port, data are input to 8-bit timer 0. If pin
P31 is used as the WAIT pin, set P3CRL <P31C1,0) > to 00, and bits 3 and 2 <BXW1,0> in the chip select/wait control register to 10.
If pin P35 (RAS/INT7) is used as the INT7 pin, set P3CRH <P35C1,0) to 00 and <171E> to 1.
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TMP96C031N/F
3.5.5 Port 4 (P40 - P43)
Port 4 is a 4-bit output dedicated port. Port 4 is also used for
chip select CS0 - CS3 outputs and column address strobe
CAS (CS3 only) output. To select the function to be used, use
function register P4FC. Resetting sets the output register for
P40, P41, and P42 to 1; the output register for P42 to 0; all bits
in the function register to 0. P40, P41, and P43 are set to output ports for outputting 1; P42 to output port for outputting 0.
Figure 3.5 (9). Port 4 (P40, P41, P43)
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TMP96C031N/F
Figure 3.5 (10). Port 4 (P42)
Figure 3.5 (11). Registers for Port 4
P4FC is disabled for read-modify-write.
Note: To select the function to be used for P43, use the B3CS register for the chip select/wait controller.
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TMP96C031N/F
3.5.6 Port 5 (P50 - P53)
Port 5 is a 4-bit input dedicated port which is also used for
analog inputs or external interrupts.
Figure 3.5 (11). Port 5 (P50, P51, P52, P53)
Port 5 Register
Figure 3.5 (12). Register for Port 5
34
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TMP96C031N/F
3.5.7 Port 6 (P60 - P67)
Port 6 is an 8-bit port. I/O can be set bit by bit. In addition to
functioning as an I/O port, pins P60 to P67 function as follows:
P60 - P63/P64 - P67: pattern generate PG0/PG1 output
P60: serial channel TxD0 output pin and programmable
open drain function.
P61: serial channel RxD0 output pin
P62: serial channel CTS0 output pin
P63:
P66:
P67:
DRAM controller refresh signal pin
external interrupt request input INT6 pin
watchdog timer WDT output pin. Set using port 6 control registers. P6CRL and P6CRH.
Resetting sets control registers P6CRL and P6CRH to 0; all
bits to input mode.
Figure 3.5 (13) Port 6 (P60, P67)
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TMP96C031N/F
Figure 3.5 (14). Registers for Port 6 (P61, P62, P66)
Figure 3.5 (15). Port 6 (P63, P64, P65)
36
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TMP96C031N/F
Figure 3.5 (16). Registers for Port 6
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37
TMP96C031N/F
3.5.8 Port 7 (P70 - P76)
Port 7 is a 7-bit general-purpose I/O port. I/O can be set bit by
bit using control registers P7CRL and P7CRH. Resetting sets
all bits in P7 to 1; control registers P7CRL and P7CRH to 0;
P70 - P76 to input mode. In addition to functioning as a general-purpose I/O port, port 7 as follows: interrupt input, timer
I/O, DRAM address multiplex, serial channel send/receive
(TXD1 and RXD1), and transfer clock input (SCLK1) pin.
Figure 3.5 (17). Port 7 (P70, P71)
38
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TMP96C031N/F
Figure 3.5 (18). Port 7 (P72, P73, P75)
Figure 3.5 (19). Port 7 (P74)
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39
TMP96C031N/F
Figure 3.5 (20). Port 7 (P76)
40
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TMP96C031N/F
Figure 3.5 (21). Registers for Port 7
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41
TMP96C031N/F
3.6 Chip Select/Wait Control
The TMP96C031F has a built-in chip select/wait controller
used to control chip select (CS0 - CS3 pins), wait (WAIT pin),
and data bus size (8 or 16 bits) for any of the three block
address areas.
The select pin (AM8/16) is used to select the width of the
external data bus. (See section 3.1.2, External data width
select pin.)
3.6.1 Control Registers
Table 3.6 (1) shows control registers
The block address areas is controlled by corresponding
CS/wait control register (B0CS, B1CS, B2CS, B3CS) and start
address register/address mask register (explained in section
3.6.2, Address area).
Registers can be written to only when the CPU is in system mode. (There are two CPU modes: system and normal.)
The reason is that the settings of these registers have an
important effect on the system.
Table 3.6 (1) Chip Select/Wait Control Register
42
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TMP96C031N/F
(1)
Enable
(3)
Control register bit 7 (B0E, B1E, B2E, and B3E) is a
master bit used to specify enable “1”)/disable “0” of
the setting.
Resetting sets B0E, B1E, and B3E to disable “0” and
B2E to enable “1”.
(2)
Control register bit 5 (B0ARE, B1ARE, B2ARE, and
B3ARE) is used to specify the target address space.
When this bit is set to “0” after reset, CS0 is set to
addresses 7F00H to 7FFFF, CS1 is set to address 80H
to 7FFFH, and CS2 is set to addresses 8000H to
3FFFFF. CS3 is undefined. (See 3.6.3 Default Address
Space Specification.) When this bit is set to “1”, the
target address is the address space is the address
space specified by the memory start address register
MSAR and memory start address mask register
MAMR. (See 3.6.2 Address Space Specification.)
System only specification
Control register bit 6 (B0SYS, B1SYS, B2SYS, and
B3SYS) is used to specify enable/disable of the setting
depending on the CPU operating mode (system or normal). Setting this bit to 0 enables setting (Address
space for CS, Wait state, Bus size, etc.) regardless of
the CPU operating mode; setting it to 1 enables setting
in system mode but disables setting in normal mode.
Resetting clears bit 6 to 0.
Bit 6 is mainly used when external memory data
should not be accessed in normal mode (i.e., for system mode only memory data for the operating system).
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Address area specification
(4)
Data bus width select
Control register bit 4 (B0BUS, B1BUS, B2BUS,
B3BUS) is used to specify the data bus width. When
this bit is set to “0”, memory is accessed in 16-bit data
bus mode. When this bit is set to “1”, memory is
accessed in 16-bit data bus mode. However, this bit is
valid only in 16-bit bus mode (AM8/16 pin = “0”). In 8bit bus mode (AM8/16 pin = “1”), all address space is
accessed in 8-bit data bus mode regardless of the
value of this bit. (See 3.1.2 External Data Bus Width
Selection Pin.)
The changing data bus width according to the address
to be address to be accessed is referred to dynamic
bus sizing. Table 3.6 (2) shows the details of the bus
operation.
43
TMP96C031N/F
Table 3.6 (2) Dynamic Bus Sizing
Operand
Start Address
Memory
Data Size
CPU Address
2n + 0
(even number)
8-bit
8-bit
2n + 1
(odd number)
2n + 0
(even number)
16-bit
2n + 1
(odd number)
2n + 0
(even number)
D15 - D8
D7 - D0
2n + 0
xxxxx
b7 - b0
16-bit
2n + 0
xxxxx
b7 - b0
8-bit
2n + 1
xxxxx
b7 - b0
16-bit
2n + 1
b7 - b0
xxxxx
8-bit
2n + 0
2n + 1
xxxxx
xxxxx
b7 - b0
b15 - b8
16-bit
2n + 0
b15 - b8
b7 - b0
8-bit
2n + 1
2n + 2
xxxxx
xxxxx
b7 - b0
b15 - b8
16-bit
2n + 1
2n + 2
b7 - b0
xxxxx
xxxxx
b15 - b8
2n + 0
2n + 1
2n + 2
2n + 3
xxxxx
xxxxx
xxxxx
xxxxx
b7 - b0
b15 - b8
b23 - b16
b31 - b24
2n + 0
2n + 2
b15 - b8
b31 - b24
b7 - b0
b23 - b16
2n + 1
2n + 2
2n + 3
2n + 4
xxxxx
xxxxx
xxxxx
xxxxx
b7 - b0
b15 - b8
b23 - b16
b31 - b24
2n + 1
2n + 2
2n + 4
b7 - b0
b23 - b16
xxxxx
xxxxx
b15 - b8
b31 - b24
8-bit
16-bit
32-bit
2n + 1
(odd number)
8-bit
16-bit
xxxxx:
44
CPU Data
Operand
Data Size
During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active.
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TMP96C031N/F
(5)
Wait control
Control register bits 3 and 2 (B0W1, 0; B1W1, 0; B2W1,
0; B3W1, 0) are used to specify the number of waits.
Setting these bits to 00 inserts a 2-state wait regardless of the WAIT pin status. Setting them to 01 inserts
a 1-state wait regardless of the WAIT status. Setting
them to 10 inserts a 1-state wait and samples the
WAIT pin status. If the pin is low, inserting the wait
maintains the bus cycle until the pin goes high. Setting
them to 11 completes the bus cycle without a wait
regardless of the WAIT pin status.
Resetting sets these bits to 00 (2-state wait mode).
Note: If there ia a contention between DRAM access
and refresh when using DRAM, the refresh
cycle is added to the specified wait.
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(6)
CS/CAS waveform select
The B3CS register bit 1 <B3CAS> is used to specify
the mode of the waveform output from the chip select
pin (CS3/CAS) pin. When this bit is set to “0”, CS3
waveform is output. When it is set to “1”, CAS waveform is output. This bit is cleared to zero after reset.
(7)
Self refresh control
(described in section 3.13.1 Refresh Controller.)
(8)
Wait control outside space CS0 to CS3
This bit is used to specify the number of waits when
B0CS register bits 1 and 0 <BEXW1, 0> or space outside CS0 to CS3 is accessed.
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TMP96C031N/F
3.6.2 Address Space Specification (B0CS to B3CS
< B0ARE to B3ARE> = “1”)
The address space is specified with the start address register
(MSAR0, MSAR1, MSAR2, and MSAR3) and address mask
register (MAMR0, MAMR1, MAMR2, and MAMR3). For each
bus cycle, the chip select controller compares the address on
the bus and value of this start address register. The value of
the address mask register is used to ignore result of this
address comparison. When there is a match, the specified
space is assumed to be accessed and a low strobe signal is
output from the corresponding chip select pin (CS0 to CS3) if
it is enabled (B0E to B3E = “1”).
Figure 3.6 (1). Chip Select (CS0 to CS3) Operation Timing
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TMP96C031N/F
Figure 3.6 (2). CS0 Address Decode Block Diagram
Figure 3.6 (3). CS1 Address Decode Block Diagram
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TMP96C031N/F
Figure 3.6 (4). CS2, CS3 Address Decode Block Diagram
(1) Memory start address register
Memory start address register
Table 3.6 (3) Memory Start Address Register
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TMP96C031N/F
Table 3.6 (4) Memory Start Address Mask Registers
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TMP96C031N/F
MSAR0 to 3 < S23> to <S16> correspond to addresses
A23 to A16 and S15, S14 to 9, and S8 corresponding to
addresses A15, A14, to 9, and A8 are “0” by default. MAMR0
<V20> to <V8> enable/disable comparison of value set with
MSAR0 and address and <V20> to <V8> correspond to
<S20> to <S16>, S15, S14 to 9, and S8. In addition, V21,
V22, and V23 corresponding to <S21>, <S22>, and <S23>
are “0” by default and comparison is always enabled.
Example of enabling/disabling comparison
(CS0 registers MSAR0 and MSAMR0)
When comparison is disabled by setting <V16> = 1, the
comparison of the value of <S16> and address A16 is disabled and the value of <S16> becomes invalid.
When comparison is enabled by setting <V16> = 0, the
comparison of the value of <S16> and address A16 is
enabled and CS0 is enabled only when they match.
CS1, CS2, and CS3 can be used in the same manner.
(2) How to the Start Address
The address decoder is output by specifying the start address
for CS output and the space size.
The start address is set every 64K-byte because it is
decoded by A16 to A23 as shown in the block diagram.
In other words, the DRAM start address is set to one of
the 64K-byte intervals after “000000H”.
However, note that the start address may be changed
due to the value of the MAMR.
Figure 3.6 (5). Where to Set Start Address
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TMP96C031N/F
(3) How to Set the Address Space
The address space is specified by setting the memory start
address mask register (MAMR0 to 3).
As shown in the address decoder block diagram (Figures
3.6 (2) to (4)), CS0, CS1, or CS2/CS3 can specify the address
area for which the chip select signal can be output depending
on whether to compare the address A8 to A20, A8 to A21, or
A15 to A22 respectively.
Figure 3.6 (6). Chip Select and Space Size
(4) Start Address/Address Space Setting Procedure
➀ Set memory start address mask register (MAMR)
(Set address space)
➁ Set memory start address register (MSAR)
(Set area start address)
➂ Check the identical address bit of MAMR and MSAR
Example: Check the value of (CS0) MAMR0 <V16>
and MSAR0 <S16>
➃ If the bits at identical address are “1” and “1”, MSAR bit
is treated as “0”. <-The start address changes.
Example: If (CS0) MAMR <V16> = 1 and MSAR
<S16> = 1, comparison of address A16
and <S16> is disabled and address A16 is
selected regardless of whether the value is
“1” or “0” and the start address is replaced
by the value in MSAR.
➄ If it is OK for the start address to change, end the setting procedure. If not, change the value to MSAR.
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➅ Reset MSAR and re-verify (return to step 3).
(Setting Example)
When address space is 128K-byte and start address is
30000H (area 30000H to4FFFFH).
Set
MAMR = 0FH address space 128K-byte
MSAR = 03H start address 30000H
MAMR <V16> and MSAR <S16> are “1” and “1” and the
start address changes to 2000H. (space 20000H to
3FFFFH).
If this is not desired, change the start address.
Change the start address to 4000H. (space 40000H to
5FFFFH).
MAMR = 0FH
MSAR = 04H
The bits at identical address of MAMR and MSAR are not
“1” and “1” and the start address remains unchanged.
Therefore, a 128K-byte space starting at address
40000H can be decoded.
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TMP96C031N/F
(Setting example 1) (CS0)
chip select output is as shown in the following memory map.
When MSAR is set to 02H and MAMR is set to 0FH, the
S23 to S17 are valid because V23 to V17 = “0” and S16
52
are invalid because V16 to V8 = “1”.
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TMP96C031N/F
(Setting example 2) (CS0)
chip select output is as shown in the following memory map.
When MSAR is set to 01H and MSAR is set to 04H, the
The values of S23 - S16, and S14-S8 become valid
because V23 to V16 = 0 and V14 - V8 = 0.The value of S15
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becomes invalid because V15 = 1.
53
TMP96C031N/F
(Setting example 3) (CS0)
Space where chip select is output by values set in MSAR and
MAMR (excerpt).
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TMP96C031N/F
3.6.3 Default Address Space Specification (B0CS to
B2CS < B0ARE to B2ARE> = “0”)
The following figures show the actual chip select image. CS0
can specify 7F00H to 7FFFH, CS1 can specify 80H to 7FFFH,
and CS2 can specify 8000H to 3FFFFFH. This is because
external connection of devices (such as RAM or I/O) other than
ROM is considered.
The area 7F00 to 7FFFH (256-byte space) for CS0 is
mapped in this space mainly due to external I/O expansion
consideration.
The area 80H to 7FFFH (approximately 32K-byte space)
for CS1 is mapped in this space mainly due to external RAM
expansion consideration.
The area 8000H to 3FFFFFH (approximately 4M-byte
space) for CS2 is mapped in this space mainly due to external
ROM expansion consideration.
CS1
CS0
7F00H
80H
8000H
8000H
CS2
8000H
3FFFFFH
FFFFFFH
FFFFFFH
(Mainly for I/O)
FFFFFFH
(Mainly for RAM)
(Mainly for ROM)
Supplement 1:
Supplement 2:
The access priority is in the order of built-in I/O and chip select/wait controller.
Wait for spaces other than CS0 to CS3 is set with B0CS register <BEXW1,0> and the data bus width is fixed to 16-bit if the AM8/16 pin is “0”
and to 8 bits if it is “1”.
Note:
When using the chip select/wait controller, do not assign multiple definitions to the same address area. (However, if CS0 is set to 7F000H to
7FFFH and CS1 is set to 80H to 7FFFH, only the CS0 setting/pin is active in the overlapped address space 7F00H to 7FFFH.)
When the bus is opened (BUSAK = “0”), CS0 to CS3 pins are also opened (output buffer OFF). Refer to the note on bus open in section “3.5
Port Functions” for the pin status at this point.
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TMP96C031N/F
3.6.4 Example of Usage
(1)
Connection example 1
Figure 3.6 (6) is an example (1) in which an external
memory is connected to the TMP96C031F. In this
example, a ROM is connected using 16-bit Bus; a
RAM is connected using 8-bit Bus.
Figure 3.6 (7). Example of External Memory Connection (ROM = 16-bit, RAM and I/O = 8-bit)
After a reset, the CS0 - CS3 pins are set to output port
mode; 1 is output from CS0, CS1, and CS3; 0 from CS2.
56
The program used to set these pins is as follows:
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TMP96C031N/F
(2)
P4FC
EQU
10H
B0CS
EQU
68H
B1CS
EQU
69H
B2CS
EQU
6AH
B3CS
EQU
6BH
MSAR3 EQU
46H
MAMR3 EQU
47H
; CS0 = 8-bit, 2WAIT, 7F00H ~ 7FFFH, 2WAIT other than in CS0 ~ CS3 areas
LD
(BOCS),
10010000B
LD
(B1CS),
100111XXB ; CS1 = 8-bit, 0WAIT, 80H ~ 7FFFH
LD
(B2CS),
100001XXB ; CS2 = 16-bit, 1WAIT, 8000H ~ 3FFFFFH
LD
(B3CS),
10111100B
; CS3 = 8-bit, 0WAIT, address area specification (400000H ~ 407FFFH)
LD
(MSAR3),
01000000B
; CS3 start address: 400000H
LD
(MAMR3),
00000000B
; CS3 area = 32K-byte
LD
(P4FC),
XXXX1111B ; CS0 ~ CS3 output mode
Note:
X: don’t care
Connection example 2
Figure 3.6 (7) is an example (2) in which an external
memory is connected to the TMP96C031. In this
example, the ROM, RAM, and I/O are connected with
8-bit width.
Figure 3.6 (8). Example of External Memory Connection (ROM = 16-bit, RAM and I/O = 8-bit)
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TMP96C031N/F
After a reset, the CS0 - CS3 pins are set to output port
mode; 1 is output from CS0, CS1, and CS3; 0 from CS2.
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P4FC
EQU
10H
B0CS
EQU
68H
B1CS
EQU
69H
B2CS
EQU
6AH
B3CS
EQU
6BH
MSAR3 EQU
46H
MAMR3 EQU
47H
LD
10010000B
(BOCS),
The program used to set these pins is as follows:
; CS0 = 8-bit, 2WAIT, 7F00H ~ 7FFFH, 2WAIT other than in CS0 ~ CS3 areas
LD
(B1CS),
100111XXB ; CS1 = 8-bit, 0WAIT, 80H ~ 7FFFH
LD
(B2CS),
100001XXB ; CS2 = 16-bit, 1WAIT, 8000H ~ 3FFFFFH
LD
(B3CS),
10111100B
; CS3 = 8-bit, 0WAIT, address area specification (400000H ~ 407FFFH)
LD
(MSAR3),
01000000B
; CS3 start address: 400000H
LD
(MAMR3),
00000000B
; CS3 area = 32K-byte
LD
(P4FC),
XXXX1111B ; CS0 ~ CS3 output mode
Note:
X: don’t care
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TMP96C031N/F
3.6.5 How to Start with an 8-Bit Data Bus
Resetting sets the CS2 pin low due to an internal pull-down
resistor; memory access starts in 16-bit data bus (2-wait)
mode. To start in 8-bit data bus mode, a special operation is
required. Operation is as described in the example below:
(with AM8/16 = “0”)
B2CS
EQU
6AH
; CS2 register address
ORG
8000H
; RESET address
LDX
(B2CS), 9CH
; CS2 8-bit, 0WAIT, 8000H ~
After reset, the program reads the LDX (B2CS), 9CH
instruction in 16-bit data bus mode. LDX is a 6-byte instruction: the 2nd, 4th and 6th bytes are handled as dummies (i.e.,
only codes in the 1st, 3rd and 5th bytes are actually used).
Even if starting in 8-bit data bus mode, it is possible to program so that the LDX instruction is executed and the block 2
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area (8000H - 3FFFFFH) is accessed in 8-bit data bus mode
without any problem.
The above program does not include setting the P42/
CS2 pin to output; add a program to set the P4CR and P4FC
registers as required.
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TMP96C031N/F
3.7 8-bit Timers
TMP96C031F contains four 8-bit timers (timers 0, 1 2, and 3),
each of which can be operated independently. The cascade
connection allows these timers to be used as two 16-bit timers. The following four operating modes are provided for the 8bit timers.
• 8-bit interval timer mode (4 timers) Either two 8-bit buses or
• 16-bit interval timer mode (2 timers) one 16-bit bus can be used.
• 8-bit programmable square wave pulse generation (PPG:
variable duty with variable cycle) output mode (2 timers)
• 8-bit pulse width modulation (PWM: variable duty with constant cycle) output mode (1 timer)
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Figure 3.7 (1) shows the block diagram of 8-bit timer
(timer 0 and timer 1).
Timers 2 and 3 have the same circuit configuration as
timers 0 and 1. However, timer 0 has an external clock, pin TI0,
whereas timer 2 does not.
Each interval timer consists of an 8-bit up counter, 8-bit
comparator, and 8-bit timer register. Timer flip-flop (TFE1) is
provided for timers 0 and 1; TFE3 timer 2 and 3.
Among the input clock sources for the interval timers, the
internal clocks of φ T1, φ T4, φT16, and φT256 are obtained
from the 9-bit prescaler shown in Figure 3.7 (2).
The operation modes and timer flip-flops of the 8-bit
timer are controlled by three control registers T01MOD,
T23MOD, TFFCR, TRUN, and TRDC.
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TMP96C031N/F
Figure 3.7 (1). Block Diagram of 8-Bit Timers (Timers 0 and 1)
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TMP96C031N/F
➀ Prescaler
This 9-bit prescaler generates the clock input to the
8-bit timers, 16-bit timer/event counters, and baud rate
generators by further dividing the fundamental clock (fc)
after it has been divided by 4 (fc/4).
Among them, 8-bit timer uses 4 types of clock:
φT1, φ T4, φT16, and φT256.
This prescaler can be run or stopped by the timer
operation control register TRUN <PRRUN>. Counting
starts when <PRRUN> is set to “1”, while the prescaler is
cleared to zero, and stops operation when <PRRUN> is
set to “0”. Resetting clears <PRRUN> to “0”, which
clears and stops the prescaler.
Figure 3.7 (2). Prescaler
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TMP96C031N/F
➁ Up-counter
This is an 8-bit binary counter counted by an input
clock specified by mode register T01MOD for timers 0
and 1, or mode register T23MOD for timers 2 and 3.
Input clocks for timer 0 or 2 can be selected from internal
clocks φ T1, φ T4, and φT16 depending to the value set in
the TI0 pin can also be selected.
The input clock of timer 1 or 3 depends on the operation mode; in 16-bit timer mode, timer 0/2 overflow output is used as the output clock. When set to any other
mode than 16-bit timer mode, the input clock is selected
from the internal clocks φ T1, φ T16, and φT256 as well
as the comparator output (match detection signal) of
timer 0 according to the set value of T01MOD register or
T23MOD.
Example: When T01MOD <T01M1,0> = 01, the over
flow output of timer 0 becomes the input
clock of timer 1 (16-bit timer).
When T01MOD7, 6 = 00, T01MOD3, 2 =
01, φ T1 (8/fc) becomes the input of timer
1 (8-bit timer).
Operation mode is also set by T01MOD register and
T23MOD register. When reset, it is initialized to T01MOD
<T01M1, 0> = 00, T23MOD <T23M1, 0> = 00 whereby
the up-counter is placed in the 8-bit timer mode.
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The counting and stop and clear of up-counter can
be controlled for each interval timer by the timer operation control register TRUN. When reset, all up-counters
will be cleared to stop the timers.
➂ Timer register
This is an 8-bit register for setting an interval time.
When the set value of timer registers TREG0, TREG1,
TREG2, TREG3 matches the value of up-counter, the
comparator match detect signal becomes active. If the
set value is 00H, this signal becomes active when the upcounter overflows.
Timer register TREG0/TREG2 is of double buffer
structure, each of which makes a pair with register buffer.
TREG0/TREG2 is used to control enable/disable of
the double buffers according to the timer register double
buffer control register, TRDC <TR0DE, TR2DE>. It is disabled when <TR0DE>/<TR2DE> = 0 and enabled when
they are set to 1.
In the condition of double buffer enable state, the
data is transferred from the register buffer to the timer
register when the 2n - 1 overflow occurs in PWM mode,
or at the PPG cycle in PPG mode.
When reset, it will be initialized to <TR0DE>/
<TR2DE> = 0 to disable the double buffer. To use the
double buffer, write data in the timer register, set
<TR0DE>/<TR2DE> to 1, and write the following data in
the register buffer.
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TMP96C031N/F
Figure 3.7 (3). Configuration of Timer Register 0/2
Note:
Timer register and the register buffer are allocated to the same memory address. When <TR0DE>/<TR2DE> = 0, the same value is written in the register buffer as well as the timer register, while when <TR0DE>/<TR2DE> = 1 only the register buffer is written.
The memory address of each timer register is as follows.
TREG0: 000022H
TREG1: 000023H
64
TREG2: 000026H
TREG3: 000027H
All registers are write-only and cannot be read.
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TMP96C031N/F
Figure 3.7 (4). Timer 0, 1 Mode Register (T01MOD)
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65
TMP96C031N/F
Figure 3.7 (5). Timer 2,3 Mode Register (T23MOD)
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TMP96C031N/F
Figure 3.7 (6). 8-Bit Timer Flip-Flop Control Register (TFFCR)
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67
TMP96C031N/F
Figure 3.7 (7). Timer Operation Control Register (TRUN)
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TMP96C031N/F
Figure 3.7 (8). Timer Register Double Buffer Control Register (TRDC)
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TMP96C031N/F
➃ Comparator
The operation of 8-bit timers will be described below:
(1)
A comparator compares the value in the up-counter
with the values to which the timer register is set. When
they match, the up-counter is cleared to zero and an
interrupt signal (INTT0, INTT1, INTT2, INTT3) is generated. If the timer flip-flop inversion is enabled, the timer
flip-flop is inverted at the same time.
8-bit timer mode
Four interval timers 0, 1, 2, 3, can be used independently as 8-bit interval timer. All interval timers operate
in the same manner, and thus only the operation of
timer 1 will be explained below.
➄ Timer flip-flops (timer F/F)
➀ Generating interrupts in a fixed cycle
The timer flip-flops are inverted according to the
interval timer match detect signal (comparator output).
The signal can output a value to the timer output pins
TO1 (also used as P70) and TO3 (also used as P71).
There are two timer flip-flops: TFF1 for timers 0 and
1; TFF3 for timers 2 and 3. TFF1 is output to the TO1 pin;
TFF3 to the TO3 pin.
TO3 (also used as P71) is multiplexed using the
DMUX pin; setting must be done using the port 7 control
registers (P7CRL and P7CRH).
To generate timer 1 interrupt at constant intervals using
timer 1 (INTT1), first stop timer 1 then set the operation
mode, input clock, and a cycle to T01MOD and
TREG1 register, respectively. Then, enable interrupt
INTT1 and start the counting of timer 1.
Example: To generate timer 1 interrupt every 40
microseconds at fc = 16MHz, set each
register in the following manner.
MSB
7
LSB
6
5
4
3
2
1
0
TRUN
←
–
–
–
–
–
–
0
–
Stop timer 1, and clear it to “0”.
T01MOD
←
0
0
x
x
0
1
–
–
Set the 8-bit timer mode, and select φT1
(0.5µs @ fc = 16MHz) as the input clock.
TREG1
←
0
1
1
0
1
0
0
0
Set the timer register at 40µs φT1 = 50H.
INTET10
←
1
1
0
1
–
–
–
–
Enable INTT1, and set it to “Level 5”.
TRUN
←
x
x
1
–
–
–
1
–
Start timer 1 counting.
Note:
x; don’t care
–; no change
Use the following table for selecting the input clock.
Table 3.7 (1) 8-Bit Timer Interrupt Cycle and Input Clock
Input Clock
Resolution
φT1 (8/fc)
0.4µs ~ 102.4µs
0.4µs
φT4 (32/fc)
1.6µs ~ 409.6µs
1.6µs
φT16 (128/fc)
φT256 (2048/fc)
70
Interrupt Cycle
(at fc = 20MHz)
6.4µs ~ 1.638ms
102.4µs ~ 2.621ms
6.4µs
102.4µs
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TMP96C031N/F
➁ Generating a 50% duty square wave pulse
The timer flip-flop is inverted at constant intervals, and
its status is output to timer output pin (TO1).
MSB
Example: To output a 2.4µs square wave pulse from
TO1 pin at fc = 20MHz, set each register in
the following procedures. Either timer 0 or
timer 1 may be used, but this example uses
timer 1.
LSB
7
6
5
4
3
2
1
0
TRUN
←
–
–
–
–
–
–
0
–
Stop timer 1, and clear it to “0”.
T01MOD
←
0
0
x
x
0
1
–
–
Set the 8-bit timer mode, and select φT1 as the input clock.
TREG1
←
0
0
0
0
0
0
1
1
Set the timer register at 2.4µs ÷ φT1 ÷ 2 = 3.
TFFCR
←
–
–
–
–
1
0
1
1
Clear TFF1 to “0”, and set to invert by the match detect signal from timer 1.
P7CRL
←
–
–
–
–
–
–
1
0
Select P71 as TO1 pin.
TRUN
←
x
x
1
–
–
–
1
–
Start timer 1 counting.
Note:
x; don’t care
–; no change
Figure 3.7 (9). Square Wave (50% Duty) Output Timing Chart
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TMP96C031N/F
➂ Making timer 1 count up by match signal from timer
0 comparator
Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1.
Figure 3.7 (10). Timer 1 Count Up by Timer 0
➃ Output inversion with software
The value of timer flip-flop (Timer F/F) can be inverted,
independent of timer operation.
Writing “00” into TFFCR <TFF1C1, 0> inverts the value
of TFF1, writing “00” into TFFCR <FF3C1, 0> inverts
the value of TFF3.
➄ Initial setting of timer flip-flop (Timer F/F)
The value of TFF1 can be initialized to “0” or “1”, independent of timer operation.
For example, write “10” in TFFCR <TFF1C1, 0> to
clear TFF1 to “0”, while write “01” in TFFCR <TFF1C1,
0> to set TFF1 to “1”.
Note:
72
(2)
16-bit timer mode
A 16-bit interval timer is configured by combining timers 0 and 1, or timers 2 and 3.
Timers 0 and 1 combined function the same as timers
2 and 3. A combination of timers 0 and 1 is used for
explanation here.
To configure a 16-bit timer by cascade-connecting timers 0 and 1, set the mode register, T01MOD
<T10M1,0>, to 00.
Setting 16-bit timer mode the input clock for timer 1 to
timer 0 overflow output regardless of the value set in
the clock control register, TCLK.
The value of timer register and timer flip-flop cannot be read.
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TMP96C031N/F
Table 3.7 (2) 16-Bit Timer (Interrupt) and Input Clock
Interrupt Cycle
(at fc = 20MHz)
Resolution
0.4µs ~ 26.214ms
0.4µs
φT4 (32/fc)
1.6µs ~ 104.857ms
1.6µs
φT16 (128/fc)
6.4µs ~ 419.430ms
6.4µs
Input Clock
φT1 (8/fc)
The lower 8-bit of the timer (interrupt) cycle are set by the
timer register TREG0, and the upper 8 bits are set by TREG1.
Note that TREG0 always must be set first. (Writing data into
TREG0 disables the comparator temporarily, and the comparator is restarted by writing data into TREG1.)
Setting example:
To generate an interrupt INTT1 every
0.4 seconds at fc = 20MHz, set the
following values for timer registers
TREG0 and TREG1:
When counting with input clock of
φT16 (8µs @ 16MHz) 0.4 sec ÷ 4µs
= 62500 = F424H
The comparator match signal is output from timer 0
each time the up-counter UC0 matches TREG0, where the
up-counter UC0 is not to be cleared.
INT0 is not to be generated at this time, either.
With the timer 1 comparator, the match detect signal is
output at each comparator timing when up-counter UC1 and
TREG1 values match. When the match detect signal is output
simultaneously from both comparators of timer 0 and timer 1,
the up-counters UC0 and UC1 are cleared to “0”, and the
interrupt INTT1 is generated. If inversion is enabled, the value
of the timer flip-flop TFF1 is inverted.
Therefore, set TREG1 = F4H and
TREG0 = 24H, respectively.
Figure 3.7 (11). Output Timer by 16-Bit Timer Mode
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TMP96C031N/F
(3)
8-bit PPG (Programmable Pulse Generation) Output
mode
Square wave pulse can be generated at any frequency
and duty by timer 0 or timer 1 and timer 0. The output
pulse may be either low-active or high-active. In this
mode, timer 1 cannot be used.
With timer 0, data are output to the TO1 pin (also used
as P70); with timer 2, to the TO3 pin (also used as
P71).
Figure 3.7 (12). Block Diagram of 8-Bit PPG Output Mode
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TMP96C031N/F
When the double buffer of TREG0 is enabled in this
mode, the value of register buffer will be shifted in TREG0 each
time TREG1 matches UC0.
Use of the double buffer makes easy handling of low duty
waves (when duty is varied).
Example: Generating 1/4 duty 62.5kHz pulse @ fc = 20MHz)
• Calculate the value to be set for timer register.
To obtain the frequency 62.5kHz, the pulse cycle t
should be: t = 1/62.5kHz = 16µs.
Given φ T1 = 0.4µs @ 20MHz),
16µs ÷ 0.4µs = 40
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Consequently, to set the timer register 1 (TREG1) to
TREG1 = 40 = 28H and then duty to 1/4, t x 1/4 =
16µs x 1/4 = 4µs
4µs ÷ 0.4µs = 10
Therefore, set timer register 0 (TREG0) to TREG0 = 10
= 0AH.
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TMP96C031N/F
MSB
←
TRUN
LSB
7
6
5
4
3
2
1
0
x
x
–
–
–
–
0
0
Stop timer 0, and clear it to “0”.
T01MOD
←
1
0
x
x
x
x
0
1
Set the 8-bit PPG mode, and select φT1 as input clock.
TFFCR
←
–
–
–
–
0
1
1
x
Sets TFF1 and enables the inversion and double buffer enable.
Writing “10” provides negative logic pulse.
TREG0
←
0
0
0
0
1
0
1
0
Write “0AH”.
TREG1
←
0
0
1
0
1
0
0
0
Write “28H”.
P7CRL
←
–
–
–
–
–
–
1
0
Set P70 as the TO1 pin.
TRUN
←
x
x
1
–
–
–
1
1
Start timer 0 and timer 1 counting.
Note:
(4)
x; don’t care
–; no change
8-bit PWM Output mode (Pulse Width Modulation)
Mode used for timers 1 and 3. Up to 2 PWMs with a
resolution of 8-bit (PWM1 and PWM3) pulse can be
output.
With timer 1, PWM is output to the TO1 pin (also used
as P70); with timer 3, to the TO3 pin (also used as
P71).
Timer 0 or 2 is used as an 8-bit timer.
Timer 1 (PWM1) is explained here because the operation is the same as timer 3.
Timer output is inverted when up-counter (UC1)
76
matches the set value of timer register TREG or when
2n - 1 (n = 6, 7, or 8; specified by T01MOD) counter
overflow occurs. Up-counter UC1 is cleared when 2n 1 counter overflow occurs. For example, when n = 6,
6-bit PWM will be output, while when n = 7, 7-bit PWM
will be output.
To use this PWM mode, the following conditions must
be satisfied.
(Set value of timer register) < (Set value of 2n - 1
counter overflow)
(Set value of timer register ≠ 0)
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TMP96C031N/F
Figure 3.7 (13). Block Diagram of 8-Bit PWM Waveforms
In this mode, the value of register buffer will be shifted in
TREG0 if 2n - 1 overflow is detected when the double buffer of
TREG0 is enabled.
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Use of the double buffer makes the handling of small
duty waves easy.
77
TMP96C031N/F
To realize 50.8µs of PWM cycle by φT1 = 0.4µs (@ fc =
20MHz),
Example: To output the following PWM waves to TO1
pin at fc = 20MHz.
50.8µs ÷ 0.4µs = 127 = 2n - 1
Consequently, n should be set to 7.
As the period of low level is 36µs, for φT1 = 0.4µs, set the
following value for TREG0:
36µs ÷ 0.4µs = 90 = 5AH
MSB
LSB
7
6
5
4
3
2
1
0
TRUN
←
x
x
–
–
–
–
–
0
Stop timer 0, and clear it to “0”.
T01MOD
←
1
1
1
0
–
–
0
1
Set 8-bit PWM mode (cycle : 27 - 1)
and select φT1 as the input clock.
TFFCR
←
–
–
–
–
1
0
1
x
Clears TFF1, enables the inversion and double buffer.
TREG0
←
0
1
0
1
1
0
1
0
Write “5AH”.
P7CRL
←
–
–
–
–
–
–
1
0
Set P70 as the TO1 pin.
TRUN
←
x
x
1
–
–
–
–
1
Start timer 0 counting.
Note : x; don’t care
–; no change
Table 3.7 (3) PWM Cycle and the Setting of 2n - 1 Counter
PWM Cycle (@ fc = 20 MHz)
φT1
78
φT4
φT16
26 - 1
25.2µsec (39.0kHz)
100µsec (10.0kHz)
4.03msec (2.4kHz)
27 - 1
50.8µsec (19.7kHz)
203µsec (4.9kHz)
812msec (1.2kHz)
28 - 1
102µsec (9.80kHz)
408µsec (2.4kHz)
1.63msec (0.61kHz)
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TMP96C031N/F
(5)
Table 3.7 (4) shows the list of 8-bit timer modes.
Table 3.7 (4) Timer Mode Setting Registers
Mode
T01M
(T23M)
PWM0
(PWM2)
01
–
8-bit timer
(8-bit x 8-bit mode x 1channel)
(Comparator output from the lower timer is
input to the upper timer.)
00
–
8-bit timer x 2channel
00
8-bit PPG x 1channel
8-bit PWM x 1channel (Lower)
8-bit timer x 1channel (Upper)
Timer Mode
(8-bit timer x 2channel)
16-bit timer
(Full 16-bit) x 1channel
Note:
Upper Input
T1CLK
(T3CLK)
Lower Input
T0CLK
(T2CLK)
Invert Select
FF1IS
(FF3IS)
–
(External clock,
φT1, 4, 16)
–
00
(External clock,
φT1, 4, 16)
0 : Lower timer
1 : Upper timer
–
(φT1, T16, T256)
(External clock,
φT1, 4, 16)
0 : Lower timer
1 : Upper timer
10
–
–
(External clock,
φT1, 4, 16)
–
11
PWM cycle
(φT1, T16, T256)
(External clock,
φT1, 4, 16)
–
–: don’t care
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TMP96C031N/F
3.8 16-Bit PWM Timer
The TMP96C031F contains one (timer 4) multifunctional 16-bit
timer/event counter with the following operation modes.
Timer/event counter consists of 16-bit up-counter, two
16-bit timer registers, two 16-bit capture registers (One of
them applies double-buffer), two comparators, capture input
controller, and timer flip-flop and the control circuit.
•
•
•
•
•
•
Timer/event counter is controlled by 4 control registers:
T4MOD, T4FFCR, TRUN and T45CR.
80
16-bit interval timer mode
16-bit event counter mode
16-bit programmable pulse generation mode
Frequency measurement mode
Pulse width measurement mode
Time differential measurement mode
Figure 3.8 (1) shows the block diagram of 16-bit timer/
event counter (timer 4).
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TMP96C031N/F
Figure 3.8 (1). Block Diagram of 16-Bit Timer (Timer 4)
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81
TMP96C031N/F
Figure 3.8 (2). 16-Bit Timer Mode Controller Register (T4MOD) (1/2)
82
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TMP96C031N/F
Figure 3.8 (3). 16-Bit Timer Mode Controller Register (T4MOD) (2/2)
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83
TMP96C031N/F
Figure 3.8 (4). 16-Bit Timer 4 F/F Control (T4FFCR)
84
TOSHIBA CORPORATION
TMP96C031N/F
Figure 3.8 (5). 16-Bit Timer (Timer 4) Control Register (T45CR)
Figure 3.8 (6). Timer Operation Control Register (TRUN)
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85
TMP96C031N/F
➀ Up-counter
UC4 is a 16-bit binary counter which counts up
according to the input clock specified by T4MOD
<T4CLK1,0> register.
As the input clock, one of the internal clocks φT1(8/
fc), φT4 (32/fc), and φT16 (128/fc) from 9-bit prescaler
(also used for 8-bit timer), and external clock from TI4
pin (also used as P72/INT4 pin) can be selected.
When reset, it will be initialized to <T4CLK1,0> = 00
to select TI4 input pin mode. Counting or stop and
clear of the counter is controlled by timer operation
control register TRUN <T4RUN> .
When clearing is enabled, up-counter UC4 will be
cleared to zero each time it coincides matches the
TREG4 timer register is of double buffer structure,
which is paired with register buffer. The timer control
register T45CR <DB4EN> controls whether the double buffer should be enabled or disabled. : disabled
when <DB4EN> = 0, while enabled when <DB4EN>
= 1.
When the double buffer is enabled, the timing to
transfer data from the register buffer to the timer register is at the match between the up-counter (UC4) and
timer register TREG5.
When reset, it will be initialized to <DB4EN> = 0,
whereby the double buffer is disabled. To use the
double buffer, write data in the timer register, set
<DB4EN> = 1, and then write the following data in the
86
timer register TREG5. The “clear enable/disable” is set
by T4MOD <CLE>.
If clearing is disabled, the counter operates as a freerunning counter.
➁ Timer registers
These two 16-bit registers are used to set the interval
time. When the value of up-counter UC4 matches the
set value of this timer register, the comparator match
detect signal will be active.
Setting data for timer register (TREG4 and TREG5) is
executed using 2-byte data transfer instruction or
using 1-byte data transfer instruction twice for lower
8-bit and upper 1-bit in order.
register buffer.
TREG4 and register buffer are allocated to the same
memory addresses 000030H/000031H. When
<DB4EN> = 0, same value will be written into only the
register buffer.
➂ Capture Register
These 16-bit registers are used to hold the values of
the up-counter.
Data in the capture registers should be read by a 2byte data load instruction or two 1-byte data load
instruction, from the lower 8-bit followed by the upper
8-bit.
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TMP96C031N/F
➃ Capture Input Control
➄ Comparator
This circuit controls the timing to latch the value of upcounter UC4 into (CAP1, CAP2). The latch timing of
capture register is controlled by register T4MOD
<CAP12M 1, 0>/T5MOD <CAP34M1,0>.
These are 16-bit comparators which compare the upcounter UC4 value with the set value of (TREG4,
TREG5) to detect the match. When a match is
detected, the comparators generate and interrupt
(INTT4, INTT5) respectively. The up-counter UC4 is
cleared only when UC4 matches TREG5. (The clearing of up-counter UC4 can be disabled by setting
T4MOD <CLE> = 0.)
• When T4MOD <CAP12M 1, 0> = 00
Capture function is disabled. Disable is the default on
reset.
• When T4MOD <CAP12M1, 0> = 01
Data is loaded to CAP1 at the rise edge of TI4 pin
(also used P80/INT4) input, while data is loaded to
CAP2 at the rise edge of TI5 pin (also used as P81/
INT5) and input. (Time difference measurement)
• When T4MOD <CAP12M1, 0> = 10
Data is loaded to CAP1 at the rise edge of TI4 pin
input, while to CAP2 at the fall edge. Only in this setting, interrupt INT4 occurs at fall edge. (Pulse width
measurement)
• When T4MOD <CAP12M1, 0> = 11
Data is loaded to CAP1 at the rise edge of timer flipflop TFF1, while to CAP2 at the fall edge.
Besides, the value of up-counter can be loaded to
capture registers by software. Whenever “0” is written
in T4MOD <CAP1IN> the current value of up-counter
will be loaded to capture register CAP1. It is necessary to keep the prescaler in RUN mode (TRUN
<PRRUN> to be “1”).
➅ Timer flip-flop (TFF4)
This flip-flop is inverted by the match detect signal
from the comparators and the latch signals to the
capture registers. Disable/enable of inversion can be
set for each element by T4FFCR <CAP2T4, CAP1T4,
EQ5T4, EQ4T4>. TFF4 will be inverted when “00” is
written in T4FFCR <TFF4C1,0>. Also it is set to “1”
when “10” is written, and cleared to “0” when “10” is
written. The value of TFF4 can be output to the timer
output pin TO4 (also used as P70).
➆ Timer flip-flop (TFF5)
This flip-flop is inverted by the match detect signal
from the comparator and the latch signal to the capture register CAP2. TFF5 will be inverted when “00” is
written in T4FFCR <TFF5C1,0>/T6FFCR
<TFF6C1,0>. Also it is set to “1” when “10” is written,
and cleared to “0” when “10” is written. The value of
TFF5 can be output to the timer output pin TO5 (also
used as P82).
TO5 (also used as P30) is multiplexed using the HWR
pin; setting must be done using the port 3 control register, P3CRL.
Note: TO5 (also used as P30) is multiplexed with HWR; setting
must be done using the P3SR.
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TMP96C031N/F
(1)
16-Bit Timer Mode
In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5.
Generating interrupts at fixed intervals
7
6
5
4
3
2
1
0
TRUN
←
x
x
–
0
–
–
–
–
Stop timer 4.
INTET54
←
1
1
0
0
1
0
0
0
Enable INTTR5 and sets interrupt level 4. Disable INTTR4.
T4FFCR
←
1
1
0
0
0
0
1
1
Disable trigger.
T4MOD
←
0
0
1
0
0
1
*
*
Select internal clock for input and disable the capture function.
(** = 01, 10, 11)
←
TREG5
←
TRUN
0
0
1
0
1
0
0
0
*
*
*
*
*
*
*
*
1
x
1
1
–
–
–
–
Note : x; don’t care
(2)
Start timer 4.
–; no change
16-Bit Event Counter Mode
external clock (TI4 pin input) as the input clock. To read
the value of the counter, first perform the “software
capture” once and read the captured value.
The counter counts at the rise edge of TI4 pin input.
TI4 can also be used as P72/INT4.
In 16-bit timer mode as described in above, the timer
can be used as an event counter be selecting the
7
6
5
4
3
2
1
0
TRUN
←
x
x
–
0
–
–
–
–
Stop timer 4.
P7CR
←
–
–
0
0
–
–
–
–
Set P72 to input mode.
INTET54
←
1
1
0
0
1
0
0
0
Enable INTTR5 and sets interrupt level 4, while disable INTTR4.
T4FFCR
←
1
1
0
0
0
0
1
1
Disable trigger.
T4MOD
←
0
0
1
0
0
1
0
0
Select TI4 as the input clock.
TREG5
←
*
*
*
*
*
*
*
*
Set the number of counts (16-bit).
TRUN
←
x
x
1
1
–
–
–
–
Start timer 4.
Note:
88
Set the interval time (16-bit).
When used as an event counter, set the prescaler in RUN mode.
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TMP96C031N/F
(3)
16-Bit Programmable Pulse Generation (PPG) Mode
up-counter UC4 with the timer register TREG4 or 5
and to be output to TO4 (also used as P70). In this
mode, the following conditions must be satisfied.
The PPG mode is obtained by inversion of the timer
flip-flop TFF4 that is to be enabled by the match of the
(Set value of TREG4) < (Set value of TREG5)
7
6
5
4
3
2
1
0
TRUN
←
x
x
–
0
–
–
–
–
Stop timer 4.
TREG4
←
*
*
*
*
*
*
*
*
Set the duty. (16-bit).
TREG5
←
*
*
*
*
*
*
*
*
Set the cycle. (16-bit).
T45CR
←
*
*
*
*
*
*
*
*
Double Buffer of TREG4 enable
T4FFCR
←
1
1
0
0
0
0
1
1
Set the mode to invert TFF4 at the match with
(Change the duty and cycle at the interrupt INTTR5).
TREG4/TREG5, and also set the TFF4 to “0”.
T4MOD
←
0
0
1
0
0
1
0
0
(** = 01, 10, 11)
Select the internal clock for the input, and disable the
capture function.
P7CR
←
–
–
–
–
–
–
1
1
Assign P70 as TO4.
TRUN
←
x
x
1
1
–
–
–
–
Start timer 4.
Note : x; don’t care
–; no change
Figure 3.8 (7). Programmable Pulse Generation (PPG) Output Waveforms
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89
TMP96C031N/F
When the double buffer of TREG4 is enabled in this
mode, the value of register buffer 4 will be shifted in TREG4 at
match with TREG5. This feature makes easy the handling of
low duty waves.
Figure 3.8 (8). Operation of Register Buffer
Shows the block diagram of this mode.
Figure 3.8 (9). Block Diagram of 16-Bit PPG Mode
90
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TMP96C031N/F
(4)
Application Examples of Capture Function
The loading of up-counter (UC4) values into the capture registers CAP1 and CAP2, the timer flip-flop TFF4
inversion due to the match detection by comparators
CP4 and CP5, and the output of the TFF4 status to
TO4 pin can be enabled or disabled. Combined with
interrupt function, they can be applied in many ways,
for example;
➀ One-shot pulse output from the external trigger
pulse
➁ Frequency measurement
➂ Pulse width measurement
➃ Time difference measurement
➀ One-Shot Pulse Output from the External Trigger
Pulse
Set the up-counter UC4 in free-running mode with the
internal input clock, input the external trigger pulse
from TI4 pin, and load the value of up-counter into
capture register CAP1 at the rise edge of the TI4 pin.
Then set T4MOD <CAP12M1, 0> = 01.
When the interrupt INT4 is generated at the rise edge
of the TI4 pin, set the CAP1 value (c) plus a delay time
(d) to TREG5 (= c + d), and set the above set value (c +
d) plus a one-shot pulse width (p) to TREG5 (= c + d +
p). When interrupt INT4 occurs the T4FFCR <EQ5T4,
EQ4T4> register sgould be set that the TFF4 inversion
is enabled only when the up-counter value matches
TREG4 or TREG5. When interrupt INTTR5 occurs, this
inversion will be disabled.
Figure 3.8 (10). One-Shot Pulse Output (with Delay)
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TMP96C031N/F
Setting example: To output 2ms one-shot with 3ms delay
92
to the external trigger pulse to TI4 pin.
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TMP96C031N/F
When delay is unnecessary, invert timer flip-flop TFF4
when the up-counter value is loaded into capture register 1
(CAP1), and set the CAP1 value (c) plus the one-shot pulse
width (p) to TREG5 when the interrupt INT4 occurs. The TFF4
inversion should be enabled when the up-counter (UC4) value matches TREG5, and disabled when generating the interrupt
INTTR5.
Figure 3.8 (11). One-Shot Pulse Output (without Delay)
➁ Frequency Measurement
The frequency of the external clock can be measured
in this mode. The clock is input through the TI4 pin, and
its frequency is measured by the 8-bit timers (Timer 0
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and Timer 1) and the 16-bit timer/event counter (Timer 4).
The TI4 pin input should be selected for the input
clock of Timer 4. The value of the up-counter is loaded
into the capture register CAP1 at the rise edge of the timer
flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and
into CAP2 at its fall edge.
The frequency is calculated by the difference between
the loaded values in CAP1 and CAP2 when the interrupt
(INTT0 or INTT1) is generated by either 8-bit timer.
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TMP96C031N/F
Figure 3.8 (12). Frequency Measurement
For example, if the value for the level “1” width of
TFF1 of the 8-bit timer is set to 0.5 s. and the difference
94
between CAP1 and CAP2 is 100, the frequency will be
100/0.5[s] = 200[Hz].
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TMP96C031N/F
➂ Pulse Width Measurement
This mode allows measuring the “H” level width of an
external pulse. While keeping the 16-bit timer/event
counter counting (free-running) with the internal clock
input, the external pulse is input through the TI4 pin. Then
the capture function is used to load the UC4 values into
CAP1 and CAP2 at the rising edge and falling edge of the
external trigger pulse respectively. The interrupt INT4
occurs at the falling edge of TI4.
The pulse width is obtained from the difference
between the values of CAP1 and CAP2 and the internal
clock cycle.
For example, if the internal clock is 0.8 microseconds
and the difference between CAP1 and CAP2 is 100, the
pulse width will be 100 x 0.8 = 80 microseconds.
Figure 3.8 (13). Pulse Width Measurement
Note:
Only in this pulse width measuring mode (T4MOD <CAP12M1, 0> = 10), external interrupt INT4 occurs at the falling edge of TI4 pin input. In other
modes, it occurs at the rising edge.
The width of “L” level can be measured from the difference between the first C2 and the second C1 at the
second INT4 interrupt.
➃ Time Difference Measurement
This mode is used to measure the difference in time
between the rising edges of external pulses input through
TI4 and TI5.
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Keep the 16-bit timer/event counter (Timer 4) counting (free-running) with the internal clock, and load the
UC4 value into CAP1 at the rising edge of the input pulse
to TI4. Then the interrupt INT4 is generated.
Similarly, the UC4 value is loaded into CAP2 at the
rising edge of the input pulse to TI5, generating the interrupt INT5.
The time difference between these pulses can be
obtained from the difference between the time counts at
which loading the up-counter value into CAP1 and CAP2
has been done.
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TMP96C031N/F
Figure 3.8 (14). Time Difference Measurement
(5)
Different Phased Pulses Output Mode
In this output mode, signals with any different phase
can be outputted by free-running up-counter UC4.
When the value in up-counter UC4 and the value in
TREG4 (TREG5) match, the value in TFF4 (TFF5) is
inverted and output to TO4 (TO5).
This mode can only be used by 16-bit timer 4.
Figure 3.8 (15). Phase Output
Cycles (counter overflow time) of the above output
waves are listed below.
96
16MHz
20MHz
φT1
32.768ms
26.214ms
φT4
131.072ms
104.856ms
φT16
524.288ms
419.424ms
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TMP96C031N/F
3.9 Stepping Motor Control/Pattern Generation Port
The TMP96C031F contains 2 channels (PG0 and PG1) of 4-bit
hardware stepping motor control/pattern generation (herein
after called PG) which actuate in synchronization with the
(8-bit/16-bit) timers. The PG (PG0 and PG1) are shared in 8-bit
I/O ports P6.
Channel 0 (PG0) is synchronous with 8-bit timer 0 or
timer 1, 16-bit timer 4, channel 1 (PG1) is synchronous with 8-
bit timer2 or timer3, 16-bit timer4, to update the output.
The PG ports are controlled by control registers
(PG01CR) and can select either stepping motor control mode
or pattern generation mode. Each bit of the P6 can be used as
the PG port.
Channel 0 (PG0) and channel 1 (PG1) operate independently.
Except in the following case, both channels operate the
same. Thus, channel 0 (PG0) is explained here.
Difference between PG0 and PG1
Figure 3.9 (1). Pattern Generator/Stepping Motor Control Block Diagram
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TMP96C031N/F
Figure 3.9 (2a). Pattern Generation Control Register (PG01CR)
98
TOSHIBA CORPORATION
TMP96C031N/F
Figure 3.9 (2b). Pattern Generation Control Register (PG01CR)
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99
TMP96C031N/F
PG0REG
(004CH)
bit Symbol
7
6
PG03
PG02
Read/Write
After reset
Function
bit Symbol
0
Function
Prohibit Read
modify write
100
0
3
2
PG01
PG00
SA03
SA02
1
0
SA01
SA00
R/W
0
0
Undefined
Pattern Generation 0 (PG0) output latch register
(Reading the P6 that is set to the PG port allows to read-out.)
Shift alternate register 0
For the PG mode (4-bit write) register
Figure 3.9 (3). Pattern Generation 0 Register (PG0REG)
7
6
5
4
3
2
1
0
PG13
PG12
PG11
PG10
SA13
SA12
SA11
SA10
0
0
0
0
Read/Write
After reset
4
W
Prohibit Read
modify write
PG1REG
(004DH)
5
W
R/W
Pattern Generation 1 (PG1) output latch register
(Reading the P6 that is set to the PG port allows to read-out.)
Undefined
Shift alternate register 1
For the PG mode (4-bit write) register
Figure 3.9 (4). Pattern Generation 1 Register (PG1REG)
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TMP96C031N/F
Figure 3.9 (5). 16-bit Timer Trigger Control Register (T45CR)
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TMP96C031N/F
Figure 3.9 (6). Connection of Timer and Pattern Generator
(1)
Pattern Generation Mode
PG functions as a pattern generation according to the
setting of PG01CR <PAT1>/<PAT0>. In this mode,
writing from CPU is executed only on the shifter alternate register. Writing a new data should be done during
the interrupt operation of the timer for shift trigger, and
a pattern can be output synchronous with the timer.
In this mode, set PG01CR <PG0M> and <PG1M> to
1, and PG01CR <CCW0> and <CCW1> to 0.
The output of this pattern generator is output to port 6;
since port and functions can be switched on a bit basis
using port function control register P6CRL/P6CRH, any
port pin can be assigned to pattern generator output.
Figure 3.9 (7) shows the block diagram of this mode.
Figure 3.9 (7). Pattern Generation Mode Timing Example
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Figure 3.9 (7). Pattern Generation Mode Block Diagram (PG0)
In this pattern generation mode, only writing the output
latch is disabled by hardware, but other functions do the same
operation as 1-2 excitation in stepping motor control port
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mode. Accordingly, the data shifted by trigger signal from a
timer must be written before the next trigger signal is output.
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(2)
Stepping Motor Control Mode
➀ 4-phase 1-Step/2-Step Excitation
Figure 3.9 (8) and Figure 3.9 (9) show the output waveforms of 4-phase 1 excitation and 4-phase 2 excitation, respectively when channel 0 (PG0) is selected.
Figure 3.9 (8). Output Waveforms of 4-Phase 1-Step Excitation
(Normal Rotation and Reverse Rotation)
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Figure 3.9 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation)
The operation when channel 0 is selected is
explained below.
The output latch of PG0 (also used as P6) is shifted
at the rising edge of the trigger signal from the timer to be
output to the port.
The direction of shift is specified by PG01CR
<CCW0>: Normal rotation (PG00 → PG01 → PG02 →
PG03) when <CCW0> is set to “0”; reverse rotation
(PG00 ← PG01 ← PG02 ← PG03) when “1”. Four-phase
1-step excitation will be selected when only one bit is set
to “1” during the initialization of PG, while 4-phase 2-step
excitation will be selected when two consecutive bits are
set to “1”.
The value in the shift alternate registers are ignored
when the 4-phase 1-step/2-step excitation mode is
selected.
Figure 3.9 (10) shows the block diagram.
Figure 3.9 (10). Block Diagram of 4-Phase 1-Step Excitation/2-Step Excitation
(Normal Rotation)
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➁ 4-Phase 1-2 Step Excitation
Figure 3.9 (11) shows the output waveforms of 4phase 1 -2 step excitation when channel 0 is selected.
Figure 3.9 (11). Output Waveforms of 4-Phase 1-2 Step Excitation
(Normal Rotation and Reverse Rotation)
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The initialization for 4-phase 1-2 step excitation is as
follows:
By rearranging the initial value “b7 b6 b5 b4 b3 b2
b1 b0” to “b7 b3 b6 b2 b5 b1 b4 b0”, the consecutive 3
bits are set to “1” and other bits are set to “0” (positive
logic).
For example, if b7, b3, and b6 are set to “1", the initial value becomes “11001000”, obtaining the output
waveforms as shown in Figure 3.10 (11).
To get an output waveform of negative logic, set values 1s and 0’s of the initial value should be inverted. For
example, to change the output waveform shown in Figure 3.10 (11) into negative logic, change the initial value
to “00110111”.
The operation will be explained below for channel 0.
The output latch of PG0 (shared by P6) and the
shifter alternate register (SA0) for Pattern Generation are
shifted at the rising edge of trigger signal from the timer
to be output to the port. The direction of shift is set by
PG01CR <CCW0>.
Figure 3.9 (12) shows the block diagram.
Figure 3.9 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)
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Setting example: To drive channel 0 (PG0) by 4-phase 1-2
step excitation (normal rotation) when
7
6
5
4
3
2
1
0
TRUN
←
–
x
–
–
–
–
–
0
Stop timer 0, and clears it to zero.
TMOD
←
0
0
x
x
–
–
0
1
Set 8-bit timer mode and selects φT1 as the input clock of timer 0.
TFFCR
←
x
x
x
0
1
0
1
0
Clear TFF1 to zero and enables the inversion trigger by timer 0.
TREG0
←
*
*
*
*
*
*
*
*
Set the cycle in timer register.
P6CRL
←
1
0
1
0
1
0
1
0
Set P60 ~ P63 bits to PG output.
PG01CR ←
–
–
–
–
0
0
1
1
Select PG0 4-phase 1 - 2 step excitation mode and normal rotation.
PG0REG ←
1
1
0
0
1
0
0
0
Set an initial value.
←
1
x
–
–
–
–
–
1
Start timer 0.
TRUN
Note:
(3)
timer 0 is selected, set each register as follows:
x; don’t care
–; no change
Trigger Signal From Timer
The trigger signal from the timer which is used by PG is
not equal to the trigger signal of timer flip-flop (TFF1,
TFF4, TFF5, and TFF6) and differs as shown in Table
3.9 (1) depending on the operation mode of the timer.
Table 3.9 (1) Select of Trigger Signal
TFF1 Inversion
Note:
8-bit timer mode
Selected by TFFCR <TFF1IS> when the up-counter value matches
TREG0 or TREG1 value.
16-bit timer mode
When the up-counter value matches with both TREG0 and TREG1
values. (The value of up-counter = TREG1*28 + TREG0)
PPG output mode
When the up-counter value matches with both TREG0 and TREG1.
When the up-counter value matches TREG1 value (PPG cycle).
PWM output mode
When the up-counter value matches TREG0 value and PWM cycle.
Trigger signal for PG is not generated.
To shift PG, TFFCR <TFF1IE> must be set to “1” to enable TFF1 inversion.
Channel 1 of PG can be synchronized with the 16-bit
timer Timer 4. In this case, the PG shift trigger signal
from the 16-bit timer is output only when the upcounter UC4 value matches TREG5.
108
PG Shift
When using a trigger signal from Timer 4, set either
T4FFCR <EQ5T4> or T4MOD <EQ5T5> to “1” and a
trigger is generated when the value in UC4 and the
value in TREG5 match.
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TMP96C031N/F
(4)
Application of PG and Timer Output
As explained in “Trigger signal from timer”, the timing
to shift PG and invert TFF differs depending on the
mode of timer. An application to operate PG while
operating an 8-bit timer in PPG mode will be explained
below.
To drive a stepping motor, in addition to the value of
each phase (PG output), synchronizing signal is often
required at the timing when excitation is changed over.
In this application, port 6 is used as a stepping motor
control port to output a synchronizing signal to the
TO1 pin (shared by P70).
Figure 3.9 (13). Output Waveforms of 4-Phase 1-Step Excitation
Setting example:
7
6
5
4
3
2
1
0
TRUN
←
–
x
–
–
–
–
0
0
Stop timer 0, and clears it to zero.
TMOD
←
1
0
x
x
x
x
0
1
Set timer 0 and timer 1 in PPG output mode and selects φT1 as the input clock.
TFFCR
←
x
x
x
0
0
1
1
x
Enable TFF1 inversion and sets TFF1 to “1”.
TREG0
←
*
*
*
*
*
*
*
*
Set the duty of TO1 to TREG0.
TREG1
←
*
*
*
*
*
*
*
*
Set the cycle of TO1 to TREG1.
P7CR
←
–
–
–
–
–
–
1
0
Assign P70 as TO1.
P6CRL
←
1
0
1
0
1
0
1
1
Assign P60 ~ 63 as PG0.
PG01CR ←
–
–
–
–
0
0
0
1
Set PG0 in 4-phase 1-step excitation mode.
PG0REG ←
*
*
*
*
*
*
*
*
Set an initial value.
←
1
x
–
–
–
–
1
1
Start timer 0 and timer 1.
TRUN
Note:
x; don’t care
–; no change
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3.10 Serial Channel
The TMP96C031F contains 2 serial I/O channels for full duplex
asynchronous transmission (UART) as well as for I/O extension.
The serial channel has the following operation modes.
●
I/O interface mode
(channel 1 only)
Mode 0: To transmit and receive I/O data as well as
the synchronizing signal SCLK for extending I/O.
●
Asynchronous transmission
(UART) mode (channel 0 and 1)
Mode 1: 7-bit data
Mode 2: 8-bit data
Mode 3: 9-bit data
In mode 1 and mode 2, a parity bit can be added. Mode
3 has wake-up function for making the master controller start
slave controllers in serial link (multi-controller system).
Figure 3.10 (1) shows the data format (for one frame) in
each mode.
Figure 3.10 (1). Data Formats
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The serial channel has a buffer register for transmitting
and receiving operations, in order to temporarily store transmitted or received data, so that transmitting and receiving
operations can be done independently (full duplex).
However, in I/O interface mode, SCLK (serial clock) pin is
used for both transmission and receiving, the channel
becomes half-duplex.
The receiving data register is of a double buffer structure
to prevent the occurrence of overrun error and provides one
frame of margin before CPU reads the received data. The
receiving data register stores the already received data while
the buffer register receives the next frame data.
By using CTS and RTS (there is no RTS pin, so any one
port must be controlled by software), it is possible to halt data
send until CPU finishes reading receive data every time a frame
is received (Handshake function).
In the UART mode, a check function is added not to start
the receiving operation by error start bits due to noise. The
channel starts receiving data only when the start bit is
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detected to be normal at least twice in three samplings.
When the transmission buffer becomes empty and
requests the CPU to send the next transmission data, or when
data is stored in the receiving data register and the CPU is
requested to read the data, INTTX or INTRX interrupt occurs.
Besides, if an overrun error, parity error, or framing error occurs
during receiving operation, flag SC0CR/SC1CR <OERR,
PERR, FERR> will be set.
The serial channel 0/1 includes a special baud rate generator, which can set any baud rate by dividing the frequency
of four clocks (φT0, φT2, φT8, and φT32) from the internal prescaler (shared by 8-bit/16-bit timer) by the value 2 to 16.
In I/O interface mode, it is possible to input synchronous
signals as well as to transmit or receive data by external clock.
3.10.1 Control Registers
The serial channel is controlled by three control registers
SC0CR, SC0MOD, and BR0CR. Transmitted and received
data is stored in register SC0BUF.
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Figure 3.10 (2). Serial Mode Control Register (Channel 0, SC0MOD)
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Figure 3.10 (3). Serial Control Register (Channel, SC0CR)
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Note:
Figure 3.10 (4). Serial Channel Control (Channel 0, BR0CR)
SC0BUF
(50H)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(Transmission)
(Receiving)
Figure 3.10 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)
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Figure 3.10 (6). Serial Mode Control Register (Channel 1, SC1MOD)
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Figure 3.10 (7). Serial Control Register (Channel 1, SC1CR)
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Figure 3.10 (8). Baud Rate Generator Control Register (Channel 0, BR0CR)
SC1BUF
(0054H)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(Transmission)
(Receiving)
Figure 3.10 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)
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Figure 3.10 (10). Port 6, 7 Control Registers
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Port 3.10 (11). Serial Open Drain Enable Register (ODE)
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3.10.2 Configuration
Figure 3.10 (12) shows the block diagram of the serial channel 0.
Figure 3.10 (12). Block Diagram of the Serial Channel 0
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Figure 3.10 (13) shows the block diagram of the serial
channel 1.
÷ 16
Figure 3.10 (13). Block Diagram of the Serial Channel 1
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➀ Baud Rate Generator
Baud rate generator comprises a circuit that generates
transmission and receiving clocks to determine the
transfer rate of the serial channel.
The input clock to the baud rate generator, φT0 (fc/4),
φT2 (fc/16), φT8 (fc/64), or φT32 (fc/256) is generated
by the 9-bit prescaler which is shared by the timers.
●
UART mode
Transfer rate =
●
One of these input clocks is selected by the baud rate
generator control register BR0CR/BR1CR <BR0CK1,
0/BR1CK1, 0>.
The baud rate generator includes a 4-bit frequency
divider, which divides frequency by 2 to 16 values to
determine the transfer rate.
How to calculate a transfer rate when the baud rate
generator is used is explained below.
Input clock of baud rate generator
Frequency divisor of baud rate generator
I/O interface mode
Transfer rate =
Input clock of baud rate generator
Frequency divisor of baud rate generator
The relation between the input clock and the source clock (fc) is as follows:
φT0 = fc/4
φT2 = fc/16
φT8 = fc/64
φT32 = fc/256
Accordingly, when source clock fc is 12.288MHz, input clock is φT2 (fc/16), and frequency divisor is 5, the transfer rate in
UART mode becomes as follows:
Transfer rate =
fc/16
5
= 12.288 x 106/16/5/16 = 9600 (bps)
Table 3.10 (1) shows an example of the transfer rate in UART mode.
Also with 8-bit timer 0, the serial channel can get a transfer rate. Table 3.10 (2) shows an example of baud rate using
timer 0.
Table 3.10 (1) Selection of Transfer Rate (1) (When Baud Rate Generator is Used)
Unit (Kbps)
Input Clock
fc [MHz]
Note:
122
Frequency
Divisor
φT0
(fc/4)
φT2
(fc/16)
φT8
(fc/64)
φT32
(fc/256)
9.830400
2
76.800
19.200
4.800
1.200
↑
4
38.400
9.600
2.400
0.600
↑
8
19.200
4.800
1.200
0.300
↑
0
9.600
2.400
0.600
0.150
12.288000
5
38.400
9.600
2.400
0.600
↑
A
19.200
4.800
1.200
0.300
14.745600
3
76.800
19.200
4.800
1.200
↑
6
38.400
9.600
2.400
0.600
↑
C
19.200
4.800
1.200
0.300
Transfer rate in I/O interface mode is 8 times as fast as the values given in the above table.
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TMP96C031N/F
Table 3.10 (2) Selection of Transfer Rate (1) (When Timer 0 (Input Clock φT1) is Used)
Unit (Kbps)
fc
TREG0
12.288MHz
12MHz
9.8304MHz
8MHz
6.144MHz
1H
96
76.8
62.5
48
2H
48
38.4
31.25
24
3H
32
4H
24
5H
19.2
8H
12
AH
9.6
10H
6
14H
4.8
31.25
16
19.2
12
9.6
9.6
6
4.8
4.8
3
2.4
How to calculate the transfer rate (when timer 0 is used):
Transfer rate =
fc
TREG0 x 8 x 16
↑
(When timer 0 (input clock φT1) is used)
Input clock of timer 0
φT1 = fc/8
φT4 = fc/32
φT16 = fc/128
Note:
Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode.
➁ Serial Clock Generation Circuit
This circuit generates the basic clock for transmitting
and receiving data.
• I/O interface mode (channel 1 only)
When in SCLK output mode with the setting of
SC1CR <IOC> = “0", the basic clock will be generated
by dividing by 2 the output of the baud rate generator as
described before. When in SCLK input mode with the
setting of SC1CR <IOC> = “1", the rising edge or falling
edge will be detected according to the setting of SC1CR
<SCLKC> register to generate the basic clock.
• Asynchronous Communication (UART) mode
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According to the setting of SC0CR and SC1CR
<SC1, 0>, the above baud rate generator clock, internal
clock φ1 (500Kbps @ fc = 16 MHz), or the match detect
signal from timer 0 will be selected to generate the basic
clock SIOCLK.
➂ Receiving Counter
The receiving counter is a 4-bit binary counter used
in asynchronous communication (UART) mode and
counts up by SIOCLK clock. 16 pulses of SIOCLK are
used for receiving one bit of data, and the data bit is
sampled three times at 7th, 8th and 9th clock.
With the three samples, the received data is evaluated by the rule of majority.
For example, if the sampled data bit is “1", “0” and
“1” at 7th, 8th and 9th clock respectively, the received
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TMP96C031N/F
data is evaluated as “1”. The sampled data “0", “0” and
“1” is evaluated that the received data is “0”.
➃ Receiving Control
• I/O interface mode (channel 1 only)
When in SCLK1 output mode with the setting of
SC1CR <IOC> = “0", RxD1 signal will be sampled at the
rising edge of shift clock which is output to SCLK pin.
When in SCLK input mode with the setting SC1CR
<IOC> = “1", RxD1 signal will be sampled at the rising
edge or falling edge of SCLK input according to the setting of SC1CR <SCLKS> register.
• Asynchronous Communication (UART) mode
The receiving control has a circuit for detecting the
start bit by the rule of majority. When two or more “0” are
detected during 3 samples, it is recognized as start bit
and the receiving operation is started.
Data being received is also evaluated by the rule of
majority.
Received data is stored one bit by one bit in the
receiving buffer 1 (shift register type). When 7 bits or 8
bits of data are stored in the receiving buffer 1, the stored
data is transferred to another receiving buffer 2
(SC0BUF/SC1BUF), generating an interrupt INTRX0/
INTRX1. The CPU reads only receiving buffer 2
(SC0BUF/SC1BUF). Even before the CPU reads the
receiving buffer 2 (SC0BUF/SC1BUF), the received data
can be stored in the receiving buffer 1. However, unless
the receiving buffer 2 (SC0BUF/SC1BUF) is read before
all bits of the next data are received by the receiving
buffer 1, an overrun error occurs. If an overrun error
occurs, the contents of the receiving buffer 1 will be lost,
although the contents of the receiving buffer 2 and
SC0CR <RB8> SC1CR <RB8> are still preserved.
The parity bit added in 8-bit UART mode and the
most significant bit (MSB) in 9-bit UART mode are stored
in SC0CR <RB8>/SC1CR <RB8>.
When in 9-bit UART mode, the wake-up function of
the slave controllers is enabled by setting SC0MOD
<WU>/SC1MOD <WU> to “1", and interrupt INTRX0/
INTRX1 occurs only when SC0CR <RB8>/SC1CR
<RB8> is set to “1”.
➅ Transmission Counter
➄ Receiving Buffer
To prevent overrun error, the receiving buffer has a
double buffer structure.
Transmission counter is a 4-bit binary counter which
is used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK clock,
generating TxDCLK every 16 clock pulses.
Figure 3.10 (14). Generation of Transmission Clock
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➆ Transmission Controller
edge of the next TxDCLK, generating a transmission shift
clock TxDSFT.
• I/O interface mode (channel 1 only)
In SCLK output mode with the setting of SC1CR
<IOC> = “0", the data in the transmission buffer are output bit by bit to TxD1 pin at the rising edge of shift clock
which is output from SCLK1 pin.
In SCLK input mode with the setting SC1CR <IOC>
= “1", the data in the transmission buffer are output bit by
bit to TxD1 pin at the rising edge or falling edge of SCLK
input according to the setting of SC1CR <SCLKC> register.
• Asynchronous Communication (UART) mode
When transmission data is written in the transmission
buffer sent from the CPU, transmission starts at the rising
Handshake function
Serial channel 0 has a CTS0 pin. Using this pin, data
can be sent in units of one frame; thus, overrun errors
can be avoided. The handshake function is enabled/disabled by SC0MOD <CTSE>.
When the CTS0 pin goes high, after completion of
the current data send, data send is halted until the CTS0
pin goes low again. The INTTX0 Interrupts are generated,
requests the next send data to the CPU.
Though there is no RTS pin, a handshake function
can be easily configured by setting any port assigned to
the RTS function. The RTS should be output “High” to
request data send halt after data receive is completed by
a software in the RXD interrupt routine.
Figure 3.10 (15). Handshake Function
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TMP96C031N/F
Figure 3.10 (16). Timing of CTS (Clear to Send)
➇ Transmission Buffer
Transmission buffer (SC0BUF/SC1BUF) shifts to and
sends the transmission data written from the CPU from
the least significant bit (LSB) in order, using transmission
shift clock TxDSFT which is generated by the transmission control. When all bits are shifted out, the transmission buffer becomes empty and generates INTTX0/
INTTX1 interrupt.
➈ Parity Control Circuit
pared with SC0BUF <RB7>/SC1BUF <RB7> when in 7bit UART mode and with SC0MOD <RB8>/SC1MOD
<RB8> when in 8-bit UART mode. If they are not equal, a
parity error occurs, and SC0CR <PERR>/SC1CR
<PERR> flag is set
➉ Error Flag
Three error flags are provided to increase the reliability of receiving data.
1. Overrun error <OERR>
When serial channel control register SC0CR <PE>/
SC1CR <PE> is set to “1", it is possible to transmit and
receive data with parity. However, parity can be added
only in 7-bit UART or 8-bit UART mode. With SC0CR
<EVEN>/SC1CR <EVEN> register, even (odd) parity can
be selected.
For transmission, parity is automatically generated
according to the data written in the transmission buffer
SCBUF, and data are transmitted after being stored in
SC0BUF <TB7>/SC1BUF <TB7> when in 7-bit UART
mode while in SCMOD <TB8>/SCMOD <TB8> when in
8-bit UART mode. <PE> and <EVEN> must be set
before transmission data are written in the transmission
buffer.
For receiving, data is shifted in the receiving buffer 1,
and parity is added after the data is transferred in the
receiving buffer 2 (SC0BUF/SC1BUF), and then com-
126
If all bits of the next data are received in receiving
buffer 1 while valid data is stored in receiving buffer 2
(SCBUF), an overrun error will occur.
2. Parity error <PERR>
The parity generated for the data shifted in receiving
buffer 2 (SCBUF) is compared with the parity bit received
from RxD pin. If they are not equal, a parity error occurs.
3. Framing error <FERR>
The stop bit of received data is sampled three times
around the center. If the majority is “0", a framing error
occurs.
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11
Generating Timing
1) UART mode
Receiving
Mode
Interrupt timing
9-Bit
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Overrun error timing
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
9-Bit
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
Just before last bit is transmitted.
←
←
Framing error timing
Transmitting
Mode
Interrupt timing
2) I/O Interface mode
Transmission interrupt timing
SCLK output mode
Immediately after rise of last SCLK signal. (See figure 3.10 (19) .)
SCLK input mode
Immediately after rise of last SCLK signal (rising mode), or immediately after fall in
falling mode. (See figure 3.10 (20))
SCLK output mode
Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is,
immediately after last SCLK. (See figure 3.10 (21))
SCLK input mode
Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is,
immediately after SCLK. (See figure 3.10 (22))
Receiving interrupt timing
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3.10.3 Operational Description
(1)
Mode 0 (I/O interface mode)
This mode is used to increase the number of I/O pins
for transmitting or receiving data to or from the external
shifter register.
This mode includes SCLK output mode to output synchronous clock SCLK and SCLK input mode to input
external synchronous clock SCLK.
Figure 3.10 (17). Example of SCLK Output Mode Connection
FIgure 3.10 (18). Example of SCLK Input Mode Connection
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➀ Transmission
In SCLK output mode, 8-bit data and synchronous clock
are output from TxD pin and SCLK pin, respectively, each
time the CPU writes data in the transmission buffer. When
all data is output, INTES1 <ITX1C> will be set to generate
INTTX1 interrupt.
Figure 3.10 (19). Transmitting Operation in I/O Interface Mode (SCLK Output Mode)
In SCLK output mode, 8-bit data are output from TxD1
pin when SCLK input becomes active while data are
written in the transmission buffer by CPU.
When all data are output, INTES1 <ITXIC> will be set
to generate INTTX1 interrupt.
Figure 3.10 (20). Transmitting Operation in I/O Interface Mode (SCLK Input Mode)
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➁ Receiving
In SCLK output mode, synchronous clock is output
from SCLK pin and the data is shifted in the receiving
buffer 1 whenever the receive interrupt flag INTES1
<IRX1C> is cleared by reading the received data.
When 8-bit data are received, the data will be transferred in the receiving buffer 2 (SC1BUF) at the timing
shown below, and INTES1 <IRX1C> will be set again
to generate INTRX1 interrupt.
Figure 3.10 (21). Receiving Operation in I/O Interface Mode (SCLK Output Mode)
In SCLK input mode, the data is shifted in the receiving
buffer 1 when SCLK input becomes active, while the
receive interrupt flag INTES1 <IRX1C> is cleared by reading the received data. When 8-bit data is received, the
data will be shifted in the receiving buffer 2 (SC1BUF) at
the timing shown below, and INTES1 <IRX1C> will be set
again to generate INTRX interrupt.
Figure 3.10 (22). Receiving Operation in I/O Interface Mode (SCLK Input Mode)
Note:
130
For data receiving, the system must be placed in the receive enable state (SCMOD <RXE> = “1”)
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TMP96C031N/F
(2)
Mode 1 (7-bit UART Mode)
The 7-bit mode can be set by setting serial channel
mode register SC0MOD <SM1, 0> /SC1MOD <SM1,
0> to “01”.
In this mode, a parity bit can be added, and the addition of a parity bit can be enabled or disabled by serial
channel control register SC0CR <PE>/SC1CR <PE>,
Setting example:
When transmitting data with the following format, the control registers
should be set as described below.
Channel 0 is explained here.
7
6
5
4
3
2
1
0
P9CRL
←
–
–
–
–
–
–
1
1
Select P60 as the TxD pin.
SC0MOD
←
x
0
–
x
0
1
0
1
Set 7-bit UART mode.
SC0CR
←
x
1
1
x
x
x
0
0
Add an even parity.
BR0CR
←
0
x
1
0
0
1
0
1
Set transfer rate at 2400 bps.
TRUN
←
x
x
1
–
–
–
–
–
Start the prescaler for the baud rate generator.
INTES0
←
1
1
0
0
–
–
–
–
Enable INTTX0 interrupt and sets interrupt level 4.
SC0BUF
←
*
*
*
*
*
*
*
*
Set data for transmission.
Note:
(3)
and even parity or odd parity is selected by SC0CR
<EVEN>/SC1CR <EVEN> when <PE> is set to “1”
(enable).
x; don’t care
–; no change
Mode 2 (8-bit UART Mode)
The 8-bit UART mode can be specified by setting
SC0MOD <SM1, 0> / SC1MOD <SM1, 0> to “10”. In
this mode, parity bit can be added, the addition of a
parity bit is enabled or disabled by SC0CR <PE>/
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SC1CR <PE>, and even parity or odd parity is selected
by SC0CR <EVEN>/SC1CR <EVEN> when <PE> is
set to “1” (enable).
Setting example:
When receiving data with the following format, the control register
should be set as described below.
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Main setting
←
P9CRL
7
6
5
4
3
2
1
0
–
–
–
–
0
0
–
–
Select P61 (RxD) as the input pin.
SC0MOD
←
–
0
1
x
1
0
0
1
Enable receiving in 8-bit UART mode.
SC0CR
←
x
0
1
x
x
x
0
0
Add an odd parity.
BR0CR
←
0
x
0
1
0
1
0
1
Set transfer rate at 9600 bps.
TRUN
←
x
x
1
–
–
–
–
–
Start the prescaler for the baud rate generator.
INTES0
←
–
–
–
–
1
1
0
0
Enable INTTX0 interrupt and sets interrupt level 4.
Interrupt processing
Acc ← SC0CR and 00011100
if Acc ≠ 0 then ERROR
)
Acc ← SC0BUF
Note:
(4)
Check for error.
Read the received data.
x; don’t care
–; no change
Mode 3 (9-bit UART Mode)
Wake-up function
9-bit UART mode can be specified by setting
SC0MOD <SM1, 0> /SC1MOD <SM1, 0> to “11”. In
this mode, parity bit cannot be added
For transmission, the MSB (9th bit) is written in SCM0D
<TB8>, while in receiving it is stored in SCCR <RB8>.
For writing and reading the buffer, the MSB is read or
written first, then SC0BUF/SC1BUF.
In 9-bit UART mode, the wake-up function of slave
controllers is enabled by setting SC0MOD <WU> /
SC1MOD <WU> to “1”. The interrupt INTRX1/INTRX0
occurs only when <RB8> = 1
.
Figure 3.10 (23). Serial Link Using Wake-Up Function
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Protocol
➀ Select the 9-bit UART mode for master and slave
controllers.
➂ The master controller transmits one-frame data
including the 8-bit select code for the slave controllers. The MSB (bit 8) <TB8> is set to “1”.
➁ Set SC0MOD <WU>/SC1MOD <WU> bit of each
slave controller to “1” to enable data receiving.
➃ Each slave controller receives the above frame, and
clears WU bit to “0” if the above select code matches
its own select code.
➅ The other slave controllers (with the <WU> bit remaining at “1”) ignore the receiving data because their
MSBs (bit 8 or <RB8>) are set to “0” to disable the
interrupt INTRX0/INTRX1.
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➄ The master controller transmits data to the specified
slave controller whose SC0MOD <WU> / SC1MOD
<WU> bit is cleared to “0.” The MSB (bit 8) <TB8> is
cleared to “0”.
The slave controllers (WU = 0) can transmit data
to the master controller, and it is possible to indicate
the end of data receiving to the master controller by
this transmission.
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Setting Example:
the internal clock φ1 (fc/2) as the transfer clock.
To link two slave controllers serially
with the master controller, and use
Since serial channels 0 and 1 operate in exactly the
same
way, channel 0 is used for the purposes of explanation.
• Setting the master controller
Main setting
P6CRL
←
–
–
–
–
0
0
1
1
INTES0
←
1
1
0
0
1
1
0
1
Select P60 as TxD pin and P61 as RxD pin.
Enable INTTX0 and sets the interrupt level 4.
Enable INTRX0 and sets the interrupt level 5.
SC0MOD
←
1
0
1
0
1
1
1
0
Set φ1 (fc/2) as the transmission clock in 9-bit UART mode.
SC0BUF
←
0
0
0
0
0
0
0
1
Set the select code for slave controller 1.
INTTX0 interrupt
SC0MOD
←
–
0
–
–
–
–
–
–
Set TB8 to “0”.
SC0BUF
←
*
*
*
*
*
*
*
*
Set data for transmission.
–
–
–
0
1
Select P61 as RxD pin and P60 as TxD pin.
• Setting the slave controller 2
Main setting
P6CRL
←
x
x
–
ODE
←
x
x
x
x
x
x
–
1
INTES0
←
1
1
0
1
1
1
1
0
Enable INTRX0 and INTTX0.
SC0MOD
←
0
0
1
1
1
1
1
0
Set <WU> to “1” in the 9-bit UART transmission mode with transfer
clock φ1 (fc/2).
INTRX0 interrupt
Acc ← SC0BUF
If Acc = Select Code
Then SC0MOD4
134
←
–
–
–
0
–
–
–
–
Clear <WU> to “0”.
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TMP96C031N/F
3.11 Analog/Digital Converter
The TMP96C031F contains a high-speed analog/digital converter (A/D converter) with 4-channel analog input that features
10-bit successive approximation.
Figure 3.11 (1) shows the block diagram of the A/D converter. The 4-channel analog input pins (AN3 to AN0) are
shared by input-only P5 and so can be used as input port.
Figure 3.11 (1). Block Diagram of A/D Converter
Note1: This A/D converter does not have a built-in sample and hold circuit. Therefore, when A/D converting high-frequency signals, connect a sample and
hold circuit externally.
Note2: The lower the power supply current in IDLE or STOP mode, depending on the timing, standby mode can be entered with the internal comparator in
enable state. Thus, stop A/D conversion before executing the HALT instruction.
The ladder resistor between VREF- GND cannot be disconnected internally. Therefore, IREF will flow regardless of the mode.
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3.11.1 Control Register
Figure 3.11 (2). A/D Converter Mode Register (ADMOD)
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TMP96C031N/F
Figure 3.11 (3). Register for Saving an A/D Switch Value (ADREG0 ~ 3)
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3.11.1 Operation
(1)
Analog Reference Voltage
High analog reference voltage is applied to the VREF
pin.
The reference voltage between VREG and AGND is
divided by 256 using ladder resistance, and compared
with the analog input voltage for A/D conversion.
(2)
Starting A/D Conversion
A/D conversion starts when A/D conversion register
ADMOD <ADS> is written “1". When A/D conversion
starts, A/D conversion busy flag ADMOD <ADBF>
which indicates “A/D conversion is in progress” will be
set to “1".
(4)
A/D Conversion Mode
Both fixed A/D conversion channel mode and A/D conversion channel scan mode have two conversion
modes, i.e., single and repeat conversion modes.
In fixed channel repeat mode, conversion of specified
one channel is executed repeatedly.
In scan repeat mode, scanning from AN0, … → AN3 is
executed repeatedly.
A/D conversion mode is selected by ADMOD <REPET,
SCAN>.
138
A/D Conversion Speed Selection
There are two A/D conversion speed modes: high
speed mode and low speed mode. The selection is
executed by ADMOD <ADCS> register.
When reset, ADMOD <ADCS> will be initialized to “0,”
so that high speed conversion mode will be selected.
(6)
Analog Input Channels
Analog input channel is selected by ADMOD <ADCH1,
0>. However, in fixed analog input mode, one channel
is selected by ADMOD <ADCH1, 0> among four pins:
AN0 to AN3.
In analog input channel scan mode, the number of
channels to be scanned from AN0 is specified by
ADMOD <ADCH1, 0>, such as AN0 → AN1, AN0 →
AN1 → AN2, and AN0 → AN1 → AN2 → AN3.
When reset, A/D conversion channel register will be initialized to ADMOD <ADCH1, 0> = 00, so that AN0 pin
will be selected.
The pins which are not used as analog input channel
can be used as ordinary input port P5.
(3)
(5)
A/D Conversion End and Interrupt
• A/D conversion single mode
ADMOD <EOCF> for A/D conversion end will be set to
“1,” ADMOD <ADBF> flag will be reset to “0,” and
INTAD interrupt will be enabled when A/D conversion
of specified channel ends in fixed conversion channel
mode or when A/D conversion of the last channel ends
in channel scan mode.
(7)
Storing the A/D Conversion Result
The results of A/D conversion are stored in ADREG0 to
ADREG3 registers for each channel. In repeat mode,
the registers are updated whenever conversion ends.
ADREG0 to ADREG3 are read-only registers.
(8)
Reading the A/D Conversion Result
The results of A/D conversion are stored in ADREG0 to
ADREG3 registers. When the contents of one of
ADREG0 to ADREG3 registers are read, ADMOD
<EOCF> will be cleared to “0".
Setting example:
➀ When the analog input voltage of the AN3 pin is A/D
converted and the result is
stored in the memory
address FF10H by A/D
interrupt INTAD routine.
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TMP96C031N/F
Main setting
INTE0AD
←
1
1
0
0
x
x
x
x
Enable INTAD and sets interrupt level 4.
ADMOD
←
x
x
0
0
0
1
1
1
Specify AN3 pin as an analog input channel and starts
A/D conversion in high speed mode.
INTAD routine
←
A
ADREG3
The value of ADREG3 is read into the accumulator. Then the accumulator
value is stored into memory at FF10H.
(FF10H)
←
A
Setting example: ➁ When the analog pin voltage of
AN0 ~ AN2 pin is A/D converted in
high speed conversion channel scan repeat
mode.
INTE0AD
←
1
0
0
x
x
x
x
x
Disable INTAD.
ADMOD
←
x
x
1
1
0
1
1
0
Start the A/D conversion of analog input channels AN0 ~ AN2
in the high-speed scan repeat mode.
Note:
x; don’t care
–; no change
3.12 Watchdog Timer (Runaway Detecting Timer)
The TMP96C031F is containing watchdog timer of Runaway
detecting.
The watchdog timer (WDT) is used to return the CPU to
the normal state when it detects that the CPU has started to
malfunction (runaway) due to causes such as noise. When the
watchdog timer detects a malfunction, it generates a non-
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maskable interrupt to notify the CPU of the malfunction, and
outputs 0 externally from watchdog timer out pin WDTOUT to
notify the peripheral devices of the malfunction.
Connecting the watchdog timer output to the reset pin
internally forces a reset.
A built-in function is used to stop the WDT count at bus
release request (BUSRQ).
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3.12.1 Configuration
Figure 3.12 (1) shows the block diagram of the watchdog timer (WDT).
Figure 3.12 (1). Block Diagram of Watchdog Timer
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The watchdog timer is a 22-stage binary counter which
uses φ (fc/2) as the input clock. There are four outputs from the
binary counter: 216/fc, 218/fc, 220/fc, and 222/fc. Selecting one
of the outputs with the WDMOD register generates a watchdog interrupt, and outputs watchdog timer out when an overflow occurs.
Since the watchdog timer out pin (WDTOUT) outputs “0”
due to a watchdog timer overflow, the peripheral devices can
be reset.
Clearing the watchdog timer (by writing the clear code
(4EH) to the WDCR) after disabling it sets 0 to output to 1 (Program example).
LDW
(WDMOD), 0B100H
LD
SET
(WDCR), 4EH
7, (WDMOD)
; writes clear code
; enables watchdog
timer again.
In other words, the WDTOUT keeps outputting “0” until
the clear code is written.
The watchdog timer out pin can also be connected to the
reset pin internally. In this case, the watchdog timer out pin
(WDTOUT) outputs 0 at 8 to 20 states (800ns to 2.0µs @
20MHz) and resets itself.
The WDTOUT (also used as P67) is multiplexed with pin
PG13; setting must be done using the port 6 control register,
P6CRH (WDTOUT pin is set after reset).
; disables
watchdog timer
Figure 3.12 (2). Normal Mode
Figure 3.12 (3). Reset Mode
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TMP96C031N/F
3.12.2 Control Registers
Watchdog timer WDT is controlled by two control registers
WDMOD and WDCR.
(1)
To disable, it is necessary to clear this bit to “0” and
write the disable code (B1H) in the watchdog timer
control register WDCR. This makes it difficult for the
watchdog timer to be disabled by runaway.
However, it is possible to return from the disable state
to enable state by merely setting <WDTE> to “1".
Watchdog Timer Mode Register (WDMOD)
➀ Setting the detecting time of watchdog timer
<WDTP>
➂ Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the
watchdog timer with RESET terminal, internally. Since
WDMOD <RESCR> is initialized to 0 at reset, a reset
by the watchdog timer will not be performed.
This 2-bit register is used to set the watchdog timer
interrupt time for detecting the runaway. This register is
initialized to WDMOD <WDTP1, 0> = 00 when reset,
and therefore 216/fc is set. (The number of states is
approximately 32,768.)
(2)
Watchdog Timer Control Register (WDCR)
➁ Watchdog timer enable/disable control register
<WDTE>
This register is used to disable and clear the binary
counter of the watchdog timer function.
When reset, WDMOD <WDTE> is initialized to “1”
enable the watchdog timer.
• Disable control
WDMOD
←
0
–
–
–
–
–
x
x
Clear WDMOD <WDTE> to “0".
WDCR
←
1
0
1
1
0
0
0
1
Write the disable code (B1H).
• Enable control
• Watchdog timer clear control
Set WDMOD <WDTE> to “1".
WDCR
142
← 0
The binary counter can be cleared and resume counting by writing clear code (4EH) into the WDCR register.
1
0
0
1
1
1
0
Write the clear code (4EH).
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TMP96C031N/F
Figure 3.12 (4). Watchdog Timer Mode Register
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TMP96C031N/F
Figure 3.12 (5). Watchdog Timer Control Register
Figure 3.12 (6)
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TMP96C031N/F
3.12.3 Operation
The watchdog timer generates interrupt INTWD after the
detecting time set in the WDMOD <WDTP1, 0> register and
outputs a low level signal. The watchdog timer must be zerocleared by software before an INTWD interrupt is generated. If
the CPU malfunctions (runaway) due to causes such as noise,
but does not execute the instruction used to clear the binary
counter, the binary counter overflows and an INTWD interrupt
is generated. The CPU detects malfunction (runaway) due to
the INTWD Interrupt and it is possible to return to normal oper-
Example:
ation by an anti-malfunction program. By connecting the
watchdog timer out pin to peripheral devices’ resets, a CPU
malfunction can also be acknowledged to other devices.
The watchdog timer restarts operation immediately after
resetting is released.
The watchdog timer stops its operation in the IDLE and
STOP modes. In the RUN mode, the watchdog timer is
enabled.
However, the function can be disabled when entering the
RUN mode.
➀ Clear the binary counter
WDCR
←
0
1
0
0
1
1
1
0
Write clear code (4EH).
➁ Set the watchdog timer detecting time to 218/fc
WDMOD
←
1
0
1
–
–
–
x
x
➂ Disable the watchdog timer
WDMOD
←
0
–
–
–
–
–
x
x
Clear WDTE to “0".
WDCR
←
1
0
1
1
0
0
0
1
Write disable code (B1H).
Disables WDT and sets IDLE mode.
➃ Set IDLE mode
WDMOD
←
0
–
–
–
1
0
x
x
WDCR
←
1
0
1
1
0
0
0
1
Executes HALT command
Set the standby mode
➄ Set the STOP mode (warming up time: 216/fc)
WDMOD
←
–
–
–
1
0
1
Executes HALT command
2)
Writing 1 to the P4FC <BUSWDT> register halts count by
the WDT binary counter at bus release due to the bus
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x
x
Set the STOP mode.
Execute HALT instruction. Set the standby mode.
request signal, BUSRQ.
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3.13 Dynamic RAM (DRAM Controller
The TMP96C031F consists of a control circuit to refresh
DRAM, an access circuit to perform read/write, and an
address decoder.
Figure 3.13 (1) shows a block diagram of the DRAM controller.
Figure 3.13 (1). DRAM Controller
3.13.1 Control Register
Figure 3.13 (2). Chip Select Wait Control Register (B3CS)
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TMP96C031N/F
Figure 3.13 (3). Port 4 Function Register
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TMP96C031N/F
Figure 3.13 (4). Refresh Control Register
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TMP96C031N/F
3.13.2 Operation Description
(1)
Read/Write Control
The read/write controller outputs valid signals RAS and
CAS to DRAM when address space specified by the
internal address decoder (chip select 2 CS3/CAS) is
accessed.
In addition, a DMUX signal is output for row address/
column address switching.
Figure 3.13 (6) shows the RAS, CAS, and DMUX output timing diagram during memory access cycle.
Figure 3.13 (5). Memory Access Cycle Timing
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TMP96C031N/F
How to set the registers is described next.
➀ Setting the RAS, CAS, DMUX, and RFSH output
Figure 3.13 (2) shoes the structure of the chip select
wait control register B3CS. B3CS <B3E> can be used to
control the output of CS3/CAS and B3CS <B3CAS> can
be used to control CAS selection.
Figure 3.13 (6). Relationship Between Address Decoder and DRAM Controller
The RAS, CAS, DMUX, and RFSH signals must be
set with the corresponding port control register because
they are multiplexed with P35, P43, P71, and P63
respectively.
150
➁ Inserting WAIT
WAIT insertion during read/write control can be set
with the register B3CS <B3W1, 0>.
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TMP96C031N/F
(2)
Refresh Controller
• Refresh cycle is asynchronous with CPU operation
cycle.
The TMP96C031F can output RAS/CAS used to
refresh in DRAM. At the same time the state signal
RFSH which indicates a refresh cycle is output.
DRAM can be refreshed easily because RAS/CAS output frequency and pulse width are programmable.
The refresh controller has the following features.
• Refresh mode:
CAS before RAS interval refresh
mode
CAS before RAS self refresh mode
• Refresh interval: 15 to 154 states (programmable)
i) CAS before RAS interval refresh mode
The refresh interval and refresh width for CAS before
RAS interval refresh mode depends on the DRAM
being used.
Therefore, TMP96C031F enables the CAS before RAS
output to be set with the refresh controller register
value according to the system clock and DRAM that
are being used.
Figure 3.13 (2) shows a timing example for CAS before
RAS refresh cycle.
• Refresh cycle width: 2 to 9 states (programmable)
• Dummy cycle can be generated
Figure 3.13 (7). Refresh Cycle Timing Example
How to set the register is described next.
Figure 3.13 (4) shows the bit structure of the refresh control register DREFCR.
The insertion interval is set with the three bits DREFCR
<RS2 to 0> according to the system clock being used.
Example:
➀ Refresh cycle insertion interval
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When the system clock is 20MHz and the
DRAM refresh cycle is to be 16µs, set these
bits to “111”.
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TMP96C031N/F
Table 3.13 Refresh Cycle Insertion Interval
➁ The three bits DREFCR <RW2 to 0> can used to
change the refresh cycle width (RAS, CAS output). (2
to 9 states)
➂ Refresh cycle control
The refresh cycle can be disabled/enable with the bit
DREFCR <RC>.
This mode is used when CPU or DRAM control is
halted with a HALT (IDEL, STOP) instruction while
refreshing with CAS before RAS interval refresh mode
(hereafter referred to as interval mode).
However, RFSH is not output. (“1” is output.).
Figure 3.13 (8) shows the self refresh mode timing diagram.
ii) CAS before RAS self refresh mode
Figure 3.13 (8). Self Refresh Cycle Timing
This mode is executed as follows. First, the settings are
made for normal interval mode Then, B3CS <SRFC> is
set to “0” just before a HALT instruction to perform one
normal refresh. Then, the CAS pin and RAS pin are
kept at low level and self refresh mode is entered. Set
152
B3CS <SRFC> to “1” to cancel this mode and return
to normal CAS before RAS refresh mode. (The first
CAS before RAS refresh is performed immediately after
cancellation because the refresh counter is cleared.)
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TMP96C031N/F
(3)
DRAM initialize
The DRAM controller can generate consecutive CAS
before RAS dummy cycles necessary when using
DRAM. This is executed by setting DREFCR <DMI> bit
to “1” and cancelled by setting it to “0”. (The <RC> bit
need not be changed.)
The dummy cycle width is fixed to 4 states.
Figure 3.13 (9) shows the CAS before RAS dummy
cycle timing.
Figure 3.13 (9). CAS before RAS Dummy Cycle Timing (Fixed to 4 states)
3.13.4 Priority
The DRAM refresh cycle may overlap with the DRAM read/
write cycle because it is not synchronized with the CPU operating cycle. In this case, the DRAM controller gives priority to
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the cycle that starts operation first. If the priority is given to the
refresh cycle, a wait is automatically inserted in the memory
access cycle. Figure 3.13 (8) shows the timing in this case.
153
TMP96C031N/F
Figure 3.13 (101). Timing Diagram when Refresh Cycle is Inserted in Memory Access Cycle
154
TOSHIBA CORPORATION
TMP96C031N/F
3.13.4 Connection Example
TOSHIBA CORPORATION
155
TMP96C031N/F
4.
Electrical Characteristics
4.1 Absolute Maximum (TMP96C031F)
Symbol
156
Parameter
Rating
Unit
Vcc
Power Supply Voltage
-0.5 ~ 6.5
V
V IN
Input Voltage
-0.5 ~ Vcc + 0.5
V
Σ IOL
Output Current (total)
100
Σ IOH
mA
Output Current (total)
-100
mA
PD
Power Dissipation (Ta = 70°C)
600
mW
T SOLDER
Soldering Temperature (10s)
260
°C
T STG
Storage Temperature
-65 ~ 150
°C
T OPR
Operating Temperature
-20 ~ 70
°C
TOSHIBA CORPORATION
TMP96C031N/F
4.2 DC Characteristics (TMP96C031F)
Vcc = 5V ± 10%, Ta = -20 ~ 70°C (Typical values are for Ta = 25°C and Vcc = 5V)
Symbol
Parameter
Min
Max
Unit
-0.3
0.8
V
Test Condition
V IL
Input Low Voltage (AD0-15)
V IL1
P2, P3, P4, P5, P6, P7, P8, P9
-0.3
0.3Vcc
V
V IL2
RESET, NMI, INTO (P87)
-0.3
0.25Vcc
V
V IL3
AM8/EA
-0.3
0.3
V
V IL4
X1
-0.3
0.2Vcc
V
V IH
Input High Voltage (AD0-15)
2.2
Vcc + 0.3
V
V IH1
P2, P3, P4, P5, P6, P7, P8, P9
0.7Vcc
Vcc + 0.3
V
V IH2
RESET, NMI, INTO (P87)
0.75Vcc
Vcc + 0.3
V
V IH3
EA
Vcc - 0.3
Vcc + 0.3
V
V IH4
X1
0.8Vcc
Vcc + 0.3
V
V OL
Output Low Voltage
0.45
V
I OL = 1.6mA
V OH
Output High Voltage
2.4
V
I OH = -400µA
V OH1
0.75Vcc
V
I OH = -100µA
V OH2
0.9Vcc
V
I OH = - 20µA
-3.5
mA
V EXT - 1.5V
R EXT = 1.1KΩ
I DAR
Darlington Drive Current
(8 Output Pins max.)
I LI
Input Leakage Current
0.02 (Typ)
±5
µA
0.0 ≤ Vin ≤ Vcc
I LO
Output Leakage Current
0.05 (Typ)
±10
µA
0.2 ≤ Vin ≤ Vcc - 0.2
30 (Typ)
2.0 (Typ)
0.2 (Typ)
60
10
50
10
mA
mA
µA
µA
tosc = 20MHz
I cc
Operating Current (RUN)
IDLE
STOP (Ta = -20 ~ 70°C)
STOP (Ta = 0 ~ 50°C)
V STOP
Power Down Voltage
(@STOP, RAM Back up)
2.0
6.0
V
R RST
RESET Pull Up Register
50
150
KΩ
C IO
Pin Capacitance
10
pF
V TH
Schmitt Width
RESET, NMI, INTO (P50)
0.4
1.0 (Typ)
V
RK
Pull Down/Up Register
50
150
KΩ
Note:
-1.0
0.2 ≤ Vin ≤ Vcc - 0.2
0.2 ≤ Vin ≤ Vcc - 0.2
V IL2 = 0.2Vcc,
V IH2 = 0.8Vcc
tosc = 1MHz
I-DAR is guaranteed for a total of up to 8 ports.
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157
TMP96C031N/F
4.3 AC Electrical Characteristics (TMP96C031F) Vcc = 5V±10%, Ta = -20 ~ 70°C (4MHz ~ 20MHz)
Variable
No.
Symbol
16MHz
20MHz
Parameter
Unit
Min
1
tOSC
Osc. Period (= x)
50
Max
250
2x - 40
Min
Max
Min
Max
62.5
50
ns
2
tCLK
CLK width
85
60.0
ns
3
tAK
A0 - 23 Valid→CLK Hold
0.5x - 20
11.0
50
ns
4
tKA
CLK Valid→A0 - 23 Hold
1.5x - 70
240
50
ns
5
tAL
A0-15 Valid→ALE fall
0.5x - 15
160
100
ns
6
tLA
ALE fall→A0 - 15 Hold
0.5x - 15
160
100
ns
7
tLL
ALE High width
x - 40
23.0
100
ns
8
tLC
ALE fall→RD/WR fall
0.5x - 30
1.0
-5
ns
9
tCL
RD/WR rise→ALE rise
0.5x - 20
11.0
50
ns
10
tACL
A0 - 15 Valid→RD/WR fall
x - 25
38.0
250
ns
11
tACH
A0 - 23 Valid→RD/WR fall
1.5x - 50
44.0
25.0
ns
12
tCA
RD/WR rise→A0 - 23 Hold
0.5x - 20
11.0
5
ns
13
tADL
A0 - 15 Valid→D0 - 15 input
3.0x - 45
143
105
ns
14
tADH
A0 - 23 Valid→D0 - 15 input
3.5x - 65
154
110
ns
15
tRD
RD fall→D0 - 15 input
2.0x - 50
75
50
ns
16
tRR
RD Low width
17
tHR
RD rise→D0 - 15 Hold
18
tRAE
RD rise→A0 - 15 output
19
tWW
WR Low width
2.0x - 40
85.0
60.0
ns
20
tDW
D0 - 15 Valid→WR rise
2.0x - 50
75.0
50.0
ns
21
tWD
WR rise→D0 - 15 Hold
0.5x - 10
21.0
15.0
ns
22
tAEH
A0 - 23 Valid→WAIT input (1WAIT + n mode)
3.5x - 90
129
85
ns
23
tAWL
A0 - 15 Valid→WAIT input (1WAIT + n mode)
3.0x - 80
108
70
ns
24
tCW
RD/WR fall→WAIT Hold (1WAIT + n mode)
25
tAPH
A0 - 23 Valid→PORT input
26
tAPH2
A0 - 23 Valid→PORT Hold
27
tCP
WR rise→PORT Valid
AC Measuring Conditions
• Output Level:
High 2.2V
(However CL = 100pF for AD0 ~
• Input Level:
High 2.4V
High 0.8Vcc
158
2.0x - 40
0
x - 15
2.0x + 0
85.0
60.0
ns
0.0
0.0
ns
48.0
35.0
ns
125.0
2.5x - 120
2.5x + 50
100.0
36
206.0
200
ns
5
175.0
200
ns
ns
200
ns
/Low 0.8V, CL50pF
AD15, AD0 ~ AD23, ALE, RD, WR, HWR, CLK, CS0 ~ CS3)
/Low 0.45V (AD0 ~ AD15)
/Low 0.2Vcc (Except for AD0 ~ AD15)
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TMP96C031N/F
(1) Read Cycle
TOSHIBA CORPORATION
159
TMP96C031N/F
(2) Write Cycle
160
TOSHIBA CORPORATION
TMP96C031N/F
4.4 DRAM Control AC Characteristics (TMP96C031F)
Vcc = 5V±10% TA = -20 ~ 70°C (4MHz ~ 20MHz)
Variable
No.
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
4x - 10
Min
Max
240
Min
Max
1
tRC
RAS cycle time
2
tRAC
RAS fall → data input
3
tCAC
CAS fall → data input
4
tRP
RAS high pulse width
2x - 30
95
70
ns
5
tRAS
RAS low pulse width
2x - 10
115
90
ns
6
tRSH
CAS fall → RAS rise
1x - 25
38
25
ns
7
tCSH
RAS fall → CAS rise
2x - 20
105
80
ns
2x - 20
190
105
1x - 25
38
ns
80
ns
25
ns
8
tCAS
CAS low pulse width
1.5x - 10
84
65
ns
9
tRCD
RAS fall → CAS fall
1x - 15
48
35
ns
10
tCRP
CAS rise → RAS rise
1.5x - 50
44
25
ns
11
tRAH
RAS fall → A0 - 15 hold
0
0
0
ns
12
tASRL
A0 - 15 valid → RAS fall
1x - 10
53
40
ns
13
tASRH
A0 - 23valid → RAS fall
1.5x - 10
84
65
ns
14
tRWL
WR fall → RAS rise
2x - 50
75
50
ns
15
tCWL
WR fall → CAS rise
2x - 50
75
50
ns
16
tDS
Data output → CAS fall setup
1x - 30
33
20
ns
17
tDH
CAS fall → data output hold
1.5x - 50
44
25
ns
18
tDHR
RAS fall → data output hold
2.5x - 50
106
75
ns
19
tWCS
WR fall → CAS fall setup
1x - 30
33
20
ns
20
tWCH
CAS fall → WR hold
1x - 30
33
20
ns
21
tRDM
RAS fall → DMUX fall
21
15
ns
0.5x - 10
22
tCDM
DMUX fall → CAS fall
0.5x - 10
21
15
ns
23
tCHR*1
RAS fall → CAS rise
2x - 50
75
50
ns
24
tRPC*
RAS rise → CAS fall
1.5x + 0
64
45
ns
25
tCP*
CAS high pulse width
1.5x + 0
64
45
ns
26
tCSR*
CAS fall → RAS fall
0.5x - 10
21
15
ns
27
tRASS*2
RAS low pulse width
2000x
125
100
ns
28
tRPS*2
RAS precharge time
4x - 20
29
tCHS*2
CAS hold time
30
tCFL*
RFSH fall → CAS fall
31
tCFH*
CAS rise → RFSH rise
230
180
ns
0
0
0
ns
1x - 10
53
40
ns
0.5x - 10
21
15
ns
*1 CAS before RAS interval refresh mode
*2 CAS before RAS self-refresh mode
* Both refresh modes
AC Measuring Conditions
• Output Level:
High 2.2V
/Low 0.8V, CL50pF
(However CL = 100pF for AD0 ~ AD15, AD0 ~ AD23, RD, WR, HWR, R/W RAS)
• Input Level:
High 2.4V
/Low 0.45V (AD0 ~ AD15)
High 0.8Vcc/Low 0.2Vcc (Except for AD0 ~ AD15)
TOSHIBA CORPORATION
161
TMP96C031N/F
(1) Read/Write Access Cycle
(2) CAS before RAS Interval Refresh Cycle
(3) CAS before RAS Self-Refresh Cycle
162
TOSHIBA CORPORATION
TMP96C031N/F
4.5 A/D Conversion Characteristics (TMP96C031F)
Vcc = 5V±10% TA = -20 ~ 70°C
Symbol
Parameter
Min
Typ
Max
VREF
Analog reference voltage
Vcc - 1.5
Vcc
AGND
Analog reference voltage
Vss
Vss
VAIN
Analog input voltage range
Vss
Vcc
IREF
Analog current for analog reference voltage
0.5
Error
Total error
(Quantize error of
(TA = 25°C, VCC = VREF = 5.0V)
±0.5 LSB not included) Total error
Unit
V
1.5
mA
1.0
LSB
2.5
4.6 Serial Channel Timing - I/O Interface Mode
Vcc = 5V±10% TA = -20 ~ 70°C
(1) SCLK Input Mode
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
tSCY
SCLK cycle
Max
Min
Max
Min
Max
16x
1
0.8
µs
tOSS
Output Data→rising edge of SCLK
tSCY/2 - 5x - 50
137
100
ns
tOHS
SCLK rising edge→output data hold
5x - 100
212
150
ns
tHSR
SCLK rising edge→input data hold
0
0
0
ns
tSRD
SCLK rising edge→effective data input
tSCY - 5x - 100
587
450
ns
(2) SCLK Output Mode
Variable
Symbol
16MHz
20MHz
Parameter
tSCY
SCLK cycle (programmable)
Unit
Min
Max
Min
Max
Min
Max
16x
8192x
1
512
0.8
409.6
µs
tOSS
Output Data→rising edge of SCLK
tSCY - 2x - 150
725
550
ns
tOHS
SCLK rising edge→output data hold
2x - 80
45
20
ns
tHSR
SCLK rising edge→input data hold
0
0
0
ns
tSRD
SCLK rising edge→effective data input
tSCY - 2x - 150
725
550
ns
4.7 Timer/Counter Input Clock (TI0, TI4, TI5)
Vcc = 5V±10% TA = -20 ~ 70°C
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
Clock cycle
8x + 100
600
500
ns
tVCKL
Low level clock pulse width
4x + 40
290
240
ns
tVCKH
High level clock pulse width
4x + 40
290
240
ns
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163
TMP96C031N/F
4.8 Interrupt Operation
Vcc = 5V±10% Ta = -20 ~ 70°C
Variable
Symbol
20MHz
Unit
Min
164
16MHz
Parameter
Max
Min
Max
Min
Max
tINTAL
NMI, INT0 Low level pulse width
4x
250
200
ns
tINTAH
NMI, INT0 High level pulse width
4x
250
200
ns
tINTBL
INT1 ~ INT7 Low level pulse width
8x + 100
600
500
ns
tINTBH
INT1 ~ INT7 High level pulse width
8x + 100
600
500
ns
TOSHIBA CORPORATION
TMP96C031N/F
4.9 Timing Chart for I/O Interface Mode
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165
TMP96C031N/F
4.10 Timing Chart for Bus Request/BUS Acknowledge
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
Max
120
Min
Max
tBRC
BUSRQ setup time for CLK
tCBAL
CLK→BUSAK falling edge
1.5x + 120
214
220
ns
tCBAH
CLK→BUSAK rising edge
0.5x + 40
71
65
ns
tABA
Output buffer is off to BUSAK
0
80
0
80
0
80
ns
tBAA
BUSAK
0
80
0
80
0
80
ns
output buffer is on.
120
Min
120
ns
Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “Wait” cycle.
Note 2: An internal programmable pull-down resistor must be connected.
Note 3: An internal programmable pull-up resistor must be connected.
166
TOSHIBA CORPORATION
TMP96C031N/F
5.
Table of Special Function Registers
(SFR; Special Function Register)
The special function registers (SFRs) include the I/O ports and
peripheral control registers allocated to the 128-byte
addresses from 000000H to 00007FH.
(1) I/O port
(2) I/O port control
(3) Timer control
(4) Pattern Generator control
(5) Watch Dog Timer control
(6) Serial Channel control
(7) A/D converter control
(8) Interrupt control
(9) Chip Select/Wait Control
(10) DRAM Control
Configuration of the table
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167
TMP96C031N/F
Table 5 I/O Register Address Map
Address
000000H
168
Name
Address
Name
Address
Name
Address
20H TRUN
40H MSAR0
60H ADREG0
1H
21H
41H MAMR0
61H ADREG1
2H
22H TREG0
42H MSAR1
62H ADREG2
3H
23H TREG1
43H MAMR1
63H ADREG3
4H
24H T01TMOD
44H MSAR2
64H
5H
25H TFFCR
45H MAMR2
65H
6H P2
26H TREG2
46H MSAR3
66H
7H P3
27H TREG3
47H MAMR3
67H
8H P2CR
28H T23MOD
48H
68H
9H P2FC
29H TRDC
49H
69H B0CS
AH P3CRL
2AH
4AH
6AH B1CS
BH P3CRH
2BH
4BH DREFCR
6BH B2CS
CH P4
2CH
4CH PG0REG
6CH B3CS
DH P5
2DH
4DH PG1REG
6DH
EH
2EH
4EH PG01CR
6EH
FH
2FH
4FH
6FH
10H P4FC
30H TREG4L
50H SC0BUF
70H INTE01
11H
31H TREG4H
51H SC0CR
71H INTE23
12H P6
32H TREG5L
52H SC0MOD
72H INTE45
13H P7
33H TREG5H
53H BR0CR
73H INTE67
14H P6CRL
34H CAP1L
54H SC1BUF
74H INTET10
15H P7CRL
35H CAP1H
55H SC1CR
75H INTET32
16H P6CRH
36H CAP2L
56H SC1MOD
76H INTET54
17H P7CRH
37H CAP2H
57H BR1CR
77H INTES0
18H
38H T4MOD
58H ODE
78H INTES1
19H
39H TFF4CR
59H
79H INTEAD
1AH
3AH T45CR
5AH
7AH IIMC0
1BH
3BH
5BH
7BH IIMC1
1CH
3CH
5CH WDMOD
7CH DMA0V
1DH
3DH
5DH WDCR
7DH DMA1V
1EH
3EH
5EH ADMOD
7EH DMA2V
1FH
3FH
5FH
7FH DMA3V
Name
TOSHIBA CORPORATION
TMP96C031N/F
(1) I/O Port
Symbol
P2
Name
PORT2
Address
7
6
5
4
P27
P26
P25
P24
PORT3
2
1
0
P23
P22
P21
P20
R/W
06H
Input mode
0
P3
3
0
0
0
0
0
0
0
P35
P34
P33
P32
P31
P30
1
1
1
1
1
1
P41
P40
1
1
P51
P50
R/W
07H
Input mode (Pulled-up)
P43
P4
PORT4
P42
R/W
0CH
1
0
P53
P52
Output mode
P5
PORT5
R
0DH
Input mode
P6
PORT6
P67
P66
P65
P64
1
1
1
1
P63
P62
P61
P60
1
1
1
1
P73
P72
P71
P70
1
1
1
R/W
12H
Input mode
P76
P7
PORT7
P75
P74
R/W
13H
1
1
1
1
Input mode
Read/Write
R/W
R
W
Prohibit RWM
TOSHIBA CORPORATION
;
;
;
;
Either read or write is possible
Only read is possible
Only write is possible
Prohibit Read Modify Write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF Instruction)
169
TMP96C031N/F
(2) I/O Port Control (1/2)
Symbol
P2CR
P2FC
Name
PORT2
Control
PORT2
Function
Address
7
6
5
4
3
2
1
0
P27C
P26C
P25C
P24C
P23C
P22C
P21C
P20C
0
0
0
0
P23F
P22F
P21F
P20F
0
0
0
0
P30C1
P30C0
0
0
08H
(Prohibit
RMW)
W
0
PORT3
Control
Low
P4FC
170
PORT3
Control
High
PORT4
Function
0
P27F
P26F
P25F
P24F
0
0
0
0
09H
(Prohibit
RMW)
W
P2FC/ P2CR = 00 : IN, 01 : OUT, 10 : –, 11 : A23 - 16
P33C0
P32C1
0AH
(Prohibit
RMW)
0BH
0
0
0
00 : PORT input
01 : PORT output
10 : BUSRQ
11 : –
00 : PORT input
01 : PORT output
10 : BUSAK
11 : –
P31C1
P31C0
0
0
0
00 : PORT input
01 : PORT output
10 : TO5
11 : HWR
00 : PORT input
01 : PORT output
10 : –
11 : –
P35C1
P35C0
0
0
W
P34C1
P34C0
0
0
W
0
(Prohibit
RMW)
P32C0
W
RDEN
P3CRH
0
<<Refer to the “P2FC”>>
P33C1
P3CRL
0
1 : pseudo
SRAM
EN
00 : PORT input
01 : PORT output
10 : NMI
11 : R/W
00 : PORT input
01 : PORT output
10 : RAS
11 : –
BUSWDT
BUDRM
10H
W
W
(Prohibit
RMW)
0
0
00 : BUSSRQ 0 : ON
1 : OFF
DIS
01 : BUSRQ
EN
P43F
P42F
P41F
P40F
0
0
W
0
00 : PORT
01 : CS3/CAS
0
00 : PORT
01 : CS2
00 : PORT
01 : CS1
00 : PORT
01 : CS0
TOSHIBA CORPORATION
TMP96C031N/F
I/O Port Control (2/2)
Symbol
P6CRL
P6CRH
P7CRL
P7CRH
Name
PORT6
Control
Low
PORT6
Control
High
PORT7
Control
Low
PORT7
Control
High
Address
7
6
5
P63C1
P63C0
P62C1
14H
(Prohibit
RMW)
2
1
0
P62C0
P61C1
P61C0
P60C1
P60C0
0
0
0
0
0
0
0
0
00 : PORT input
01 : PORT output
10 : PG03
11 : RFSH
00 : PORT input
01 : PORT output
10 : PG02
11 : –
00 : PORT input
01 : PORT output
10 : PG01
11 : –
00 : PORT input
01 : PORT output
10 : PG00
11 : TxD0
P67C1
P67C0
P66C1
P66C0
P65C1
P65C0
P64C1
P64C0
0
0
0
0
0
0
0
0
W
00 : PORT input
01 : PORT output
10 : PG13
11 : WDTOUT
00 : PORT input
01 : PORT output
10 : PG12
11 : –
00 : PORT input
01 : PORT output
10 :PG11
11 : –
00 : PORT input
01 : PORT output
10 : PG10
11 : –
P73C1
P72C1
P72C0
P71C1
P71C0
P70C1
P70C0
0
0
0
0
0
P73C0
16H
(Prohibit
RMW)
3
W
15H
(Prohibit
RMW)
4
W
0
00 : PORT input
01 : PORT output
10 : –
11 : –
0
0
00 : PORT input
01 : PORT output
10 : –
11 : –
00 : PORT input
01 : PORT output
10 : TO3
11 : DMUX
00 : PORT input
01 : PORT output
10 : TO1
11 : TO4
P76C1
P76C0
P75C1
P75C0
P74C1
P74C0
0
0
0
0
0
0
17H
(Prohibit
RMW)
TOSHIBA CORPORATION
W
00 : PORT input
01 : PORT output
10 : SCLK1
11 : –
00 : PORT input
01 : PORT output
10 : –
11 : –
00 : PORT input
01 : PORT output
10 : TxD1
11 : –
171
TMP96C031N/F
(3) Timer Control (1/3)
Symbol
Name
Address
7
6
5
4
3
2
1
0
T5RUN
T4RUN
P1RUN
P0RUN
T1RUN
T0RUN
0
0
0
T1CLK1
T1CLK0
T0CLK1
T0CLK0
0
0
0
R/W
TRUN
TREG0
TREG1
T01TMOD
Timer RUN
Control
Reg.
0
22H
(Prohibit
RMW)
8bit Timer
Register 1
23H
(Prohibit
RMW)
24H
(Prohibit
RMW)
–
W
Undefined
–
W
Undefined
T10M1
T10M0
PWMM1
PWMM0
0
0
0
0
0
00 : –
01 : 26 - 1
10 : 27 - 1
11 : 28 - 1
PWM
Cycle
00 : TO0TRG
01 : φT1
10 : φT16
11 : φT256
W
00 : 8-bit Timer
01 : 16-bit Timer
10 : 8-bit PPG
11 : 8-bit PWM
TFF3C1
TFF3C0
TFF3IE
W
TFFCR
8bit Timer
Flip-flop
Control
TREG2
PWM Timer
Register 2
0
Prescaler and Timer Run/Stop CONTROL
0 : Stop and Clear
1 : Run (Count up)
8bit Timer
Register 0
8bit Timer
Source CLK
and MODE
0
20H
–
25H
TFF3IS
TFF1C1
R/W
0
1 : TFF3
Invert
Enable
00 : Invert TFF3
01 : Set TFF3
10 : Clear TFF3
11 : Don’t care
00 : TI0 Input
01 : φT1
10 : φT4
11: φT16
TFF1C0
TFF1IE
W
0
–
0 : Timer 2
1 : Timer 3
TFF1IS
R/W
0
1 : TFF1
Invert
Enable
00 : Invert TFF1
01 : Set TFF1
10 : Clear TFF1
11 : Don’t care
0
0 : Timer 0
1 : Timer 1
–
26H
W
Undefined
–
TREG3
PWM Timer
Register 3
27H
W
Undefined
T23M1
T23M0
PWM21
PWM20
T3CLK1
T3CLK0
T2CLK0
T2CLK0
0
0
0
0
0
0
0
0
00 : –
01 : 26 - 1
10 : 27 - 1
11 : 28 - 1
PWM
Cycle
00 : TO2TRG
01 : φT1
10 : φT16
11 : φT256
R/W
T23MOD
Timer 2, 3
Hode Reg.
28H
(Prohibit
RMW)
00 : 8-bit Timer
01 : 16-bit Timer
10 : 8-bit PPG
11 : 8-bit PWM
00 : TI0 Input
01 : φT1
10 : φT4
11: φT16
TR2DE
TR0DE
R/W
TRDC
172
Timer Reg.
Double Buffer
Control Reg.
0
29H
0
Tmer Reg.
Double Buffer Control
0 : Double Buffer Disable
1 : Double Buffer Enable
TOSHIBA CORPORATION
TMP96C031N/F
(3) Timer Control (2/3)
Symbol
Name
Address
TREG4L
16bit Timer
Register 4L
30H
(Prohibit
RMW)
16bit Timer
Register 4H
31H
(Prohibit
RMW)
16bit Timer
Register 5L
32H
(Prohibit
RMW)
16bit Timer
Register 5H
33H
(Prohibit
RMW)
TREG4H
TREG5L
TREG5H
7
6
5
4
3
2
1
0
CLE
T4CLK1
T4CLK0
0
0
0
–
W
Undefined
–
W
Undefined
–
W
Undefined
–
W
Undefined
–
CAP1L
Capture
Register 1L
34H
R
Undefined
–
CAP1H
Capture
Register 1H
35H
R
Undefined
–
CAP2L
Capture
Register 2L
36H
R
Undefined
–
CAP2H
Capture
Register 2H
37H
R
Undefined
CAP2T5
EQ5T5
R/W
T4MOD
16bit Timer 4
Source
CLK and
MODE
0
38H
TOSHIBA CORPORATION
TFF5 INV TRG
O : TRG Disable
1: TRG Enable
CAP1IN
CAP12M1
CAP12M0
W
0
0
0 : SoftCapture
1 : Don’t care
R/W
0
0
Capture Timing
00 : Disable
01 : T14 ↑ TI5 ↑
10 : T14 ↑ T14 ↑
11 : TFF1 ↑ TFF1 ↓
1 : UC4
Clear
Enable
Source Clock
00 : TI4
01 : φT1
10 : φT4
11 : φT16
173
TMP96C031N/F
(3) Timer Control (3/3)
Symbol
T4FFCR
Name
16bit Timer 4
Flip-flop
Control
Address
7
6
5
4
3
2
1
0
TFF5C1
TFF5C0
CAP2T4
CAP1T4
EQ5T4
EQ4T4
TFF4C1
TFF4C0
W
39H
R/W
0
0
0
W
0
0
0
0
TFF4 Invert Trigger
0 : Trigger Disable
1 : Trigger Enable
00 : Invert TFF5
01 : Set TFF5
10 : Clear TFF5
11 : Don’t care
–
PG1T
PG0T
R/W
T45CR
T4, T5 Control
0
Source Clock
00 : Invert TFF4
01 : Set TFF4
10 : Clear TFF4
11 : Don’t care
DB4EN
R/W
0
0
0
Fix at “0”
PG1 shift
trigger
0 : Timer 0, 1
1 : Timer 4
PG0 shift
trigger
O : Timer 2,3
1 : Timer 4
3AH
0
1 : Double
Buffer
Enable
(4) Pattern Generator
Symbol
PG0REG
PG1REG
Name
Address
7
6
5
4
3
2
1
0
PG03
PG02
PG01
PG00
SA03
SA02
SA01
SA00
PGO Register
4CH
(Prohibit
RMW)
0
0
0
0
4DH
(Prohibit
RMW)
PG13
PG12
PG11
PG10
SA11
SA10
PG1 Register
W
R/W
Undefined
SA13
SA12
W
R/W
0
0
0
0
PAT1
CCW1
PG1M
PG1TE
Undefined
0
0
0
0
PAT0
CCW0
PG0M
PG0TE
0
0
0
0
R/W
PG01CR
PG0, 1 Control
4EH
0 : Normal
0 : 8-bit write
Rotation
1 : 4-bit write 1 : Reverse
Rotation
PG1 trigger
0 : 4-bit Step input
1 : 8-bit Step enable
1 : Enable
0 : Normal
0 : 8-bit write
Rotation
1 : 4-bit write 1 : Reverse
Rotation
PG0 trigger
0 : 4-bit Step input
1 : 8-bit Step enable
1 : Enable
(5) Watch Dog Timer
Symbol
Name
Address
7
6
5
4
3
2
1
0
WDTE
WDTP1
WDTP0
WARM
HALTM1
HALTM0
RESCR
DRVE
1
0
0
0
0
0
0
0
R/W
WDMOD
Watch Dog
Timer Mode
5CH
1 : WDT
Enable
WDCR
174
Watch Dog
Timer
Control
Register
00 : 216/fc
01 : 218/fc
10 : 220/fc
11 : 222/fc
Standby Mode
00 : RUN Mode
01 : STOP Mode
10 : IDLE Mode
11 : Don’t care
Warming up
Time
0 : 214/fc
1 : 216/fc
1 : Connect
internally
WDT out
pin to
Reset Pin
1 : Drive
the pin
in STOP
Mode
–
5DH
W
Undefined
B1H : WDT Disable Code
4EH : WDT Clear Code
TOSHIBA CORPORATION
TMP96C031N/F
(6) Serial Channel (1/2)
Symbol
Name
SC0BUF
Serial
Channel 0
Buffer
Address
7
6
5
4
3
2
1
0
RB7
TB7
RB6
TB6
RB5
TB5
RB4
TB4
RB3
TB3
RB2
TB2
RB1
TB1
RB0
TB0
FERR
–
–
50H
R (Receiving)/W (Transmission)
Undefined
RB8
SC0CR
Serial
Channel 0
Control
EVEN
R
Receiving
data bit 8
OERR
0
0
R/W
0
51H
PE
Parity
0 : Odd
1 : Even
PERR
R (Cleared to 0 by reading)
1 : Parity
Enable
0
R/W
0
0
0
1 : Error
Fix at “0”
Fix at “0”
SM0
SC1
SC0
0
0
0
Overrun
Parity
Framing
SM1
0
TB8
CTSE
RXE
WU
0
0
0
0
R/W
SC0MOD
Serial
Channel 0
Mode
52H
Transmission 1 : CTS
data bit 8
Enable
1 : Receive
Enable
1 : Wake up
Enable
BR0CK1
BR0CK0
–
00 : Unused
01 : UART 7-bit
10 : UART 8-bit
11 : UART 9-bit
BR053
R/W
BR0CR
Baud Rate
Control
0
0
53H
SC1BUF
RB7
TB7
BR052
BR051
BR050
0
0
0
R/W
0
0
00 : φt0 (fc/4)
01 : φt2 (fc/16)
10 : φt8 (fc/64)
11 : φt32 (fc/256)
Fix at “0”
Serial
Channel 1
Buffer
00 : TO0 Trigger
01 : Baud rate generator
10 : Internal clock φ1
11 : Don’t care
RB6
TB6
RB5
TB5
54H
Set frequency divisor
0~F
(“1” prohibited)
RB4
TB4
RB3
TB3
RB2
TB2
RB1
TB1
FERR
SCLKS
RB0
TB0
R (Receiving)/W (Transmission)
Undefined
RB8
EVEN
R
0
SC1CR
Serial
Channel 1
Control
PE
OERR
R/W
PERR
R (Cleared to 0 by reading)
0
0
0
IOC
R/W
0
0
0
1 : Error
55H
Receiving
data bit 8
TB8
Parity
0 : Odd
1 : Even
–
1 : Parity
Enable
RXE
Overrun
WU
1 : Input
SCLK1 pin
Parity
Framing
SM1
SM0
SC1
SC0
0
0
0
0
R/W
SC1MOD
Serial
Channel 1
Mode
0
0
0
0
56H
TOSHIBA CORPORATION
Transmission
data bit 8
Fix at “0”
1 : Receive
Enable
1 : Wake up
Enable
00 : I/O Interface
01 : UART 7-bit
10 : UART 8-bit
11 : UART 9-bit
00 : TO0 Trigger
01 : Baud rate generator
10 : Internal clock φ1
11 : Don’t care
175
TMP96C031N/F
(6) Serial Channel (2/2)
Symbol
Name
Address
7
6
–
5
4
3
2
1
0
BR1CK1
BR1CK0
BR153
BR152
BR151
BR150
0
0
0
R/W
BR1CR
Baud Rate
Control
R/W
0
0
57H
0
0
00 : φt0 (fc/4)
01 : φt2 (fc/16)
10 : φt8 (fc/64)
11 :φt32 (fc/256)
Fix at “0”
Set frequency divisor
0~F
(“1” prohibited)
ODE1
ODE
Special
Open Drain
Enable
ODE0
R/W
58H
0
0
1 : P74
Open-drain
1 : P60
Open-drain
2
1
0
ADS
ADCH1
(7) A/D Converter Control
Symbol
Name
Address
7
EOCF
ADMOD
A/D Converter
Mode Reg.
6
5
4
3
ADBF
REPET
SCAN
ADCS
R/W
R/W
0
0
0
1 : Scan
mode
1 : Slow
mode
R
5EH
0
1 : END
0
1 : BUSY
1 : Repeat
mode set
R/W
ADCH0
R/W
0
1 : START
0
0
Analog Input Channel Select
–
ADREG0
AD Result
Reg. 0
60H
R
Undefined
–
ADREG1
AD Result
Reg. 1
61H
R
Undefined
–
ADREG2
AD Result
Reg. 2
62H
R
Undefined
–
ADREG3
AD Result
Reg. 3
63H
R
Undefined
176
TOSHIBA CORPORATION
TMP96C031N/F
(8) Interrupt Control (1/2)
TOSHIBA CORPORATION
177
TMP96C031N/F
(8) Interrupt Control (2/2)
Symbol
Name
Address
DMA0V
DMA 0
request
Vector
7CH
(Prohibit
RMW)
7
6
5
4
3
2
1
0
DAM0V5
DMA0V4
0
0
DAM1V5
DMA1V4
0
0
DAM2V5
DMA2V4
0
0
DAM3V5
DMA3V4
µDMA0 start vector
DMA0V8
DMA0V7
0
0
DMA0V6
W
0
µDMA1 start vector
DMA1V
DMA 1
request
Vector
7DH
(Prohibit
RMW)
DMA01V8
DMA1V7
DMA1V6
W
0
0
DMA2V8
DMA2V7
0
0
0
µDMA2 start vector
DMA2V
DMA 2
request
Vector
7EH
(Prohibit
RMW)
DMA2V6
W
0
µDMA3 start vector
DMA3V
DMA 3
request
Vector
7FH
(Prohibit
RMW)
DMA3V8
DMA3V7
DMA3V6
W
0
I4IE
I3IE
I2IE
I1IE
0
0
0
0
I1EM
I0IE
I0LE
NMIREE
0
0
0
0
W
7AH
IIMC0
Interrupt Input
Mode
Control 0
(Prohibit
RMW)
0
1 : INT4
input
enable
0
1 : INT3
input
enable
0
1 : INT2
input
enable
0
1 : INT1
input
enable
0 : INTO
rising
edge
1 : INT1
falling
edge
1 : INT0
input
enable
0 : INTO
edge
mode
1 : INTO
level
mode
I7IE
I6LE
7BH
IIMC1
178
Interrupt Input
Mode
Control 1
I5IE
W
0
(Prohibit
RMW)
1 : Operate
even at
NMI rise
edge
1 : INT7
input
enable
0
1 : INT6
input
enable
0
1 : INT5
input
enable
TOSHIBA CORPORATION
TMP96C031N/F
(9) Chip Select/Wait Controller (1/2)
Symbol
Name
Address
7
6
5
4
B0E
B0SYS
B0ARE
B0BUS
3
2
1
0
B0W1
B0W0
B0C1
B0C0
0
0
0
0
W
B0CS
Block 0
CS/WAIT
control
register
68H
(Prohibit
RMW)
0
0
0
0
0 : CS0 DIS
1 : CS0 EN
1 : SYSTEM
only
0 : 7F00 ~
7FFF
1 : Address
area
specification
0 : 16-bit Bus
1 : 8-bit Bus
B1E
B1SYS
B1ARE
B1BUS
00 : 2WAIT
01 : 1WAIT
10 : 1WAIT + n
11 : 0WAIT
00 : 2WAIT
01 : 1WAIT
10 : 1WAIT + n
11 : 0WAIT
B1W1
B1W0
0
0
W
B1CS
Block 1
CS/WAIT
control
register
69H
(Prohibit
RMW)
0
0
0
0
0 : CS1 DIS
1 : CS1 EN
↑
0 : 80 ~
7FFF
1 : Address
area
specification
↑
B2E
B2SYS
B2ARE
B2BUS
1
0
0
Undefined
0 : CS0 DIS
1 : CS0 EN
↑
0 : 8000 ~
3FFFFF
1 : Address
area
specification
↑
B3E
B3SYS
B3ARE
B3BUS
0
0
0
0
0 : CS3/CAS
DIS
1 : CS3/CAS
EN
↑
0 : Undefined
1 : Address
area
specification
↑
S23
S22
S21
S20
↑
B2W1
B2W0
0
0
–
–
–
–
W
B2CS
B3CS
MSAR0
MAMR0
MSAR1
Block 2
CS/WAIT
control
register
Block 3
CS/WAIT
control
register
Memory
Start
Adrress
Reg. 0
Memory
Start
Adrress
Mask
Reg. 0
Memory
Start
Adrress
Reg. 1
6AH
(Prohibit
RMW)
40H
B3W1
B3W0
B3CAS
SRFC
0
0
0
0
W
68H
(Prohibit
RMW)
↑
0 : CS3/CAS
DIS
1 : CS3/CAS
EN
↑
0 : Self
refresh
execution
1 : Release
S19
S18
S17
S16
1
1
1
1
V16
V15
V14 ~ 9
V8
1
1
1
1
R/W
1
1
1
1
A23 ~ A16
Memory start address setting
V20
V19
V18
V17
1
1
1
1
R/W
41H
0: Address A8 ~ A20 comparison is valid.
1: Address A8 ~ A20 comparison is invalid. (Specification bit by bit).
S23
S22
S21
S20
1
1
1
1
S19
S18
S17
S16
1
1
1
1
R/W
42H
TOSHIBA CORPORATION
A23 ~ A16
Memory start address setting
179
TMP96C031N/F
(9) Chip Select/Wait Controller (2/2)
Symbol
Name
MAMR1
Memory
Start
Adrress
Mask
Reg. 1
MSAR2
MAMR2
Memory
Start
Adrress
Reg. 2
Memory
Start
Adrress
Mask
Reg. 2
Address
7
6
5
4
3
2
1
0
V21
V20
V19
V18
V17
V16
V15 ~ 9
V8
1
1
1
1
1
1
1
1
R/W
43H
0: Address A8 ~ A21 comparison is valid.
1: Address A8 ~ A21 comparison is invalid. (Specification bit by bit).
S23
S22
S21
S20
1
1
1
1
MSAR3
MAMR3
180
Memory
Start
Mask
Adrress
Reg. 3
S18
S17
S16
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
44H
A23 ~ A16
Memory start address setting
V22
V21
V20
V19
R/W
45H
1
1
1
1
0: Address A15 ~ A22 comparison is valid
1: Address A15 ~ A22 comparison is invalid. (Specification bit by bit).
S23
Memory
Start
Adrress
Reg. 3
S19
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
46H
1
1
1
1
A23 ~ A16
Memory start address setting
V22
V21
V20
V19
R/W
46H
1
1
1
1
0: Address A15 ~ A22 comparison is valid
1: Address A15 ~ A22 comparison is invalid. (Specification bit by bit).
TOSHIBA CORPORATION
TMP96C031N/F
(10) DRAM Control
Symbol
Name
Address
7
6
5
4
DMI
RS2
RS1
RS0
3
2
1
0
RW2
RW1
RW0
RC
0
0
0
0
R/W
0
DREFCR
Refresh
Control
Reg.
48H
TOSHIBA CORPORATION
Dummy cycle
0 : Prohibit
1 : Execute
0
0
Refresh cycle insertion interval
000 : 15 states
001 : 31 states
010 : 62 states
011 : 78 states
100 : 97 states
101 : 109 states
110 : 124 states
111 : 154 states
0
Refresh cycle insertion interval
000 : 2 states
001 : 3 states
010 : 4 states
011 : 5 states
100 : 6 states
101 : 7 states
110 : 8 states
111 : 9 states
Refresh cycle
0 : Prohibit
1 : Execute
181
TMP96C031N/F
6. Port Section Equivalent Circuit Diagram
• Reading The Circuit Diagram
Basically, the gate singles written are the same as
those used for the standard CMOS logic IC [74HCXX]
series.
The dedicated signal is described below.
STOP: This signal becomes active “1” when the hold mode
setting register is set to the STOP mode and the CPU
executes the HALT instruction. When the drive enable
bit [DRIVE] is set to “1”, however, STP remains at “0”.
• The input protection resistans ranges from several tens of
ohms to several hundreds of ohms.
• PO (AD0 ~ AD7), P1 (AD8 ~ 15, A8 ~ 15), P2 (A16 ~ 23)
• RD, WR
• P30 ~ 33, P35
182
TOSHIBA CORPORATION
TMP96C031N/F
• P61 ~ P67, P70 ~ P73, P75 ~ P76
VCC
• P50 (AN0/INT0)
• P51 ~ P53 (AN1 ~ 3/INT1 ~ 3)
TOSHIBA CORPORATION
183
TMP96C031N/F
• P60 (TXD0), P74 (TXD1)
• P34 (NMI/R/W)
• P40~ P43 (CS0 ~ CS3/CAS)
184
TOSHIBA CORPORATION
TMP96C031N/F
• CLK
• AM8/16
• RESET
• X1, X2
• VREF
TOSHIBA CORPORATION
185
TMP96C031N/F
7. Guidelines and Restrictions
(1)
(2)
Special Expression
➀ AM8/16 pin
➀ Explanation of a built-in I/O register: Register
Fix these pins VCC or GND unless changing voltage.
Symbol
<Bit Symbol>
ex) TRUN <TRUN> . . . Bit T0RUN of Register TRUN
➁ Warming-up Counter
An instruction which CPU executes following by one
instruction.
The warming-up counter operates when the STOP
mode. is released even the system which is used an
external oscillator. As a result, it takes warming up time
from inputting the releasing request to outputting the
system clock.
1. CPU reads data of the memory.
➂ Programmable Pull Up/Down Resistance
➁ Read, Modify and Write Instruction
2. CPU modifies the data.
3. CPU writes the data to the same memory.
ex1) SET 3, (TRUN) . . . set bit3 of TRUN
ex2) INC1, (100H) increment the data of 100H
• The representative Read, Modify and Write
Instruction in the TLCS-900
SET
CHG
INC
RLD
imm, mem,
imm, mem,
imm, mem,
A, mem,
RES
TSET
DEC
ADD
imm, mem
imm, mem
imm, mem
imm, reg
The programmable pull up/down resistors can be
selected ON/OFF by program when they are used as
the input ports. The case of they are used as the output ports, they cannot be selected ON/OFF by program.
➃ Bus Releasing Function
Refer to the “Note about the Bus Release” in 3.5 Functions of Ports because the pin state when the bus is
released is written.
➄ Watch Dog Timer
➂ 1 state
The watch dog timer starts operation immediately after
the reset is released. When the watch dog timer is not
used, set watch dog timer to disable.
One cycle clock divided by 2 oscillation frequency is
called 1 state
➅ CPU (High Speed µDMA)
ex) Oscillation frequency is 20MHz
2/20MHz = 100ns = 1 state
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Guidelines
Only the “LDC cr, r”, “LDC r, cr” instruction can be
used to access the control register like transfer source
address register (DMASn) in the CPU.
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