TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com 256-TAPS DUAL CHANNEL DIGITAL POTENTIOMETER WITH NON-VOLATILE MEMORY Check for Samples: TPL0102 FEATURES 1 • • • • • • • • • • • • Dual Channel, 256-Position Resolution Non-volatile Memory Stores Wiper Settings 2mm x 2mm, 14-pin MicroQFN or 14-pin TSSOP Packages 100 kΩ End-to-End Resistance (TPL0102-100) Fast Power-up Response Time to Wiper Setting: <100µs ±0.5 LSB INL, ±0.25 LSB DNL (Voltage-Divider Mode) 4 ppm/°C Ratiometric Temperature Coefficient I2C-compatible Serial Interface 2.7 V to 5.5 V Single-Supply Operation ±2.25 V to ±2.75 V Dual-Supply Operation Operating Temperature Range From -40°C to +85°C ESD Performance Tested Per JESD 22 – 2000-V Human Body Model (A114-B, Class II) APPLICATIONS • • • • • Adjustable Gain Amplifiers and Offset Trimming Adjustable Power Supplies Precision Calibration of Set Point Thresholds Sensor Trimming and Calibration Mechanical Potentiometer Replacement MicroQFN - RUC PACKAGE (TOP VIEW) VDD A0 HA 1 LA 14 13 12 A1 2 11 GND WA 3 10 SCL HB 4 9 SDA 8 VSS LB 5 6 7 WB A2 TSSOP - PW PACKAGE (TOP VIEW) HA 1 14 VDD LA 2 13 A0 WA 3 12 A1 HB 4 11 GND LB 5 10 SCL WB 6 9 SDA A2 7 8 VSS DESCRIPTION The TPL0102 is a two channel, linear-taper digital potentiometer with 256 wiper positions. Each potentiometer can be used as a three-terminal potentiometer or as a two-terminal rheostat. The TPL0102-100 has an end-to-end resistance of 100kΩ. The TPL0102 has non-volatile memory (EEPROM) which can be used to store the wiper position. The internal registers of the TPL0102 can be accessed using the I2C interface. The TPL0102 is available in a 14-pin MicroQFN and 14-pin TSSOP package with a specified temperature range of -40°C to +85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) TSSOP – PW (2) ORDERABLE PART NUMBER TOP-SIDE MARKING Tape and reel MicroQFN-RUC TPL0102-100PWR EL-100 TPL0102-100RUCR 6N Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Table 1. Summary of Features Feature TPL0102-100 # of Potentiometers 2 Digital Interface 2 I C Steps 256 Wiper Memory Non-Volatile Taper Linear End-to-end Resistance 100kΩ End-to-end Resistance Tolerance 20% 25 Ω (typ) Wiper Resistance MicroQFN (RUC): 4 mm2 Smallest Package Size FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 SCL I 2C INTERFACE VDD VSS HA HB VOLATILE REGISTERS WA SDA WB NON-VOLATILE REGISTERS GND 2 Submit Documentation Feedback LA LB Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com DIGITAL POTENTIOMETER CONFIGURATIONS VOLTAGE DIVIDER MODE VH VHW VHW = (VH – VL) x (1 – (D/256)) W VH - VL VWL VWL = (VH – VL) x D/256 Where D = Decimal Value of Wiper Code VL RHEOSTAT MODE A H H (Floating) RTOT W OR RWL = RTOT x D/256 RTOT W Where D = Decimal Value of Wiper Code RWL RWL L L RHEOSTAT MODE B H H RHW RTOT RHW W OR L RTOT RHW = RTOT x (1 – (D/256)) W Where D = Decimal Value of Wiper Code L (Floating) Figure 1. DPOT Configurations Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 3 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com Table 2. PIN DESCRIPTION TABLE 4 14 RUC/14 PW PIN NAME TYPE DESCRIPTION 1 HA I/O High terminal of Potentiometer A 2 LA I/O Low terminal of Potentiometer A 3 WA I/O Wiper terminal of Potentiometer A 4 HB I/O High terminal of Potentiometer B 5 LB I/O Low terminal of Potentiometer B 6 WB I/O Wiper terminal of Potentiometer B 7 A2 Input Address Bit 2 8 VSS Power Negative or GND Power Supply Pin 9 SDA I/O I2C Data I/O 2 10 SCL Input I C Clock Input 11 GND Ground Ground 12 A1 Input Address Bit 1 13 A0 Input Address Bit 0 14 VDD Power Positive Power Supply Pin Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) (3) VDD to GND VSS to GND Supply voltage range MIN MAX –0.3 7 V –7 0.3 V 7 V VSS – 0.3 VDD + 0.3 V –0.3 VDD + 0.3 VDD to VSS VH, VL, VW Voltage at resistor terminals VI Digital input voltage range IH, IL, IW Pulse Current Continuous Current θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) PW package mA ±2 mA 216.7 –65 V ±20 88 RUC package UNIT 150 °CW °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. All voltages are with respect to ground, unless otherwise specified. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 5 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V, VSS = 0V, VH= VDD, VL= GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at VDD= 5V, TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 100 120 kΩ RTOT End-to-end Resistance (Between H and L Terminals) RH, RL Terminal resistance 60 200 Ω RW Wiper resistance 25 100 Ω Terminal capacitance 22 pF Wiper capacitance 16 pF CH, CL (1) (2) CW (1) (2) TPL0102-100 VH = VSS to VDD, VL = Floating OR VL = VSS to VDD, VH = Floating ILKG Terminal Leakage Current TCR Resistance temperature Input Code = 0x80h coefficient 92 ppm/°C RTOT,MATCH Channel-to-channel resistance match 0.1 % 0.1 1 µA Voltage Divider Mode INL (3) (4) DNL –0.5 Integral non-linearity (3) (5) –0.25 LSB 0.25 LSB ZSERROR (6) (7) Zero-scale error 0 0.1 2 LSB FSERROR (6) (8) Full-scale error –2 –0.1 0 LSB VMATCH (6) (9) Channel-to-Channel matching Wiper at the same tap position, same voltage at all H and same voltage at all L terminals 2 LSB TCV Ratiometric temperature coefficient Wiper set at mid-scale BW Bandwidth TPL0102-100 TSW Wiper setting time TPL0102-100 THD Total harmonic distortion VH = 1 VRMS at 1 kHz, VL = (VDD – VSS)/2, Measurement at W XTALK Cross talk fH = 1 kHz, VL = GND, Measurement at W (1) –2 4 Wiper set at mid-scale CLOAD = 10 pF TPL0102-100 ppm/°C 229 kHz 3.6 µS 0.03 % –82 dB Terminal and Wiper Capacitance extracted from self admittance of three port network measurement Yii = (2) Differential non-linearity 0.5 Ii Vi Vk =0 for k ¹i Digital Potentiometer Macromodel H CH RTOTAL CW L (3) (4) (5) (6) (7) (8) (9) 6 W CL LSB = (VMEAS[code 255] – VMEAS[code 0]) / 255 INL = ((VMEAS[code x] – VMEAS[code 0]) / LSB) - [code x] DNL = ((VMEAS[code x] – VMEAS[code x-1]) / LSB) – 1 IDEAL_LSB = (VH-VL) / 256 ZSERROR = VMEAS[code 0] / IDEAL_LSB FSERROR = [(VMEAS[code 255] – (VH-VL)) / IDEAL_LSB] + 1 VMATCH = (VMEAS_A[code x] – VMEAS_B[code x]) / IDEAL_LSB Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7V to 5.5V, VSS = 0V, VH= VDD, VL= GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at VDD= 5V, TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RHEOSTAT MODE (Measurements between W and L with H not connected, or between W and H with L not connected) RINL (10) (11) Integral non-linearity RDNL (10) (12) Differential non-linearity ROFFSET (13) (14) Offset RMATCH (13) (15) Channel-to-Channel matching RBW Bandwidth (10) (11) (12) (13) (14) (15) –1 1 LSB –0.5 0.5 LSB 2 LSB 2 LSB 0 0.2 –2 Code = 0x00h, L Floating, Input applied to W, Measure at H, CLOAD = 10 pF TPL0102-100 54 kHz RLSB = (RMEAS[code 255] – RMEAS[code 0]) / 255 RINL =( (RMEAS[code x] – RMEAS[code 0]) / RLSB) - [code x] RDNL =( (RMEAS[code x] – RMEAS[code x-1]) / RLSB )– 1 IDEAL_RLSB = RTOT / 256 ROFFSET = RMEAS[code 0] / IDEAL_RLSB RMATCH = (RMEAS_A[code x] – RMEAS_B[code x]) / IDEAL_RLSB OPERATING CHARACTERISTICS VDD = 2.7V to 5.5V, VSS = 0V, VH = VDD, VL = GND, TA= –40°C to 85°C (unless otherwise noted). Typical values are at VDD = 5V, TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS IDD(STBY) VDD standby current VDD = 2.75 V, VSS = –2.75, I2C interface in standby mode ISS(STBY) VSS standby current VDD = 2.75 V, VSS = –2.75, I2C interface in standby mode IDD(SHUTDOWN) VDD shutdown current VDD = 2.75 V, VSS = –2.75, I2C interface in standby mode ISS(SHUTDOWN) VSS shutdown current VDD = 2.75 V, VSS = –2.75, I2C interface in standby mode IDD VDD current during non-volatile write VDD = 2.75 V, VSS = –2.75 ISS VSS current during non-volatile write VDD = 2.75 V, VSS = –2.75 ILKG-DIG Digital pins leakage current (A0, A1, A2, SDA, and SCL) VPOR Power-on recall voltage MIN –1 TYP MAX 0.2 1 µA µA 1 –0.2 200 µA µA µA -200 –1 Minimum VDD at which memory recall occurs µA –0.2 0.2 –1 UNIT µA 1 2 V EEPROM Specification EEPROM endurance 100,000 Cycles 100 Years 20 ms SCL falling edge of last bit of wiper data byte to wiper new position 600 ns Wiper position recall time from shut-down mode SCL falling edge of last bit of ACR data byte to wiper stored position and H connection 800 ns Power-up delay VDD above VPOR, to wiper initial value register recall completed, and I2C interface in standby mode 35 EEPROM retention tWC TA = 85°C Non-volatile write cycle time Wiper Timing Characteristics tWRT tSHUTDOWNREC tD CIN Wiper response time Pin capacitance A0, A1, A2, SDA SCL pins 100 7 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 µs pF 7 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com OPERATING CHARACTERISTICS (continued) VDD = 2.7V to 5.5V, VSS = 0V, VH = VDD, VL = GND, TA= –40°C to 85°C (unless otherwise noted). Typical values are at VDD = 5V, TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C Interface Specifications VIH Input high voltage VIL Input low voltage VOL Output low voltage SDA pin, IOL = 4 mA CIN Pin capacitance A0, A1, A2, SDA SCL pins 0.7 x VDD 5.5 V 0 0.3 x VDD V 0.4 V 7 pF TIMING REQUIREMENTS VDD = 2.7V to 5.5V, VSS = 0V, VH = VDD, VL = GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at VDD = 5V, TA = 25°C (unless otherwise noted). STANDARD MODE I2C BUS FAST MODE I2C BUS MIN MAX 100 UNIT MIN MAX 0 400 2 I C Interface Timing Requirements fSCL I2C clock frequency 0 tSCH I2C clock high time 4 2 tSCL I C clock low time tsp I2C spike time tSDS I2C serial data setup time tSDH I2C serial data hold time 4.7 0 µs 1.3 50 0 kHz µs 0.6 50 ns 250 100 ns 0 0 ns 2 tICR I C input rise time 1000 300 ns tICF I2C input fall time 300 20 + 0.1Cb (1) 300 ns tICF I2C output fall time, 10 pF to 400 pF bus 300 20 + 0.1Cb (1) 300 ns 2 20 + 0.1Cb (1) tBUF I C bus free time between stop and start 4.7 1.3 µs tSTS I2C start or repeater start conditions setup time 4.7 1.3 µs tSTH I2C start or repeater start condition hold time 4 0.6 µs 2 I C stop condition setup time tVD(DATA) Valid data time, SCL low to SDA output valid 1 1 µs tVD(DATA) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1 1 µs (1) 8 4 µs tSPS 0.6 Cb = total capacitance of one bus line in pF Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com REGISTER DESCRIPTION Slave Address Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 2 Bit 0 (LSB) 1 0 1 0 A2 A1 A0 R/W TPL0102 Register Map REGISTER ADDRESS (HEX) NON-VOLATILE VOLATILE 0 IVRA WRA 1 IVRB WRB 2 General purpose N/A 3 General purpose N/A 4 General purpose N/A 5 General purpose N/A 6 General purpose N/A 7 General purpose N/A 8 General purpose N/A 9 General purpose N/A A General purpose N/A B General purpose N/A C General purpose N/A E General purpose N/A D General purpose F 10 N/A Reserved N/A ACR IVRA (Initial Value Register for Potentiometer A) • • • Register Address: 00H Factory Programmed Value: 80H Type: Non-volatile Write/Read NAME SIZE (BITS) IVRA 8 DESCRIPTION Non-volatile register to store wiper position for potentiometer A WRA (Wiper Resistance Register for Potentiometer A) • • • Register Address: 00H Reset Value: Same as IVRA Type: Volatile Write/Read NAME SIZE (BITS) WRA 8 DESCRIPTION Volatile register to change wiper position for potentiometer A Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 9 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com IVRB (Initial Value Register for Potentiometer B) • • • Register Address: 01H Factory Programmed Value: 80H Type: Non-volatile Write/Read NAME SIZE (BITS) IVRB 8 DESCRIPTION Non-volatile register to store wiper position for potentiometer B WRB (Wiper Resistance Register for Potentiometer B) • • • Register Address: 01H Reset Value: Same as IVRB Type: Volatile Write/Read NAME SIZE (BITS) WRB 8 DESCRIPTION Volatile register to change wiper position for potentiometer B ACR (Access Control Register) • • • Register Address: 00H Reset Value: 40H Type: Non-volatile Write/Read NAME SIZE (BITS) IVRA 8 ACR 8 Default Value NAME VOL DESCRIPTION Non-volatile register to store wiper position for potentiometer A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VOL SHDN WIP 0 0 0 0 0 0 1 0 0 0 0 0 0 SIZE (BITS) 1 DESCRIPTION 0: Non-volatile registers (IVRA, IVRB) are accessible. Value written to IVRi register is also written to the corresponding WRi. 1: Only Volatile Registers (WRi) are accessible. SHDN 1 0: Shut-down mode is enabled. Potentiometers are in shut-down mode. (see Figure 2) 1: Shut-down mode is disabled WIP (Read-only bit) 10 0: Non-volatile write operation is not in progress 1 1: Non-volatile write operation is in progress (it is not possible to write to the WRi or ACR while WIP = 1) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com H SHDN Switch Open when SHDN = Low, Switch Closed when SHDN = High SHDN Switch Open when SHDN = Low, Switch Closed when SHDN = High W L Figure 2. Potentiometer in Shut-Down Mode Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 11 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com PRINCIPLES OF OPERATION The TPL0102 is a two channel, linear-taper digital potentiometer with 256 wiper positions. Each potentiometer can be used as a three-terminal potentiometer or as a two-terminal rheostat. The TPL0102-100 has an end-to-end resistance of 100kΩ. The TPL0102 has non-volatile memory (EEPROM) which can be used to store the wiper position. When the device is powered down, the last value stored in the IVR register will be maintained in the non-volatile memory. When power is restored, the contents of the IVR register are recalled and loaded into the corresponding WR register to set the wipers to the initial position. The internal registers of the TPL0102 can be accessed using the I2C interface. The position of the wiper terminal is controlled by the value in the WR 8-bit register. When the WR contains all zeroes, the wiper terminal W is closest to its L (Low) terminal. As the value of the WR increases from all zeroes to all ones (255 decimal), the wiper moves monotonically from the position closest to L to the position closest to H. At the same time, the resistance between W and L increases monotonically, whereas the resistance between W and H decreases monotonically. Potentiometer Pin Description HA,HB,LA,LB The high (HA, HB) and low (LA, LB) terminals of the TPL0102 are equivalent to the fixed terminals of a mechanical potentiometer. The H and L terminals do not have any polarity restrictions, i.e. H can be at a higher voltage than L, or L can be at a higher voltage than H. The WA and WB terminals are the wipers and equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper is set using the WR register. With the WR register set to 255 decimal, the wiper is closest to the H terminal, and with the WR register set to 0, the wiper is closest to the L terminal. SDA, SCL SDA is a bi-directional serial data input/output pin for I2C communication. SDA is an open drain output and requires an external pull-up resistor. SCL is the serial clock input for I2C communication. SCL requires an external pull-up resistor. A0, A1, A2 These inputs are used to set the last three bits of the I2C address of the device. By using different values for A0, A1, A2, up to eight TPL0102 devices can be used on the same I2C bus. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com I2C Interface From Processor to DPOT From DPOT to Processor 2 I C Write to A Register Start Address (1010 _ _ _) 0 Ack Register Addr Ack Data1 DataN Ack Ack Stop 2 I C Read From A Register Start Address (1010_ _ _) 0 Ack Register Addr Ack reStart Address (1010_ _ _) 1 Ack First Read Data Byte Ack Ack Last Read Data Byte noAck Stop Figure 3. I2C Interface Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 13 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com Following is a sample sequence to set wipers of both potentiometers at mid-scale. Assume A0, A1, and A2 are zero and device has just been powered up. From Processor to DPOT From DPOT to Processor Method 1: First Write 0x80 to IVRA and then write 0x80 to IVRB Register Start Address (1010 000b) Data (0x80) Start Ack Address (1010 000b) Data (0x80h) Ack 0 Ack IVRA Register (0x00h) Ack Ack IVRB Register (0x01h) Ack Stop 0 Stop Method 2: Perform a multi byte write to IVRA and IVRB Register Start Address (1010 000b) Data (0x80h) Ack Data written to Register 0x00h 0 Ack Data (0x80h) IVRA Register (0x00h) Ack Ack Stop Data written to Register 0x01h Figure 4. I2C Interface Example 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com Standard I2C Interface Details The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by the master sending a start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 5). After the start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse Figure 5. Definition of Start and Stop Conditions The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see Figure 6). Figure 6. Bit Transfer A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 5). The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken into account. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 15 TPL0102 SLIS134A – MARCH 2011 – REVISED MARCH 2011 www.ti.com Figure 7. Acknowledgment on the I2C Bus 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPL0102 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPL0102-100PWR PREVIEW TSSOP TPL0102-100RUCR ACTIVE QFN Pins Package Qty PW 14 2000 TBD RUC 14 3000 Green (RoHS & no Sb/Br) Eco Plan (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPL0102-100RUCR Package Package Pins Type Drawing QFN RUC 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 2.3 B0 (mm) K0 (mm) P1 (mm) 2.3 0.55 4.0 W Pin1 (mm) Quadrant 8.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL0102-100RUCR QFN RUC 14 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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