DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA2754GR SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µPA2754GR is Dual N-channel MOS Field Effect Transistor designed for Li-ion battery protection circuit and power management application. 8 5 1 : Source 1 2 : Gate 1 7, 8: Drain 1 FEATURES 3 : Source 2 4 : Gate 2 5, 6: Drain 2 PACKAGE µPA2754GR Power SOP8 6.0 ±0.3 4 4.4 0.8 0.15 +0.10 –0.05 5.37 MAX. 0.05 MIN. ORDERING INFORMATION PART NUMBER 1.44 1 1.8 MAX. • Dual chip type • Low on-state resistance RDS(on)1 = 14.5 mΩ MAX. (VGS = 4.5 V, ID = 5.5 A) RDS(on)2 = 15.0 mΩ MAX. (VGS = 4.0 V, ID = 5.5 A) RDS(on)4 = 18.6 mΩ MAX. (VGS = 2.5 V, ID = 5.5 A) • Low Ciss: Ciss = 1940 pF TYP. (VDS = 10 V, VGS = 0 V) • Built-in G-S protection diode • Small and surface mount package (Power SOP8) 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS 30 V Gate to Source Voltage (VDS = 0 V) VGSS ±12 V EQUIVALENT CIRCUIT ID(DC) ±11 A (1/2 circuit) ID(pulse) ±88 A PT 2.0 W PT 1.7 W Tch 150 °C Tstg −55 to +150 °C IAS 11 A EAS 12.1 mJ Drain Current (DC) Note2 Drain Current (pulse) Note1 Total Power Dissipation (2 units) Total Power Dissipation (1 unit) Channel Temperature Storage Temperature Single Avalanche Current Note3 Single Avalanche Energy Note3 Note2 Note2 Drain Body Diode Gate Gate Protection Diode Source Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1% 2 2. TA = 25°C, Mounted on ceramic substrate of 2000 mm x 2.2 mm 3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 12 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G15816EJ1V0DS00 (1st edition) Date Published January 2003 NS CP(K) Printed in Japan 2001 µPA2754GR ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 1 µA Gate Leakage Current IGSS VGS = ±12 V, VDS = 0 V ±10 µA VGS(off) VDS = 10 V, ID = 1 mA 0.5 1.5 V | yfs | VDS = 10 V, ID = 5.5 A 8 RDS(on)1 VGS = 4.5 V, ID = 5.5 A 11.5 14.5 mΩ RDS(on)2 VGS = 4.0 V, ID = 5.5 A 11.8 15.0 mΩ RDS(on)3 VGS = 3.1 V, ID = 5.5 A 12.7 16.9 mΩ RDS(on)4 VGS = 2.5 V, ID = 5.5 A 13.9 18.6 mΩ Gate Cut-off Voltage Note Forward Transfer Admittance Note Drain to Source On-state Resistance Note 16 S Input Capacitance Ciss VDS = 10 V 1940 pF Output Capacitance Coss VGS = 0 V 385 pF Reverse Transfer Capacitance Crss f = 1 MHz 270 pF Turn-on Delay Time td(on) VDD = 15 V, ID = 5.5 A 21 ns tr VGS = 4.5 V 45 ns td(off) RG = 10 Ω 75 ns 30 ns Rise Time Turn-off Delay Time Fall Time tf Total Gate Charge QG VDD = 24 V 25 nC Gate to Source Charge QGS VGS = 4.5 V 3 nC Gate to Drain Charge QGD ID = 11 A 10 nC Body Diode Forward Voltage VF(S-D) IF = 11 A, VGS = 0 V 0.81 1.2 V Reverse Recovery Time trr IF = 11 A, VGS = 0 V 47 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 41 nC Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% BVDSS IAS VDS VDS ID Starting Tch τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE PG. 2 50 Ω 10% 0 10% Wave Form VDD D.U.T. IG = 2 mA 90% VDS VGS 0 RL VDD Data Sheet G15816EJ1V0DS td(on) tr ton td(off) tf toff µPA2754GR TYPICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 0 Mounted on ceramic substrate of 2000 mm 2 x 2.2 mm 2.4 2 units 2 1.6 1 unit 1.2 0.8 0.4 0 0 25 50 75 100 125 150 175 0 TA - Ambient Temperature - °C 25 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 1000 100 I D(pulse) = 88 A I D(DC) = 11 A PW = 100 µs 10 1 ms 30 A 1 10 ms 55 A 100 ms Power Dissipation Limited 0.1 1 unit, Single pulse Mounted on ceramic substrate of 2000 mm 2 x 2.2 mm DC 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A R DS(on) Limited (V GS = 4.5 V) Rth(ch-A) = 73.5°C/W 100 10 1 1 unit, Single pulse 2 Mounted on ceramic substrate of 2000 mm x 2.2 mm 0.1 100 µ 1m 10 m 100 m 1 10 100 PW - Pulse Width - s Data Sheet G15816EJ1V0DS 3 µPA2754GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 100 100 V DS = 10 V Pulsed Pulsed 80 10 ID - Drain Current - A ID - Drain Current - A V GS = 4.5 V 3.1 V 60 2.5 V 40 1 0.1 20 0.01 0 0.001 0 0.4 0.8 1.2 1.6 2 3 4 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE V DS = 10 V ID = 1 mA 1.5 1 0.5 -50 0 50 100 150 100 V DS = 10 V Pulsed TA = −25°C 25°C 75°C 125°C 10 1 0.1 0.01 0.1 1 10 100 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 50 Pulsed V GS = 2.5 V 40 3.1 V 30 20 4.5 V 10 0 0.1 1 10 100 1000 RDS(on) - Drain to Source On-state Resistance - mΩ VGS(off) - Gate Cut-off Voltage - V 1 VGS - Gate to Source Voltage - V 0 RDS(on) - Drain to Source On-state Resistance - mΩ 0 VDS - Drain to Source Voltage - V 2 80 Pulsed 60 ID = 11 A 5.5 A 40 20 0 0 4 8 VGS - Gate to Source Voltage - V ID - Drain Current - A 4 T A = 150°C 75°C 25°C −25°C Data Sheet G15816EJ1V0DS 12 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 25 10000 Pulsed Ciss, Coss, Crss - Capacitance - pF VGS = 2.5 V 3.1 V 4.5 V 20 15 10 5 0 -50 0 50 100 C iss 1000 C oss V GS = 0 V f = 1 MHz 10 0.01 150 Tch - Channel Temperature - °C 10 100 DYNAMIC INPUT/OUTPUT CHARACTERISTICS V DD = 15 V V GS = 4.5 V R G = 10 Ω 100 VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 1 40 tr t d(off) tf td(on) 10 8 30 6 V DD = 24 V 15 V 6.0 V 20 4 V GS 10 2 V DS ID = 11 A 0 1 0.1 1 10 0 0 100 10 20 30 QG - Gate Charge - nC ID - Drain Current - A SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 100 1000 trr - Reverse Recovery Time - ns Pulsed IF - Diode Forward Current - A 0.1 VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS 1000 C rss 100 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ µPA2754GR 10 V GS = 0 V 1 0.1 0.01 di/dt = 100 A/µs V GS = 0 V 100 10 1 0 0.5 1 1.5 2 VF(S-D) - Source to Drain Voltage - V Data Sheet G15816EJ1V0DS 0.1 1 10 100 IF - Diode Forward Current - A 5 µPA2754GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD SINGLE AVALANCHE ENERGY DERATING FACTOR 120 Energy Derating Factor - % IAS - Single Avalanche Current - A 100 IAS = 11 A 10 E AS = 12.1 mJ 1 V DD = 15 V R G = 25 Ω V GS = 12 → 0 V Starting Tch = 25°C 0.1 0.01 80 60 40 20 0 0.1 1 10 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - °C L - Inductive Load - mH 6 V DD = 15 V RG = 25 Ω V GS = 12 → 0 V IAS ≤ 11 A 100 Data Sheet G15816EJ1V0DS µPA2754GR • The information in this document is current as of January, 2003. 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