DATA SHEET MOS INTEGRATED CIRCUIT µPD4704 EXTENSION 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS DESCRIPTION The µPD4704 is 8-bit up/down counters for extension of the µPD4702 incremental encoder counter. They perform an up/down-count using an 8-bit width with a µPD4702 carry or borrow signal as input. In addition, a carry output and borrow output are also provided for further extension of the count width, enabling extension to be performed in 8-bit units. FEATURES • 8-bit up/down counter for extension of µPD4702 • Count data output controllable (latch and 3-state output) • Extension carry and borrow outputs • CMOS, single +5 V power supply PIN NAMES PIN CONFIGURATION (Top View) Up : Up-count input Down Reset : Down-count input : Counter reset input STB OE : Latch strobe signal input : Output control signal input CD0-7 Carry : Count data outputs : Carry pulse output Borrow : Borrow pulse output ORDERING INFORMATION Part Number Package µPD4704C 20-pin plastic DIP (300 mil) µPD4704G 20-pin plastic SOP (300 mil) Document No. IC-3305A (2nd edition) (O. D. No. IC-8762B) Date Published April 1997 P Printed in Japan Reset 1 20 VDD A 2 19 Carry B 3 18 Borrow NC 4 17 STB CD0 5 16 OE CD1 6 15 CD7 CD2 7 14 CD6 CD3 8 13 CD5 NC 9 12 CD4 VSS 10 11 NC © 1993 µPD4704 BLOCK DIAGRAM Reset Carry A Phase Discrimination Edge Detection 8-Bit Up/Down Counter B Borrow 8-Bit Latch 3-State Output STB OE CD0–7 PIN FUNCTIONS Pin Name 2 Function Input/Output Up-count & down-count signal input pins Count is performed on rise of signal. Up Down Input D0 to 7 Output (3-state) Carry Output 8-bit counter carry signal output pin (active-low) Borrow Output 8-bit counter borrow signal output pin (active-low) RESET Input (Schmitt) Count data output pins. Activated when OE is “L”, high impedance outputs when OE is “H”. 8-bit counter reset signal output pin Counter is reset when this pin is “H”. OE Input Count data output control signal input pin STB Input Counter data output latch signal. Data is latched on the fall of STB, and is held while STB = “L”. VDD Power supply input pin GND Ground pin µPD4704 TRUTH TABLE 1 (COUNTER BLOCK) × : H or L UP DOWN RESET Carry Borrow × × H × × H H × H L × × Down-count L × × Up-count L × × Disabled (count undefined) L L × × Disabled (count undefined) H L L H L Borrow output when count = 00H L H L L H Carry output when count = 0FFH H L Remarks Reset Reset TRUTH TABLE 2 (LATCH & OUTPUT BLOCKS) × : H or L STB OE CD0 to CD7 × H Output disable (3-state) × L Output enable H × Data through (count value load) L × Data latch (count value retention) 3 µPD4704 1. DESCRIPTION OF OPERATIONS (1) Count operation The µPD4704 is designed as 8-bit up/down counter for extension of the µPD4702. The first-stage Carry output is connected to the UP input of the µPD4704, and similarly, the Borrow output is connected to the DOWN input. A count is executed on the rising edge of the UP input or DOWN input. If the µPD4704 is to be used alone, without being connected to the µPD4702, either UP or the DOWN must be "H". If a count pulse is input to UP or DOWN while the other is "L", the count value may change. (2) Latch operation An R-S flip-flop is inserted in the latch circuit input as shown in Fig. 1, and when STB is changed from "H" to "L" while the UP or DOWN input is "L", the internal latch signal STB' remains at "H" until the end of the count operation. Therefore, latching is not performed during a count operation. If STB changes from "H" to "L" tSUDSTB1 (40 ns) or more after the falling edge of UP or DOWN, the post-count data is latched, and if STB changes from "H" to "L" within tSUDSTB2 (10 ns) after the falling edge of UP or DOWN, then conversely, the pre-count data is latched. Caution is required since, when UP or DOWN is "L" (during a count operation), the latch operation is kept waiting even if STB is changed from "H" to "L", and therefore if a reset is executed the latch contents will also be reset (see Figs. 2 and 3). Fig. 1 STB Input Circuit From UP/DOWN Circuit Count Clock STB' STB 4 µPD4704 Fig. 2 Relation Between STB Timing and Counter Value UP/DOWN STB tSUDSTB1 Pre-count value latched tSUDSTB2 Post-count value latched Either pre- or post-count value latched Fig. 3 STB and RESET Timing UP/DOWN tSUDSTB1 tDUDCD RESET STB If STB changes from "H" to "L" and a reset is executed in this period, the latch is also reset. (3) Carry & borrow outputs If the counter performs an up-count operation when the count value is 0FFH, an active-low pulse is output to the Carry output (the pulse width is virtually the same as the UP or DOWN pulse L period). Similarly, if the counter performs a down-count operation when the count value is 00H, an active-low pulse is output to the Borrow output. A Borrow pulse is also output if a down-count operation is performed while RESET is "H" (during a reset), and therefore, when a µPD4704 is added, a reset must be executed at the same time. 5 µPD4704 2. OPERATING PRECAUTIONS As the µPD4704 incorporates an 8-bit counter, a large transient current flows in the case of a count value which changes all the bits (such as 00H ↔ 0FFH or 7FH ↔ 080H). This will cause misoperation unless the impedance of the power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1 µF) be connected between VDD and VSS right next to the IC as shown in Fig. 4. Fig. 4 Decoupling Capacitor +5 V C VDD µPD4704 VSS 6 C : 0.1 uF tantalum electrolytic laminated ceramic capacitor, etc. µPD4704 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS = 0 V) PARAMETER SYMBOL RATING UNIT VDD –0.5 to +7.0 V Input voltage VI –1.0 to VDD +1.0 V Output voltage VO –0.5 to VDD +0.5 V Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C Permissible loss PD Supply voltage 500 (DIP) 200 (SOP) mW DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %) RATING PARAMETER SYMBOL TEST CONDITIONS UNIT MIN. Input voltage low VIL MAX. 0.8 V VIH Reset 2.6 V VIH Other than the above 2.2 V Output voltage low VOL IOL = 12 mA Output voltage high VOH IOH = –4 mA Static consumption current IDD VI = VDD, VSS II VI = VDD, VSS Input voltage high Input current 3-state output leak current Dynamic consumption current Hysteresis voltage IOFF IDD dyn VH 0.45 VDD – 0.8 V 50 µA –1.0 1.0 µA –10 10 µA 12 mA fIN = 16 MHz, CL = 50 pF Reset V 0.2 V AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %) PARAMETER Cycle Up SYMBOL tCYCT TEST CONDITIONS fin = 16 MHz MIN. MAX. UNIT 60 ns tPWUDL 25 ns tPWUDH 35 ns Setup time tSRSUD 0 ns Up/down switchover setupt time tSUDM 100 ns Reset time tDRSCD 60 ns Output delay tDUDCD 70 ns Output delay tDOECD 50 ns Output delay tDSTBCD 50 ns Float time tFOECD 40 ns tDUDCB1 50 ns tDUDCB2 100 ns Input pulse width Down CD0 to 7 Carry Output delay Borrow Output pulse width tPWCB 30 ns RESET Reset pulse width tPWRS 40 ns tSUDSTB1 40 ns STB Setting time tSUDSTB2 10 ns 7 µPD4704 AC Timings Fig. 1 Up/Down Signal Input Timing tCYCT tPWUDL tPWUDH UP/DOWN tCYCT tSUDM tPWUDL tPWUDH Fig. 2 Count Data Output Timing tPWRS tSRSUD RESET UP/DOWN tDRSCD tDUDCD Hi-Z CD0–CD7 Hi-Z tDOECD tFOECD OE tDSTBCD tDSTBCD tSUDSTB1 STB Fig. 3 Carry/Borrow Signal Output Timing tDUDCB1 tDUDCB2 UP/DOWN tPWCB Carry tDUDCB1 tDUDCB2 tPWCB Borrow Fig. 4 Strobe Signal Output Timing tSUDSTB1 UP/DOWN STB 8 tSUDSTB2 µPD4704 Consumption Current Measurement Circuit Measurement Conditions A, B inputs fIN = 16 MHz A D0 CL B 2.6 V D1 CL 0.8 V STB input connected to VDD or OE input connected to VSS. VDD Load on all outputs, CL = 50 pF. STB OE D7 CL AC Test Input Waveform VIH VIL VIH = 2.6 V (RESET input) VIH = 2.2 V (inputs other than RESET) VIL = 0.8 V Timing measurement is performed at 1.5 V. • 3 state output OE Output 1.5 V tDOECD tDFOECD R C VOH 1.5 V 90 % VDD 0V VDD Output 1.5 V 10 % R Output VOL R = 1 kΩ C = 50 pF C 9 µPD4704 Sample Application Circuits 16-bit counter 8 Data Bus Incremental Rotary Encoder 8 A Carry B Borrow 8 UP Down D0 D0 STB STB OE OE R D7 R D7 RESET µPD4702 µPD4704 CSL CSH The application circuits and their parameters are for references only and are not intended for use in actual design-in's. 10 µPD4704 RECOMMENDED SOLDERING CONDITIONS The following conditions (see table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. TYPES OF SURFACE MOUNT DEVICE For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (IEI-1207). µPD4704G Soldering process * Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 235 °C or below, Reflow time: 30 seconds or below (210 °C or higher), Number of reflow process: 2, Exposure limit*: None IR35-00-2 VPS Peak package’s surface temperature: 215 °C or below, Reflow time: 40 seconds or below (200 °C or higher), Number of reflow process: 2, Exposure limit*: None VP15-00-2 Wave soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or below, Number of flow process: 1, Exposure limit*: None WS60-00-1 Partial heating method Terminal temperature: 300 °C or below, Flow time: 10 seconds or below, Exposure limit*: None ● Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Note Do not apply more than a single process at once, except for “Partial heating method”. TYPES OF THROUGH HOLE MOUNT DEVICE µPD4704C Soldering process Wave soldering Soldering conditions Symbol Solder temperature: 260 °C or below, Flow time: 10 seconds or below REFERENCE Dcodument name Document No. NEC semiconductor device reliability/quality control system IEI-1212 Quality grade on NEC semiconductor devices IEI-1209 Semiconductor device mounting technology manual IEI-1207 Semiconductor device package manual IEI-1213 Guide to quality assurance for semiconductor devices MEI-1202 Semiconductor selection guide MF-1134 11 µPD4704 20PIN PLASTIC DIP (300 mil) 20 11 1 10 A K L P I J H C F D N R M B G M NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A B 25.40 MAX. 1.27 MAX. 1.000 MAX. 0.050 MAX. C 2.54 (T.P.) 0.100 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 1.1 MIN. 0.043 MIN. G H 3.5±0.3 0.51 MIN. 0.138±0.012 0.020 MIN. I J 4.31 MAX. 5.08 MAX. 0.170 MAX. 0.200 MAX. K 7.62 (T.P.) 0.300 (T.P.) L 6.4 0.252 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.25 0.01 P 0.9 MIN. 0.035 MIN. R 0~15° 0~15° P20C-100-300A,C-1 12 µPD4704 20 PIN PLASTIC SOP (300 mil) 20 11 P detail of lead end 1 10 A H J E K F G I C N D M L B M NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.00 MAX. 0.512 MAX. B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40 +0.10 –0.05 0.016 +0.004 –0.003 E 0.1±0.1 0.004±0.004 F 1.8 MAX. 0.071 MAX. G 1.55 0.061 H 7.7±0.3 0.303±0.012 I 5.6 0.220 J 1.1 0.043 K 0.20 +0.10 –0.05 0.008 +0.004 –0.002 L 0.6±0.2 0.024 +0.008 –0.009 M 0.12 0.005 N 0.10 0.004 P 3° +7° –3° 3° +7° –3° P20GM-50-300B, C-4 13 µPD4704 [MEMO] 14 µPD4704 [MEMO] 15 µPD4704 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5