DATA SHEET MOS INTEGRATED CIRCUIT µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 4-BIT SINGLE-CHIP MICROCONTROLLERS The µ PD750068 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing capability comparable to that of an 8-bit microcontroller. The µPD750068 provides more CPU functions compared to the 75X Series and realizes high-speed operation at the low voltage of 1.8 V, making it ideal for battery-driven applications. This device has on-chip A/D converters, and sophisticated timers capable of operating as a 16-bit timer. The µPD750068(A) has a higher reliability than the µPD750068. A version with on-chip one-time PROM, µPD75P0076, is also available for the evaluation during system development or for small-scale production. Detailed function descriptions are provided in the following user’s manual. Be sure to read the document before designing. µPD750068 User’s Manual: U10670E Features O O Low-voltage operation: VDD = 1.8 to 5.5 V On-chip memory • Program memory (ROM): 4096 × 8 bits ( µPD750064, 750064(A)) 6144 × 8 bits ( µPD750066, 750066(A)) 8192 × 8 bits ( µPD750068, 750068(A)) • Data memory (RAM): 512 × 4 bits O O O O Variable instruction execution time for high-speed operation and power-saved operation • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation) • 122 µs (@ 32.768-kHz operation) Internal low-voltage A/D converters (AVREF = 1.8 to 5.5 V) 8-bit resolution × 8 channels Small packages (shrink SOP, shrink DIP) Uses instructions of 75X Series for easy replacement Applications O O µPD750064, 750066, 750068 Cordless phones, audio-visual equipment, home appliances, office machines, fitness machines, meters, gas ranges, etc. µPD750064(A), 750066(A), 750068(A) Electrical equipment for automobiles The µPD750064, 750066, 750068 and µPD750064(A), 750066(A), 750068(A) differ only in quality grade. In this manual, the µ PD750068 is described as typical product unless otherwise specified. Users of other than the µPD750068 should read the µ PD750068 as referring to the pertinent product. When the description differs among the µPD750064, 750066, and 750068, they also refer to the pertinent (A) products. µPD750064 → µPD750064(A), µPD750066 → µPD750066(A), µPD750068 → µPD750068(A) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U10165EJ2V0DS00 (2nd edition) Date Published April 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1995 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Ordering Information Part Number Package Quality Grade µPD750064CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard µPD750064GT-××× 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Standard µPD750066CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard µPD750066GT-××× 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Standard µPD750068CU-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Standard µPD750068GT-××× 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Standard µPD750064CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special µPD750064GT(A)-××× 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Special µPD750066CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special µPD750066GT(A)-××× 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Special µPD750068CU(A)-××× 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Special µPD750068GT(A)-××× 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Special Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Differences between µ PD75006× and µ PD75006×(A) Part Number Item Quality grade 2 µPD750064 µPD750064(A) µPD750066 µPD750068 µPD750066(A) µPD750068(A) Standard Special Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Functional Outline Item Function • 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (@ 4.19-MHz operation with main system clock) • 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (@ 6.0-MHz operation with main system clock) • 122 µs (@ 32.768-kHz operation with subsystem clock) Instruction execution time On-chip memory ROM 4096 × 8 bits ( µPD750064) 6144 × 8 bits ( µPD750066) 8192 × 8 bits ( µPD750068) RAM 512 × 4 bits General-purpose register • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks Input/ output CMOS input 12 On-chip pull-up resistors can be specified by software: 7 Also used for analog input pins: 4 port CMOS input/output 12 On-chip pull-up resistors can be specified by software: 12 Also used for analog input pins: 4 N-ch open-drain 8 13 V withstand voltage input/output pins Total On-chip pull-up resistors can be specified by mask option 32 Timer 4 • • • channels 8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter) Basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel Serial interface • 3-wire serial I/O mode ··· MSB or LSB can be selected for transferring first bit • 2-wire serial I/O mode A/D converter 8-bit resolution × 8 channels (1.8 V ≤ AV REF ≤ V DD) Bit sequential buffer 16 bits Clock output (PCL) • Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19-MHz operation with main system clock) • Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0-MHz operation with main system clock) Buzzer output (BUZ) • 2 kHz, 4 kHz, 32 kHz (@ 4.19-MHz operation with main system clock or @ 32.768-kHz operation with subsystem clock) • 2.93 kHz, 5.86 kHz, 46.9 kHz (@ 6.0-MHz operation with main system clock) Vectored interrupt External: 3, Internal: 4 Test input External: 1, Internal: 1 System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation • Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Operating ambient temperature T A = –40 to +85˚C Power supply voltage VDD = 1.8 to 5.5 V Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) • 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Data Sheet U10165EJ2V0DS00 3 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) CONTENTS 1. PIN CONFIGURATION (Top View) ...................................................................................................... 6 2. BLOCK DIAGRAM ................................................................................................................................ 7 3. PIN FUNCTION ..................................................................................................................................... 8 3.1 Port Pins ...................................................................................................................................... 8 3.2 Non-port Pins ............................................................................................................................ 10 3.3 Pin Input/Output Circuits ......................................................................................................... 12 3.4 Recommended Connection of Unused Pins .......................................................................... 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 16 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................. 18 6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 23 6.1 Port ............................................................................................................................................. 23 6.2 Clock Generator ........................................................................................................................23 6.3 Subsystem Clock Oscillator Control Function ...................................................................... 25 6.4 Clock Output Circuit .................................................................................................................26 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 27 6.6 Watch Timer ..............................................................................................................................28 6.7 Timer/Event Counter .................................................................................................................29 6.8 Serial Interface .......................................................................................................................... 32 6.9 A/D Converter ............................................................................................................................ 33 6.10 Bit Sequential Buffer ................................................................................................................ 34 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 35 8. STANDBY FUNCTION ........................................................................................................................37 9. RESET FUNCTION .............................................................................................................................38 10. MASK OPTION ...................................................................................................................................41 11. INSTRUCTION SET ............................................................................................................................ 42 12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 55 13. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................. 68 14. PACKAGE DRAWINGS ...................................................................................................................... 70 15. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 72 4 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX A. µPD75068, 750068 AND 75P0076 FUNCTIONAL LIST .................................................. 73 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 75 APPENDIX C. RELATED DOCUMENTS ................................................................................................. 79 Data Sheet U10165EJ2V0DS00 5 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 1. PIN CONFIGURATION (Top View) • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD750064CU-×××, µPD750064CU(A)-××× µPD750066CU-×××, µPD750066CU(A)-××× µPD750068CU-×××, µPD750068CU(A)-××× • 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD750064GT-×××, µPD750064GT(A)-××× µPD750066GT-×××, µPD750066GT(A)-××× µPD750068GT-×××, µPD750068GT(A)-××× XT1 XT2 RESET X1 X2 P33 P32 P31 P30 AVSS P63/KR3/AN7 P62/KR2/AN6 P61/KR1/AN5 P60/KR0/AN4 P113/AN3 P112/AN2 P111/AN1 P110/AN0 AVREF IC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P40 P41 P42 P43 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ IC: Internally Connected (Connect pin directly to VDD). Pin Identification 6 AN0 to AN7 : Analog Input 0 to 7 P60 to P63 : Port 6 AVREF : Analog Reference P110 to P113 : Port 11 AVSS : Analog Ground PCL : Programmable Clock BUZ : Buzzer Clock PTO0, PTO1 : Programmable Timer Output 0, 1 IC : Internally Connected RESET : Reset Input INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 SB0, SB1 : Serial Data Bus 0, 1 INT2 : External Test Input 2 SCK : Serial Clock KR0 to KR3 : Key Return 0 to 3 SI : Serial Input P00 to P03 : Port 0 SO : Serial Output P10 to P13 : Port 1 TI0, TI1 : Timer Input 0, 1 P20 to P23 : Port 2 VDD : Positive Power Supply P30 to P33 : Port 3 VSS : Ground P40 to P43 : Port 4 X1, X2 : Main System Clock Oscillation 1, 2 P50 to P53 : Port 5 XT1, XT2 : Subsystem Clock Oscillation 1, 2 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 2. BLOCK DIAGRAM Basic interval timer/watchdog timer SP (8) INTBT BUZ/P23 INTW TI0/P13 PTO0/P20 TI1/P12/INT2 PTO1/P21 INTW INTT0 8-bit timer/ event counter#0 BANK Cascaded 16-bit timer/ event counter INTT1 General reg. Program memoryNote (ROM) Data memory (RAM) 512 × 4 bits SI/SB1/P03 SO/SB0/P02 P00 to P03 Port 1 4 P10 to P13 Port 2 4 P20 to P23 Port 3 4 P30 to P33 Port 4 4 P40 to P43 Port 5 4 P50 to P53 Port 6 4 P60 to P63 Port 11 4 P110 to P113 SBS Program counter 8-bit timer/ event counter#1 4 CY ALU Watch timer Port 0 Clocked serial interface SCK/P01 INTCSI TOUT0 INT1/P11 INT4/P00 Interrupt control INT2/P12/TI1 KR0/P60 to 4 KR3/P63 CPU Clock Φ fx/2N Clock output control AN0/P110 to 4 AN3/P113 AN4/P60 to 4 AN7/P63 Bit seq. buffer (16) Decode and control INT0/P10 A/D converter PCL/P22 System clock generator Sub Main Clock divider XT1 XT2 X1 X2 Stand by control IC VDD VSS RESET AVREF AVSS Note The ROM capacity varies depending on the product. Data Sheet U10165EJ2V0DS00 7 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3. PIN FUNCTION 3.1 Port Pins (1/2) Input/Output Alternate Function P00 Input INT4 P01 Input/Output SCK P02 Input/Output SO/SB0 P03 Input/Output SI/SB1 P10 Input INT0 Pin Name P11 INT1 P12 TI1/INT2 P13 TI0 P20 Input/Output PTO0 P21 PTO1 P22 PCL P23 BUZ P30 to P33 Function 4-bit input port (PORT0). For P01 to P03, connection of on-chip pullup resistors can be specified by software in 3-bit units. 8-bit I/O After Reset I/O Circuit TypeNote 1 No Input <B> <F>-A <F>-B <M>-C 4-bit input port (PORT1). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. P10/INT0 can select noise elimination circuit. No Input <B>-C 4-bit input/output port (PORT2). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. No Input E-B Input/Output – Programmable 4-bit input/output port (PORT3). This port can be specified for input/output in 1-bit units. Connection of on-chip pull-up resistor can be specified by software in 4-bit units. No Input E-B P40 to P43Note 2 Input/Output – N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be contained in 1-bit units (mask option). Withstand voltage is 13 V in open-drain mode. Yes High level (when pull-up resistors are provided) or highimpedance M-D P50 to P53Note 2 Input/Output – N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained in 1-bit units (mask option). Withstand voltage is 13 V in open-drain mode. High level (when pull-up resistors are provided) or highimpedance M-D Notes 1. 2. Circuit types enclosed in brackets indicate the Schmitt trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed. 8 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.1 Port Pins (2/2) Pin Name P60 Input/Output Alternate Function Input/Output KR0/AN4 P61 KR1/AN5 P62 KR2/AN6 P63 KR3/AN7 P110 Input AN0 P111 AN1 P112 AN2 P113 AN3 Note 8-bit I/O After Reset I/O Circuit Type Note Programmable 4-bit input/output port (PORT6). This port can be specified for input/output in 1-bit units. Connection of on-chip pull-up resistors can be specified by software in 4-bit units. No Input <Y>-D 4-bit input port (PORT11). No Input Y-A Function Circuit types enclosed in brackets indicate the Schmitt trigger input. Data Sheet U10165EJ2V0DS00 9 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.2 Non-port Pins (1/2) Pin Name TI0 Input/Output Alternate Function Input P13 TI1 P12/INT2 PTO0 Output P20 After Reset I/O Circuit Type Note Inputs external event pulses to the timer/event counter. Input <B>-C Timer/event counter output Input E-B Input <F>-A Function PTO1 P21 PCL P22 Clock output BUZ P23 Optional frequency output (for buzzer output or system clock trimming) Input/Output P01 Serial clock input/output SO Output P02 Serial data output SB0 Input/Output SCK SI Input <F>-B Serial data bus input/output P03 Serial data input <M>-C SB1 Input/Output INT4 Input P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) INT0 Input P10 Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 can select noise elimination circuit. INT1 Serial data bus input/output P11 INT2 Input P12/TI1 KR0 to KR3 Input P60/AN4 to Input <B>-C Input <B>-C Falling edge detection testable input Input <Y>-D Analog signal input Input Y-A Rising edge detection testable input Noise elimination circuit/asynchronous selection <B> Asynchronous Asynchronous P63/AN7 AN0 to AN3 Input AN4 to AN7 P110 to P113 P60/KR0 to P63/KR3 <Y>-D AV REF – – A/D converter reference voltage – Z-N AV SS – – A/D converter reference GND potential – Z-N Note 10 Circuit types enclosed in brackets indicate the Schmitt trigger input. Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.2 Non-port Pins (2/2) Input/Output Alternate Function Function After Reset I/O Circuit Type Note X1 Input – Crystal/ceramic connection pin for the main system clock oscillation. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. – – X2 – – Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. – – Input – System reset input (low-level active) – <B> IC – – Internally connected. Connect directly to VDD. – – V DD – – Positive power supply – – V SS – – Ground potential – – Pin Name XT1 Input XT2 – RESET Note Circuit types enclosed in brackets indicate the Schmitt trigger input. Data Sheet U10165EJ2V0DS00 11 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.3 Pin Input/Output Circuits The µPD750068 pin input/output circuits are shown schematically. (1/3) TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch output disable N-ch Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off). CMOS standard input buffer TYPE E-B TYPE B VDD P.U.R. P.U.R. enable P-ch data IN Type D IN/OUT output disable Type A Schmitt-triggered input with hysteresis characteristics P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-C VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data output disable IN/OUT Type D IN Type B P.U.R. : Pull-Up Resistor 12 P.U.R. : Pull-Up Resistor Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) (2/3) TYPE F-B TYPE Y VDD P.U.R. P.U.R. enable P-ch output disable (P) VDD VDD IN P-ch N-ch + – VDD Sampling C P-ch IN/OUT AVSS data output disable N-ch input enable output disable (N) AVSS Reference voltage (from the voltage tap of the series resistor string) P.U.R. : Pull-Up Resistor TYPE M-C TYPE Y-A VDD P.U.R. IN instruction P.U.R. enable P-ch IN/OUT Type A Input butfer data N-ch IN output disable Type Y P.U.R. : Pull-Up Resistor TYPE M-D VDD P.U.R. (Mask Option) IN/OUT data output disable Input instruction N-ch (+13 V withstand voltage) VDD P-ch P.U.R.Note Voltage limitation (+13 V circuit withstand voltage) Note This pull-up resistor operates only when an input instruction is executed without a pull-up resistor connected using the mask option (current flows from VDD to the pin when the pin is low). Data Sheet U10165EJ2V0DS00 13 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) (3/3) TYPE Y-D TYPE Z-N VDD AVREF P.U.R. P.U.R. enable P-ch data output disable IN/OUT Type D Reference voltage Type B ADEN N-ch Type Y AVSS P.U.R.: Pull-Up Resistor 14 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin Recommended Connection P00/INT4 Connect to VSS or V DD. P01/SCK Independently connect to VSS or VDD via a resistor. P02/SO/SB0 P03/SI/SB1 Connect to VSS. P10/INT0, P11/INT1 Connect to VSS or V DD. P12/TI1/INT2 P13/TI0 P20/PTO0 Input state: Independently connect to VSS or VDD via a resistor. P21/PTO1 Output state: Leave open. P22/PCL P23/BUZ P30 to P33 P40 to P43 Connect to VSS (do not connect a pull-up resistor P50 to P53 of mask option). P60/KR0/AN4 to P63/KR3/AN7 Input state: Output state: P110/AN0 to P113/AN3 Independently connect to VSS or VDD via a resistor. Leave open. Connect directly to VSS or V DD. XT1 Note Connect to VSS. XT2 Note Leave open. IC Connect directly to VDD. AV REF Connect to VSS. AV SS Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor). Data Sheet U10165EJ2V0DS00 15 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode The CPU of the µPD750068 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). • Mk I mode: Upward compatible with µPD75068. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. • Mk II mode: Incompatible with µPD75068. Can be used in all the 75XL CPUs including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 Kbytes. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility. 16 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100×BNote at the beginning of a program. When using the Mk II mode, it must be initialized to 000×BNote. Note Set the desired value in the × position. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. Data Sheet U10165EJ2V0DS00 17 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 5. MEMORY CONFIGURATION Program memory (ROM) .... 4096 × 8 bits (µPD750064) .... 6144 × 8 bits (µPD750066) .... 8192 × 8 bits (µPD750068) • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. • Addresses 0002H to 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. • Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. Data memory (RAM) • Data area .... 512 words × 4 bits (000H to 1FFH) • Peripheral hardware area .... 128 words × 4 bits (F80H to FFFH) 18 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-1. Program Memory Map (µPD750064) Address 7 6 0 0 0 H MBE RBE 0 0 2 H MBE RBE 0 0 4 H MBE RBE 0 0 6 H MBE RBE 0 0 8 H MBE RBE 0 0 A H MBE RBE 0 0 C H MBE RBE 5 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 4 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 4 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 4 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 4 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 4 bits) INTT0 start address (low-order 8 bits) INTT1 start address (high-order 4 bits) INTT1 start address (low-order 8 bits) CALLF ! faddr instruction entry address 020H GETI instruction reference table Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address –15 to –1, +2 to +16 BRCB !caddr instruction branch address 07FH 080H Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10165EJ2V0DS00 19 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-2. Program Memory Map (µPD750066) Address 7 6 0 0 0 0 H MBE RBE 0 0 0 2 H MBE RBE 0 0 0 4 H MBE RBE 0 0 0 6 H MBE RBE 0 0 0 8 H MBE RBE 0 0 0 A H MBE RBE 0 0 0 C H MBE RBE 5 0 0 0 0 0 0 0 0 Internal reset start address (high-order 5 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 5 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 5 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 5 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 5 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 5 bits) INTT0 start address (low-order 8 bits) INTT1 start address (high-order 5 bits) INTT1 start address (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR ! addr, BRA ! addr1Note or CALLA ! addr1Note instruction CALL ! addr instruction subroutine entry address BR $ addr instruction relative branch address –15 to –1, +2 to +16 BRCB ! caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 17FFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 20 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-3. Program Memory Map (µPD750068) Address 7 6 0 0 0 0 H MBE RBE 0 0 0 2 H MBE RBE 0 0 0 4 H MBE RBE 0 0 0 6 H MBE RBE 0 0 0 8 H MBE RBE 0 0 0 A H MBE RBE 0 0 0 C H MBE RBE 5 0 0 0 0 0 0 0 0 Internal reset start address (high-order 5 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 5 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 5 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 5 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 5 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 5 bits) INTT0 start address (low-order 8 bits) INTT1 start address (high-order 5 bits) INTT1 start address (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR ! addr, BRA ! addr1Note or CALLA ! addr1Note instruction CALL ! addr instruction subroutine entry address BR $ addr instruction relative branch address –15 to –1, +2 to +16 BRCB ! caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1FFFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10165EJ2V0DS00 21 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-4. Data Memory Map Data memory 000H General-purpose register area Memory bank (32 × 4) 01FH 020H 256 × 4 0 (224 × 4) Note Stack area Data area static RAM (512 × 4) 0FFH 100H 256 × 4 1 1FFH Not incorporated F80H 128 × 4 Peripheral hardware area FFFH Note 22 Memory bank 0 or 1 can be selected as the stack area. Data Sheet U10165EJ2V0DS00 15 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6. PERIPHERAL HARDWARE FUNCTION 6.1 Port The following three types of I/O ports are available. • CMOS input (PORT0, 1, 11) : 12 • CMOS input/output (PORT2, 3, 6) : 12 • N-ch open-drain input/output (PORT4, 5) :8 Total 32 Table 6-1. Types and Features of Digital Ports Port Name PORT0 Function 4-bit input PORT1 Operation and Features When the serial interface function is used, the alternate-function Also used for the INT4, SCK, pins function as output ports depending on the operation mode. SO/SB0, SI/SB1 pins. 4-bit input only port. Also used for the INT0 to INT2/TI1, TI0 pins. PORT2 4-bit input/output Can be set to input mode or output mode in 4-bit units. PORT3 Can be set to input mode or output mode in 1-bit units. PORT4 PORT5 4-bit input/output (N-ch open drain, 13 V withstand voltage) Remarks Can be set to input mode or output mode in 4-bit units. On-chip pull-up resistor can be specified in 1-bit units by mask option. Also used for the PTO0, PTO1, PCL, BUZ pins. – Ports 4 and 5 are paired and data can be input/ output in 8-bit units. PORT6 4-bit input/output Can be set to input mode or output mode in 1-bit units. Also used for the KR0 to KR3, AN4 to AN7 pins. PORT11 4-bit input Also used for the AN0 to AN3 pins. 4-bit input only port. 6.2 Clock Generator The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Figure 6-1 shows the configuration of the clock generator. Operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). Two types of system clocks are available; main system clock and subsystem clock. The instruction execution time can be changed. • 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (@ 4.19-MHz operation with main system clock) • 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (@ 6.0-MHz operation with main system clock) • 122 µs (@ 32.768-kHz operation with subsystem clock) Data Sheet U10165EJ2V0DS00 23 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · INT0 noise eliminator · Clock output circuit XT1 XT2 Subsystem clock oscillator fXT Main system clock oscillator fX Watch timer X1 X2 1/1 to 1/4096 Divider 1/2 1/4 1/16 Selector WM.3 SCC Oscillation stop Divider SCC3 Selector 1/4 Internal bus SCC0 Φ · CPU · INT0 noise eliminator · Clock output circuit PCC PCC0 PCC1 4 HALT F/F PCC2 S HALTNote PCC3 STOPNote R PCC2, PCC3 Clear STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 24 fX = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor Clock Control Register 5. SCC: System Clock Control Register 6. One clock cycle (t CY) of the CPU clock is equal to one machine cycle of the instruction. Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.3 Subsystem Clock Oscillator Control Function The subsystem clock oscillator of the µPD750068 has the following two control functions to decrease the supply current. • Selects by software whether an internal feedback resistor is to be used or notNote. • Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD ≥ 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor) by software, connect XT1 to VSS, and open XT2. This makes it possible to reduce the current consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 Data Sheet U10165EJ2V0DS00 25 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PCL pin to the remote control wave output applications and peripheral LSIs. • Clock output (PCL) : Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19-MHz operation) : Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0-MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator Φ Output buffer fX/22 Selector fX/24 PCL/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 26 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (d) Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear Clear fX/25 fX/27 MPX Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution Data Sheet U10165EJ2V0DS00 27 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.6 Watch Timer The µPD750068 has one channel of watch timer. The watch timer has the following functions. (a) Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. (b) 0.5 sec interval can be created by both the main system clock (4.194304 MHz) and subsystem clock (32.768 kHz). (c) Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. (d) Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of system clock frequencies. (e) Clears the frequency divider to make the clock start with zero seconds. (f) Uses the clock of 0.5 sec as the clock source of the timer/event counter to continue the standby mode until the longest time 9 hours (by using timer 0, 1) to be in the lowest consumption mode. Figure 6-5. Watch Timer Block Diagram fW (256 Hz : 3.91 ms) 27 From clock generator fX 128 (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Divider fW 214 2 Hz 0.5 sec 4 kHz 2 kHz fW fW 23 24 Selector INTW IRQW set signal Clear Selector Output buffer P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch PMGB bit 2 Port 2 input/ output mode Bit test instruction Internal bus Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz. 28 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.7 Timer/Event Counter The µPD750068 has two channels of timer/event counters. Its configuration is shown in Figures 6-6 and 6-7. The timer/event counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to the PTOn pin (n = 0, 1) (c) Event counter operation (d) Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). (e) Supplies the shift clock to the serial interface circuit. (f) Reads the count value. The timer/event counter operates in the following two modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Yes Yes Mode 8-bit timer/event counter mode 16-bit timer/event counter mode Data Sheet U10165EJ2V0DS00 Yes 29 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 6-6. Timer/Event Counter Block Diagram (Channel 0) Internal bus 8 – TM0 TOE0 8 TM06 TM05 TM04 TM03 TM02 TM01 TM00 TMOD0 Modulo register (8) Decoder TO enable flag PORT2.0 PMGB bit 2 Port 2 input/ output mode P20 output latch 8 PORT1. 3 Comparator (8) Match TOUT P20/PTO0 Output buffer F/F Input buffer 8 Reset TOUT0 TI0/P13 Watch timer (INTW) output fX/22 4 From clock fX/26 fX/2 generator fX/28 fX/210 MPX CP T0 Count register (8) Overflow Clear Timer/event counter (channel 1) clock input INTT0 (IRQT0 set signal) 16-bit timer/event counter mode IRQT0 clear signal Timer operation start RESET Timer/event counter (channel 1) TM12 signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode) 30 To serial interface Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 6-7. Timer/Event Counter Block Diagram (Channel 1) Internal bus 8 – 8 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TO enable flag TMOD1 Decoder PORT1.2 PORT2.1 TOE1 TM1 P21 output latch PMGB bit 2 Port 2 input/output mode Modulo register (8) 8 Input buffer Comparator (8) TI1/P12/INT2 8 Timer/event counter output (channel 0) fX/22 fX/26 From clock fX/28 generator fX/210 fX/212 TOUT F/F P21/PTO1 Output buffer Reset Count register (8) CP MPX T1 Match Clear RESET Timer operation start 16 bit timer/event counter mode IRQT1 clear signal Selector INTT1 IRQT1 set signal Timer/event counter (channel 0) TM02 signal (When 16-bit timer/event counter mode) Timer/event counter (channel 0) match signal/operation start (When 16-bit timer/event counter mode) Timer/event counter (channel 0) comparator (When 16-bit timer/event counter mode) Data Sheet U10165EJ2V0DS00 31 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.8 Serial Interface The serial interface has the following three modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode The 3-wire serial I/O mode enables connections to be made with the 75X Series, 78K Series, and many other types of I/O devices. The 2-wire serial I/O mode enables communication with two or more devices. Figure 6-8. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 8 Bit manipulation CSIM SBIC RELT CMDT Selector P03/SI/SB1 SO latch SET CLR Shift register (SIO) (8) D Q Selector P02/SO/SB0 P01/SCK Serial clock counter P01 Output latch Serial clock control circuit INTCSI control circuit INTCSI IRQCSI set signal Serial clock selector External SCK 32 Data Sheet U10165EJ2V0DS00 f X/23 f X/24 f X/26 TOUT0 From timer/event counter 0 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.9 A/D Converter The µPD750068 incorporates the 8-bit resolution A/D converter which has eight channels analog input pins (AN0 to AN7). This A/D converter is a successive approximation type. Figure 6-9. A/D Converter Block Diagram Internal bus 8 ADEN ADM6 ADM5 ADM4 SOC EOC 0 0 8 Controller AN0/P110 Sample hold circuit AN1/P111 AN2/P112 + AN3/P113 Multiplexer SA register (8) – AN4/P60/KR0 Comparator AN5/P61/KR1 AN6/P62/KR2 8 AN7/P63/KR3 Tap decoder AVREF R/2 R R R R/2 AVSS ADEN Data Sheet U10165EJ2V0DS00 33 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.10 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-10. Bit Sequential Buffer Format Address FC3H 3 Bit Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH FC1H 1 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H L = 4H L = 3H DECS L 2 1 0 BSB0 L = 0H INCS L Remarks 1. 2. 34 In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD750068 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge detection testable inputs. The interrupt control circuit of the µPD750068 has the following functions. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software. • Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQ×××) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. Data Sheet U10165EJ2V0DS00 35 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IM2 IM1 IM0 IME IPS IST1 IST0 Interrupt enable flag (IE××× ) Decoder INTBT Both edge detector INT0/P10 Note Selector INT4/P00 Edge detector INT2/P12 KR0/P60 KR3/P63 Rising edge detector VRQn IRQ4 IRQ0 Edge detector INT1/P11 IRQBT IRQ1 INTCSI IRQCSI INTT0 IRQT0 INTT1 IRQT1 INTW IRQW Selector Priority control circuit IRQ2 Standby release signal Falling edge detector IM2 Note 36 Vector table address generator Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.) Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 8. STANDBY FUNCTION In order to save power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD750068. Table 8-1. Operation Status in Standby Mode Mode Item STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Settable only when the main system clock is used. Settable both by the main system clock and subsystem clock. Operation status Clock generator The main system clock stops oscillation. Only the CPU clock Φ halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops. Operable only when the main system clock is oscillated (The IRQBT is set in the reference time interval). Serial interface Operable only when an external SCK input is selected as the serial clock. Operable only when an external SCK input is selected as the serial clock or when the main system clock is oscillated. Timer/event counter Operable only when a signal input to the TI0 and TI1 pins or a watch timer which selected fXT is specified as the count clock. Operable only when a signal input to the TI0 and TI1 pins or a watch timer which selected fXT is specified as the count clock or when the main system clock is oscillated. Watch timer Operable when fXT is selected as the count clock. Operable. A/D converter Operation stops. Operable only when the main system clock is oscillated. External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operatedNote. CPU Operation stops. Release signal Note • Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. • Test request signal sent from the test source enabled by the test enable flag • RESET signal generation Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). Data Sheet U10165EJ2V0DS00 37 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 9. RESET FUNCTION There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the configuration of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus When the RESET signal is generated, each hardware is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation WaitNote RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms: @6.0-MHz operation, 31.3 ms: @4.19-MHz operation) 2 15/fX (5.46 ms: @6.0-MHz operation, 7.81 ms: @4.19-MHz operation) 38 Data Sheet U10165EJ2V0DS00 Operation mode µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Table 9-1. Status of Each Hardware After Reset (1/2) RESET Signal Generation in Standby Mode RESET Signal Generation in Operation Sets the low-order 4 bits of program memory’s address 0000H to the PC11 to PC8 and the contents of address 0001H to the PC7 to PC0. Sets the low-order 4 bits of program memory’s address 0000H to the PC11 to PC8 and the contents of address 0001H to the PC7 to PC0. µPD750066, Sets the low-order 5 bits of 750068 program memory’s address 0000H to the PC12 to PC8 and the contents of address 0001H to the PC7 to PC0. Sets the low-order 5 bits of program memory’s address 0000H to the PC12 to PC8 and the contents of address 0001H to the PC7 to PC0. Hardware Program counter (PC) PSW µPD750064 Carry flag (CY) Held Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Bank enable flag (MBE, RBE) Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Stack pointer (SP) Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Stack bank select register (SBS) Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Watch timer Mode register (WM) Data Sheet U10165EJ2V0DS00 39 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Table 9-1. Status of Each Hardware After Reset (2/2) Hardware RESET Signal Generation in Standby Mode RESET Signal Generation in Operation Shift register (SIO) Held Undefined Operation mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 0 0 Mode register (ADM) 04H 04H SA register (SA) 7FH 7FH Reset (0) Reset (0) Serial interface Sub-oscillator control register (SOS) A/D converter Interrupt Interrupt request flag (IRQ×××) function Interrupt enable flag (IE×××) 0 0 Interrupt priority selection register (IPS) 0 0 INT0, 1, 2 mode registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, PMGB) 0 0 Pull-up resistor setting register (POGA) 0 0 Held Undefined Digital port Bit sequential buffer (BSB0 to BSB3) 40 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 10. MASK OPTION The µPD750068 has the following mask options. • Mask option of P40 to P43 and P50 to P53 Can select whether to incorporate the pull-up resistor. (1) The pull-up resistor is incorporated in 1-bit units. (2) The pull-up resistor is not incorporated. • Mask option of standby function Can select the wait time with the RESET signal. (1) 2 17/fX (21.8 ms at fX = 6.0 MHz, 31.3 ms at f X = 4.19 MHz) (2) 2 15/fX (5.46 ms at fX = 6.0 MHz, 7.81 ms at f X = 4.19 MHz) • Mask option of subsystem clock Can select whether to enable the internal feedback resistor. (1) The internal feedback resistor is enabled (switch internal feedback resistor ON/OFF by software). (2) The internal feedback resistor is disabled (disconnect internal feedback resistor by hardware). Data Sheet U10165EJ2V0DS00 41 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to “RA75X Assembler Package User’s Manual——Language (U12385E)”. If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are described as they are. For immediate data, appropriate numbers or labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see µPD750068 User’s Manual (U10670E). Expression Format reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 rp2 rp' rp'1 BC, BC, XA, BC, rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr, addr1 (Mk II mode only) caddr faddr 0000H to 0FFFH 0000H to 17FFH 0000H to 1FFFH 12-bit immediate 11-bit immediate taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IE××× RBn MBn PORT0 to PORT6, PORT11 IEBT, IET0, IET1, IE0 to IE2, IE4, IECSI, IEW RB0 to RB3 MB0, MB1, MB15 Note 42 Description Method DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' immediate data or label (µPD750064) immediate data or label ( µPD750066) immediate data or label (µPD750068) data or label data or label mem can be only used for even address in 8-bit data processing. Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) (2) Legend in explanation of operation A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA’ : XA’ expanded register pair BC’ : BC’ expanded register pair DE’ : DE’ expanded register pair HL’ : HL’ expanded register pair PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 6, 11) IME : Interrupt master enable flag IPS : Interrupt priority selection register IE××× : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (××) : The contents addressed by ×× ××H : Hexadecimal data Data Sheet U10165EJ2V0DS00 43 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) (3) Explanation of symbols under addressing area column *1 MB = MBE•MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 0000H to 0FFFH (µPD750064) 0000H to 17FFH (µPD750066) 0000H to 1FFFH (µPD750068) *7 addr, addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H 0000H 1000H 1000H to to to to 0FFFH 0FFFH 17FFH 1FFFH (µPD750064) (PC12 = 0: µPD750066, 750068) (PC12 = 1: µPD750066) (PC12 = 1: µPD750068) *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH *11 Mk II mode only addr1 = 0000H to 0FFFH (µPD750064) 0000H to 17FFH (µPD750066) 0000H to 1FFFH (µPD750068) Remarks 1. Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle (= tCY) of CPU clock Φ; time can be selected from among four types by setting PCC. 44 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Transfer Mnemonic MOV XCH Number of Bytes Number of Machine Cycles A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' Operand Operation Data Sheet U10165EJ2V0DS00 Addressing Area Skip Condition String effect A 45 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Table reference Mnemonic MOVT Operand XA, @PCDE Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition µPD750064 XA ← (PC11–8+DE)ROM µPD750066, 750068 XA ← (PC12–8+DE)ROM XA, @PCXA 1 3 µPD750064 XA ← (PC11–8+XA)ROM µPD750066, 750068 XA ← (PC12–8+XA)ROM Bit transfer Operation MOV1 ADDS ADDC SUBS SUBC Note XA, @BCDE 1 3 XA ← (BCDE)ROMNote *6 XA, @BCXA 1 3 XA ← (BCXA)ROMNote *6 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) XA, rp' 2 2+S XA ← XA+rp' carry rp'1, XA 2 2+S rp'1 ← rp'1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp' 2 2 XA, CY ← XA+rp'+CY rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp' 2 2+S XA ← XA–rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp' 2 2 XA, CY ← XA–rp'–CY rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY carry *1 *1 borrow *1 Set “0” to register B if the µPD750064 is used. Only low-order one bit of register B will be valid if the µPD750066, 750068 is used. 46 *1 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Operation Number of Bytes Number of Machine Cycles A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) XA, rp' 2 2 XA ← XA ∧ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∧ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp' 2 2 XA ← XA ∨ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp' 2 2 XA ← XA v rp' rp'1, XA 2 2 rp'1 ← rp'1 v XA RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A INCS reg 1 1+S reg ← reg+1 reg = 0 rp1 1 1+S rp1 ← rp1+1 rp1 = 00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg–1 reg = FH rp' 2 2+S rp' ← rp'–1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic AND OR XOR Accumulator manipulation Increment and Decrement DECS Comparison Carry flag manipulation SKE Operand Operation Skip if CY = 1 Addressing Area Skip Condition *1 *1 *1 CY = 1 CY ← CY Data Sheet U10165EJ2V0DS00 47 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Memory bit manipulation Mnemonic SET1 CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 48 Number of Bytes Number of Machine Cycles mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=0 *1 (@H+mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY v (H+mem3–0.bit) *1 Operand Operation Data Sheet U10165EJ2V0DS00 Addressing Area Skip Condition µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Branch Mnemonic BRNote Operand addr Number of Bytes Number of Machine Cycles – – Operation µPD750064 PC11–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. Addressing Area Skip Condition *6 µPD750066, 750068 PC12–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. addr1 – – µPD750064 PC11-0 ← addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 µPD750066, 750068 PC12–0 ← addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. ! addr 3 3 µPD750064 PC11–0 ← addr *6 µPD750066, 750068 PC12–0 ← addr $addr 1 2 µPD750064 PC11–0 ← addr *7 µPD750066, 750068 PC12–0 ← addr $addr1 1 2 µPD750064 PC11–0 ← addr1 µPD750066, 750068 PC12–0 ← addr1 Note The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10165EJ2V0DS00 49 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Branch Mnemonic BR Operand Number of Bytes Number of Machine Cycles 2 3 PCDE Operation Addressing Area Skip Condition µPD750064 PC11–0 ← PC11-8+DE µPD750066, 750068 PC12–0 ← PC12-8+DE PCXA 2 3 µPD750064 PC11–0 ← PC11-8+XA µPD750066, 750068 PC12–0 ← PC12-8+XA BCDE 2 3 µPD750064 PC11–0 ← BCDENote 1 *6 µPD750066, 750068 PC12–0 ← BCDENote 2 BCXA 2 3 µPD750064 PC11–0 ← BCXANote 1 *6 µPD750066, 750068 PC12–0 ← BCXANote 2 BRANote 3 3 3 µPD750064 PC11–0 ← addr1 *11 µPD750066, 750068 PC12–0 ← addr1 BRCB !caddr 2 2 µPD750064 PC11–0 ← caddr11–0 *8 µPD750066, 750068 PC12–0 ← PC12+caddr11–0 Subroutine stack control CALLANote 3 !addr1 3 3 µPD750064 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr1, SP ← SP–6 *11 µPD750066, 750068 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 PC12–0 ← addr1, SP ← SP–6 Notes 1. 2. 3. “0” must be set to B register. Only low-order one bit is valid in B register. The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 50 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Subroutine stack control Mnemonic CALLNote Operand !addr Number of Bytes Number of Machine Cycles 3 3 Operation µPD750064 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← addr, SP ← SP–4 Addressing Area Skip Condition *6 µPD750066, 750068 (SP–3) ← MBE, RBE, 0, PC12 (SP–4) (SP–1) (SP–2) ← PC11–0 PC12–0 ← addr, SP ← SP–4 4 µPD750064 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr, SP ← SP–6 µPD750066, 750068 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 PC12–0 ← addr, SP ← SP–6 CALLFNote !faddr 2 2 µPD750064 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← 0+faddr, SP ← SP–4 *9 µPD750066, 750068 (SP–3) ← MBE, RBE, 0, PC12 (SP–4) (SP–1) (SP–2) ← PC11–0 PC12–0 ← 00+faddr, SP ← SP–4 3 µPD750064 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← 0+faddr, SP ← SP–6 µPD750066, 750068 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 PC12–0 ← 00+faddr, SP ← SP–6 Note The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10165EJ2V0DS00 51 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Subroutine stack control Mnemonic RETNote Operand Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition µPD750064 PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4 µPD750066, 750068 PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, PC12 ← (SP+1), SP ← SP+4 µPD750064 ×, ×, MBE, RBE ← (SP+4) 0, 0, 0, 0, ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 µPD750066, 750068 ×, ×, MBE, RBE ← (SP+4) MBE, 0, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 RETSNote 1 3+S µPD750064 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally Unconditional µPD750066, 750068 MBE, RBE, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally µPD750064 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) ×, ×, MBE, RBE ← (SP+4) SP ← SP+6 then skip unconditionally µPD750066, 750068 0, 0, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) ×, ×, MBE, RBE ← (SP+4) SP ← SP+4 then skip unconditionally Note The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 52 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Subroutine stack control Mnemonic Operand RETINote 1 Number of Bytes Number of Machine Cycles 1 3 Addressing Area Operation Skip Condition µPD750064 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 µPD750066, 750068 MBE, RBE, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 µPD750064 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 µPD750066, 750068 0, 0, 0, PC12 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1) (SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn+1, PORTn PORTn, A 2 2 PORTn ← A PORTn, XA 2 2 PORTn+1, PORTn ← XA HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0, 1, 15) PUSH POP Interrupt control EI IE××× DI Input/output IN Note 2 OUTNote 2 CPU control Special SEL Notes 1. (n = 0-6, 11) (n = 4) (n = 2-6) (n = 4) The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and MBS must be set to 15. Data Sheet U10165EJ2V0DS00 53 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Group Mnemonic GETINotes 1, 2 Special Operand taddr Number of Bytes Number of Machine Cycles 1 3 Operation µPD750064 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) Addressing Area Skip Condition *10 –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, 0 PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction µPD750066, 750068 • When TBR instruction PC12–0 ← (taddr) 4–0 + (taddr+1) –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, PC12 PC12–0 ← (taddr) 4–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 µPD750064 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––––––– 4 3 • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 µPD750066, 750068 • When TBR instruction PC12–0 ← (taddr) 4–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––––––– Notes 1. ––––––––––––– ––––––––––––– Depending on the reference instruction ––––––––––––– • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, PC12 (SP–2) ← ×, ×, MBE, RBE PC12–0 ← (taddr) 4–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––––––– 3 *10 • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← ×, ×, MBE, RBE PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––––––– 4 Depending on the reference instruction • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ––––––––––––– Depending on the reference instruction The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 2. The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 54 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Conditions Supply voltage V DD Input voltage V I1 Other than ports 4, 5 V I2 Ports 4, 5 Pull-up resistor provided N-ch open drain Ratings Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V –0.3 to +14 V Output voltage VO Output current, high IOH –0.3 to VDD + 0.3 V Per pin –10 mA Output current, low I OL Total of all pins –30 mA Per pin 30 mA Operating ambient temperature TA 220 mA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Total of all pins Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25˚C, VDD = 0 V) Parameter Input capacitance Symbol Conditions CIN f = 1 MHz Output capacitance COUT Unmeasured pins returned to 0 V I/O capacitance CIO Data Sheet U10165EJ2V0DS00 MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 55 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Main System Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Resonator Recommended Constants Parameter Ceramic resonator Conditions Oscillation frequency (fX)Note 1 X1 TYP. 1.0 MAX. Unit 6.0Note 2 MHz X2 C1 C2 Crystal resonator Oscillation stabilization timeNote 3 After VDD reaches oscillation voltage range MIN. value Oscillation frequency (fX)Note 1 X1 MIN. 4 1.0 ms 6.0Note 2 MHz X2 C1 C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 10 ms 30 External clock X1 Notes 1. X1 input frequency (fX)Note 1 1.0 X1 input high-/ low-level width (tXH, t XL) 83.3 6.0Note 2 MHz X2 500 ns The oscillation frequency and X1 input frequency shown above indicate only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, do not select the processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle time is less than 0.95 µs, falling short of the rated value of 0.95 µs. 3. The oscillation stabilization time is the time required to stabilize oscillation after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 56 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Subsystem Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Resonator Recommended Constants Crystal resonator Parameter Conditions Oscillation frequency (f XT)Note 1 XT1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s XT2 R C3 C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V 10 External clock XT1 Notes 1. XT1 input frequency (f XT)Note 1 32 100 kHz XT1 input high-/ low-level width (t XTH, tXTL) 5 15 µs XT2 The oscillation frequency and XT1 input frequency shown above indicate only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The oscillation stabilization time is the time required to stabilize oscillation after VDD has been applied. Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Data Sheet U10165EJ2V0DS00 57 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Recommended Oscillator Constant Ceramic resonator (TA = –40 to +85˚C) Manufacturer Murata Mfg. Co., Ltd. Part Number Frequency (MHz) C1 C2 MIN. MAX. 1.0 100 100 2.0 5.5 CSA2.00MG040 2.0 100 100 2.3 – – CSA4.19MG 4.19 30 30 – – CSA4.19MGU 30 30 CST4.19MGWU – – 6.0 – 1.9 – 1.8 – Capacitor-contained model 30 30 – – CSA6.00MGU 30 30 CST6.00MGWU – – 3.0 – Capacitor-contained model 2.4 – Capacitor-contained model KBR-1000F/Y 1.0 100 100 1.8 KBR-2.0MS 2.0 68 68 1.95 KBR-4.19MSA 4.19 33 33 1.8 KBR-6.0MSA 6.0 33 33 CCR1000K2 1.0 100 100 1.8 CCR2.0MC33 2.0 – – 2.0 CCR4.19MC3 4.19 FCR4.19MC5 5.5 5.5 – – Capacitor-contained model 2.2 6.0 2.0 FCR6.0MC5 Note Rd = 1 kΩ Capacitor-contained model CST6.00MGW CCR6.0MC3 Remarks Capacitor-contained model CST4.19MGW CSA6.00MG TDK Oscillation Voltage Range (V DD) CSB1000JNote CST2.00MG040 Kyocera Corp. Oscillator Constant (pF) 2.2 When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 1 kΩ) is necessary (refer to the figure below). The limiting resistor is not necessary when using the other recommended resonators. X1 X2 CSB1000J C1 Rd C2 Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee precision of the oscillation frequency. If the application circuit requires precision of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 58 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Output current, low Input voltage, high Symbol I OL VIH1 VIH2 VIH3 Conditions MAX. Unit Per pin 15 mA Total of all pins 150 mA Ports 2, 3, 11 Ports 0, 1, 6, RESET Ports 4, 5 2.7 V ≤ V DD ≤ 5.5 V 0.7V DD V DD V 1.8 V ≤ VDD < 2.7 V 0.9V DD V DD V 2.7 V ≤ V DD ≤ 5.5 V 0.8V DD V DD V 1.8 V ≤ VDD < 2.7 V 0.9V DD V DD V 2.7 V ≤ V DD ≤ 5.5 V 0.7V DD V DD V provided 1.8 V ≤ VDD < 2.7 V 0.9V DD V DD V 2.7 V ≤ V DD ≤ 5.5 V 0.7V DD 13 V 1.8 V ≤ VDD < 2.7 V 0.9V DD 13 V VIH4 X1, XT1 VIL1 Ports 2, 3, 4, 5, 11 VIL2 Ports 0, 1, 6, RESET VIL3 X1, XT1 Output voltage, high VOH SCK, SO, ports 2, 3, 6 Output voltage, low SCK, SO, ports 2, 3, 4, 5, 6 VOL1 TYP. Pull-up resistor N-ch open drain Input voltage, low MIN. V DD–0.1 V DD V 2.7 V ≤ V DD ≤ 5.5 V 0 0.3V DD V 1.8 V ≤ VDD < 2.7 V 0 0.1V DD V 2.7 V ≤ V DD ≤ 5.5 V 0 0.2V DD V 1.8 V ≤ VDD < 2.7 V 0 0.1V DD V 0 0.1 V IOH = –1.0 mA VDD–0.5 IOL = 15 mA V 0.2 2.0 V VDD = 4.5 to 5.5 V I OL = 1.6 mA VOL2 SB0, SB1 I LIH1 VIN = VDD 0.4 V 0.2V DD V Pins other than X1, XT1 3 µA N-ch open drain Pull-up resistor ≥ 1 kΩ Input leakage X1, XT1 20 µA I LIH3 VIN = 13 V Ports 4, 5 (N-ch open drain) 20 µA Input leakage I LIL1 VIN = 0 V Pins other than ports 4, 5, X1, XT1 –3 µA current, low I LIL2 X1, XT1 –20 µA I LIL3 Ports 4, 5 (N-ch open drain) –3 µA current, high I LIH2 When input instruction is not executed Ports 4, 5 (N-ch open drain) When input instruction is executed Output leakage –30 µA VDD = 5.0 V –10 –27 µA VDD = 3.0 V –3 –8 µA 3 µA I LOH1 VOUT = VDD I LOH2 VOUT = 13 V Ports 4, 5 (N-ch open drain) 20 µA I LOL VOUT = 0 V –3 µA Internal pull-up RL1 VIN = 0 V resistor RL2 current, high Output leakage SCK, SO/SB0, SB1, ports 2, 3, 6, ports 4, 5 (Pull-up resistor provided) current, low Ports 0, 1, 2, 3, 6 (except pin P00) 50 100 200 kΩ Ports 4, 5 (Mask option) 15 30 60 kΩ Data Sheet U10165EJ2V0DS00 59 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) DC Characteristics (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Supply currentNote 1 Symbol IDD1 IDD2 IDD1 IDD2 IDD3 Conditions MIN. VDD = 5.0 V 2.2 6.6 mA VDD = 3.0 V ±10%Note 4 0.48 1.5 mA Note 2 HALT VDD = 5.0 V ±10% 0.86 2.6 mA mode VDD = 3.0 V ±10% 0.43 1.3 mA ±10%Note 3 1.7 4.5 mA VDD = 3.0 V ±10%Note 4 0.4 1.2 mA 4.19-MHz crystal oscillation C1 = C2 = 22 pF VDD = 5.0 V HALT VDD = 5.0 V ±10% 0.7 2 mA mode VDD = 3.0 V ±10% 0.39 1.2 mA 32.768- Low- VDD = 3.0 V ±10% 11 33 µA kHzNote 5 voltage VDD = 2.0 V ±10% 5.5 17 µA crystal modeNote 6 VDD = 3.0 V, TA = 25˚C 11 22 µA Low current dissipation mode Note 7 VDD = 3.0 V ±10% 9.2 27 µA VDD = 3.0 V, TA = 25˚C 9.2 18 µA HALT Low- VDD = 3.0 V ±10% 6.4 20 µA mode voltage VDD = 2.0 V ±10% 2.5 8 µA 6.4 12.8 µA VDD = 3.0 V ±10% 4.6 13.8 µA VDD = 3.0 V, TA = 25˚C 4.6 9.2 µA modeNote 6 VDD = 3.0 V, TA = 25˚C Low current dissipation mode Note 7 XT1 = VDD = 5.0 V ±10% 0.05 10 µA 0 VNote 8 VDD = 3.0 V ±10% 0.02 5 µA 0.02 3 µA STOP mode 2. 3. Unit crystal oscillation C1 = C2 = 22 pF IDD4 Notes 1. MAX. ±10%Note 3 oscillation IDD5 TYP. 6.0-MHz Note 2 TA = 25˚C The current flowing to the internal pull-up resistor is not included. Including the case when the subsystem clock oscillates. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 4. When the device operates in low-speed mode with PCC set to 0000. 5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 60 6. When the sub-oscillation circuit control register (SOS) is set to 0000. 7. When SOS is set to 0010. 8. When SOS is set to 00×1, and the sub-oscillation circuit feedback resistor is not used (×: don’t care). Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) AC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 0.67 64 µs (minimum instruction main system clock 0.95 64 µs execution time = 1 Operates with 114 125 µs machine cycle) subsystem clock 0 1.0 MHz 0 275 kHz CPU clock cycle timeNote 1 TI0, TI1 input frequency TI0, TI1 input high-/low-level t CY f TI t TIH, t TIL VDD = 2.7 to 5.5 V Operates with VDD = 2.7 to 5.5 V 0.48 µs 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 10 µs INT1, 2, 4 10 µs KR0 to 3 10 µs 10 µs VDD = 2.7 to 5.5 V width Interrupt input high-/ t INTH, t INTL INT0 low-level width RESET low-level width Notes 1. 122 t RSL The cycle time (minimum instruction tCY vs VDD execution time) of the CPU clock (Φ) (with main system clock) is determined by the oscillation frequency of the connected resonator (and external 64 60 clock), the system clock control register (SCC), and processor clock control 6 register (PCC). 5 Guaranteed operation range voltage V DD vs. cycle time t CY characteristics when the device operates with the main system clock. 2. 2t CY or 128/fX depending on the setting of the interrupt mode register (IM0). Cycle time tCY [ µ s] The figure on the right shows the supply 4 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] Data Sheet U10165EJ2V0DS00 61 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 SCK high-/low-level width tKL1, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH1 SI Note 1 SI Note 1 setup time (to SCK ↑) hold time tSIK1 tKSI1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V (from SCK ↑) SCK ↓ → SONote 1 output tKSO1 delay time Notes 1. RL = 1 kΩ, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2–50 ns tKCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and C L are the load resistance and load capacitance of the SO output line. 2. 2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high-/low-level width Symbol tKCY2 tKL2, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH2 SI Note 1 setup time (to SCK ↑) SI Note 1 hold time tSIK2 tKSI2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V (from SCK ↑) SCK ↓ → SONote 1 output delay time Notes 1. 2. 62 tKSO2 RL = 1 kΩ, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and C L are the load resistance and load capacitance of the SO output line. Data Sheet U10165EJ2V0DS00 MAX. µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) A/D Converter Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V, 1.8 V ≤ AV REF ≤ V DD) Parameter Symbol Conditions Resolution Absolute accuracyNote 1 VDD = AVREF MIN. TYP. 8 8 2.7 V ≤ V DD 1.8 V ≤ VDD < 2.7 V VDD ≠ AVREF MAX. Unit 8 bit 1.5 LSB 3 LSB 3 LSB Conversion time tCONV Note 2 168/fX µs Sampling time tSAMP Note 3 44/f X µs Analog input voltage VIAN Analog input impedance RAN 1000 AV REF current IREF 0.25 Notes 1. 2. AVSS AV REF V MΩ 2.0 mA Absolute accuracy excluding quantization error (±1/2LSB) Time until end of conversion (EOC = 1) after execution of conversion start instruction (40.1 µs: fX = 4.19 MHz). 3. Time until end of sampling after execution of conversion start instruction (10.5 µs: f X = 4.19 MHz). Data Sheet U10165EJ2V0DS00 63 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) AC timing test points (excluding X1 and XT1 inputs) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD – 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD – 0.1 V XT1 input 0.1 V TI0, TI1 timing 1/fTI tTIL tTIH TI0, TI1 64 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Serial transfer timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 Input data SI tKSO1, 2 Output data SO 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 Data Sheet U10165EJ2V0DS00 65 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0 to 3 RESET input timing tRSL RESET 66 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85˚C) Parameter Symbol Release signal set time t SREL Oscillation stabilization t WAIT Conditions TYP. MAX. Unit µs 0 wait time Note 1 Notes 1. MIN. Released by RESET Note 2 ms Released by interrupt request Note 3 ms The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Either 2 17/fX or 215/fX can be selected by mask option. 3. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait Time BTM3 BTM2 BTM1 BTM0 – 0 0 0 220/fX (approx. 250 ms) 220/fX (approx. 175 ms) – 0 1 1 217/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms) – 1 0 1 215/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms) 1 213/fX 213/fX (approx. 1.37 ms) f X = 4.19 MHz – 1 1 fX = 6.0 MHz (approx. 1.95 ms) Data retention timing (STOP mode release by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: STOP mode release by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDDDR VDD tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U10165EJ2V0DS00 67 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 13. CHARACTERISTICS CURVES (REFERENCE VALUES) IDD vs VDD (main system clock: 6.0-MHz crystal resonator) (TA = 25˚C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32-kHz oscillation 1.0 Supply Current IDD (mA) 0.5 0.1 0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 Crystal resonator 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 68 Data Sheet U10165EJ2V0DS00 5 XT2 Crystal resonator 6.0 MHz 32.768 kHz 330 kΩ 22 pF 33 pF 33 pF 6 7 8 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) IDD vs VDD (main system clock: 4.19-MHz crystal resonator) (TA = 25˚C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32-kHz oscillation 1.0 Supply Current IDD (mA) 0.5 0.1 0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 Crystal resonator 22 pF 0.001 0 1 2 3 4 5 XT2 Crystal resonator 4.19 MHz 32.768 kHz 330 kΩ 22 pF 33 pF 33 pF 6 7 8 Supply Voltage VDD (V) Data Sheet U10165EJ2V0DS00 69 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 14. PACKAGE DRAWINGS 42 PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 21 A K H G J I L F B D N R M C M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item “K” to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 39.13 MAX. 1.541 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 15.24 (T.P.) 13.2 0.600 (T.P.) 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P42C-70-600A-1 70 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 42 PIN PLASTIC SHRINK SOP (375 mil) 42 22 3° +7° –3° detail of lead end 1 21 A H J E K F G I N C D M B L M S42GT-80-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 18.16 MAX. 0.715 MAX. B 1.13 MAX. 0.044 MAX. C 0.8 (T.P.) 0.031 (T.P.) D 0.35 +0.10 –0.05 0.014 +0.004 –0.003 E 0.125 ±0.075 0.005 ±0.003 F 2.9 MAX. 0.115 MAX. G 2.5 ±0.2 0.098+0.009 –0.008 H 10.3 ±0.3 0.406+0.012 –0.013 I 7.15 ±0.2 0.281+0.009 –0.008 J 1.6 ±0.2 0.063 ±0.008 K 0.15 +0.10 –0.05 0.006 +0.004 –0.002 L 0.8 ±0.2 0.031 +0.009 –0.008 M 0.10 0.004 N 0.10 0.004 Data Sheet U10165EJ2V0DS00 71 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 15. RECOMMENDED SOLDERING CONDITIONS The µPD750068 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions µPD750064GT-××× : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD750066GT-××× : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD750068GT-××× : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD750064GT(A)-××× : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD750066GT(A)-××× : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD750068GT(A)-××× : 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235˚C, Time: 30 sec. Max. (at 210˚C or higher), IR35-00-2 Count: two times or less VPS Package peak temperature: 215˚C, Time: 40 sec. Max. (at 200˚C or higher), VP15-00-2 Count: two times or less Wave soldering Solder bath temperature: 260˚C Max., Time: 10 sec. Max., Count: once Preheating temperature: 120˚C Max. (package surface temperature) Partial heating Pin temperature: 300˚C Max., Time: 3 sec. Max. (per pin row) WS60-00-1 Caution Do not use different soldering methods together (except for partial heating). Table 15-2. Through Hole Type Soldering Conditions µPD750064CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD750066CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD750068CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD750064CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD750066CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD750068CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) Soldering Method Soldering Conditions Wave soldering (pin only) Solder bath temperature: 260˚C Max., Time: 10 sec. Max. Partial heating Pin temperature: 300˚C Max., Time: 3 sec. Max. (per pin) Caution In wave soldering, apply solder only to the pins. Care must be taken that jet solder does not come in contact with the main body of the package. 72 Data Sheet U10165EJ2V0DS00 — µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX A. µPD75068, 750068 AND 75P0076 FUNCTIONAL LIST Item Program memory µPD75068 µPD750068 µPD75P0076 Mask ROM 0000H to 1F7FH (8064 × 8 bits) Mask ROM 0000H to 1FFFH (8192 × 8 bits) One-time PROM 0000H to 3FFFH (16384 × 8 bits) Data memory 000H to 1FFH (512 × 4 bits) CPU 75X Standard CPU 75XL CPU General-purpose register 4 bits × 8 or 8 bits × 4 (4 bits × 8 or 8 bits × 4) × 4 banks Instruction execution time When main system clock is selected 0.95, 1.91, 15.3 µs (@4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (@6.0-MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (@4.19-MHz operation) When subsystem clock is selected 122 µs (@32.768-kHz operation) CMOS input 12 (on-chip pull-up resistor specified by software: 7) CMOS input/output 12 (on-chip pull-up resistor specified by software) N-ch open-drain input/output 8 (on-chip pull-up resistor specified by mask option) Withstand voltage is 10 V Total 32 I/O port Timer 3 • • • channels 8-bit timer/event counter 8-bit basic interval timer Watch timer A/D converter • 8-bit resolution × 8 channels (successive approximation) • Can operate at the voltage from V DD = 2.7 V 8 (on-chip pull-up resistor specified by mask option) Withstand voltage is 13 V 8 (no mask option) Withstand voltage is 13 V 4 channels • 8-bit timer/event counter 0 (watch timer output added) • 8-bit timer/event counter 1 (can be used as a 16-bit timer/ event counter) • 8-bit basic interval timer/watchdog timer • Watch timer • 8-bit resolution × 8 channels (successive approximation) • Can operate at the voltage from V DD = 1.8 V Data Sheet U10165EJ2V0DS00 73 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Item µPD75068 µPD750068 µPD75P0076 Clock output (PCL) Φ, 524, 262, 65.5 kHz (@4.19-MHz operation with main system clock) • Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@4.19-MHz operation with main system clock) • Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@6.0-MHz operation with main system clock) Buzzer output (BUZ) 2, 4, 32 kHz (@4.19-MHz operation with main system clock or @32.768-kHz operation with subsystem clock) • 2, 4, 32 kHz (@4.19-MHz operation with main system clock or @32.768-kHz operation with subsystem clock) • 2.93, 5.86, 46.9 kHz (@6.0-MHz operation with main system clock) Serial interface 3 modes are available • 3-wire serial I/O mode ··· MSB/LSB can be selected for transfer first bit • 2-wire serial I/O mode • SBI mode 2 modes are available • 3-wire serial I/O mode ··· MSB/LSB can be selected for transfer first bit • 2-wire serial I/O mode Vectored interrupt External: 3, internal: 3 External: 3, internal: 4 Test input External: 1, internal: 1 Supply voltage VDD = 2.7 to 6.0 V Operating ambient temperature TA = –40 to +85˚C Package • 42-pin plastic shrink DIP (600 mil) • 44-pin plastic QFP (10 × 10 mm) 74 VDD = 1.8 to 5.5 V • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) • 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD750068. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part Number (Product Name) Host Machine OS PC-9800 Series Supply Media MS-DOSTM 3.5-inch 2HD µS5A13RA75X Ver. 3.30 to 5-inch 2HD µS5A10RA75X 3.5-inch 2HC µS7B13RA75X 5-inch 2HC µS7B10RA75X Ver. 6.2Note IBM PC/ATTM compatible machines Device file Refer to “OS for IBM PC” OS PC-9800 Series Supply Media MS-DOS Ver. 3.30 to Ver.6.2 IBM PC/AT compatible machines Note Part Number (Product Name) Host Machine 3.5-inch 2HD µS5A13DF750068 5-inch 2HD µS5A10DF750068 3.5-inch 2HC µS7B13DF750068 5-inch 2HC µS7B10DF750068 Note Refer to “OS for IBM PC” Ver. 5.00 or later has the task swap function, but it cannot be used for this software. Remark Operation of the assembler and device file is guaranteed only on the above host machines and OSs. Data Sheet U10165EJ2V0DS00 75 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) PROM write tools Hardware Software PG-1500 PG-1500 is a PROM programmer which enables you to program single-chip microcontrollers including PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PA-75P0076CU PROM programmer adapter for the µPD75P0076CU and 75P0076GT. programmer adapter to PG-1500 for use. PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Part Number (Product Name) Host Machine OS PC-9800 Series MS-DOS Ver. 3.30 to Connect the Supply Media 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 3.5-inch 2HD µS7B13PG1500 5-inch 2HC µS7B10PG1500 Ver. 6.2Note IBM PC/AT compatible machines Note Refer to “OS for IBM PC” Ver. 5.00 or later has the task swap function, but it cannot be used for this software. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. 76 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD750068. The system configurations are described as follows. Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a µPD750068 Subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. IE-75001-R In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X Series and 75XL Series. When developing a µPD750068 Subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use a µPD750068 Subseries. It must be used with the IE-75000-R or IE-75001-R. EP-750068CU-R Emulation probe for the µPD750068CU. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. EP-750068GT-R Emulation probe for the µPD750068GT. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the flexible board EV-9500GT-42 which facilitates connection to a target system. EV-9500GT-42 Software IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the IE-75000-R or IE-75001-R on a host machine. Host Machine OS PC-9800 Series MS-DOS Ver. 3.30 to Supply Media Part Number (Product Name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 3.5-inch 2HC µS7B13IE75X 5-inch 2HC µS7B10IE75X Ver. 6.2Note 2 IBM PC/AT compatible machines Notes 1. 2. Refer to “OS for IBM PC” Maintenance product Ver. 5.00 or later has the task swap function, but it cannot be used for this software. Remarks 1. 2. Operation of the IE control program is guaranteed only on the above host machines and OSs. The µ PD750064, 750066, 750068, and 75P0076 are commonly referred to as the µPD750068 Subseries. Data Sheet U10165EJ2V0DS00 77 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) OS for IBM PC The following IBM PC OS’s are supported. OS Version PC DOSTM Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote IBM DOS TM J5.02/V Note Note Only English version is supported. Caution Ver. 5.0 or later has the task swap function, but it cannot be used for this software. 78 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to device Document No. Document Name Japanese English µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet U10165J U10165E (this document) µPD75P0076 Data Sheet U10232J U10232E µPD750068 User’s Manual U10670J U10670E µPD750068 Instruction Table IEM-5606 75XL Series Selection Guide U10453J – U10453E Documents related to development tool Document No. Document Name Japanese Hardware Software English IE-75000-R/IE-75001-R User’s Manual EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-750068CU/GT-R User’s Manual U10950J U10950E PG-1500 User’s Manual U11940J U11940E Operation U12622J U12622E Language U12385J U12385E Structured Assembler U12598J Preprocessor U12598E PC-9800 Series EEU-704 (MS-DOS) Based EEU-1291 IBM PC Series EEU-5008 (PC DOS) Based U10540E RA75X Assembler Package User’s Manual PG-1500 Controller User’s Manual Other related documents Document No. Document Name Japanese English SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcomputer-Related Products by Third Party Caution U11416J – The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U10165EJ2V0DS00 79 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 80 Data Sheet U10165EJ2V0DS00 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U10165EJ2V0DS00 81 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8