NEC UPD75312B

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75312B, 75316B
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75316B is a 75X Series 4-bit single-chip microcomputer capable of the same data processing as an 8bit microcomputer.
It is a low-voltage operation version of the µPD75316 with an on-chip LCD controller/driver. Operation at an ultralow voltage of 2.0 V is possible. An ultra small-sized plastic TQFP (12 x 12 mm) is also provided and it is suitable
for small-sized sets that use an LCD panel.
A detailed explanation of the functions will be given in the user's manual listed below. It should be read before
starting design work.
µ PD75308 User's Manual: IEM-1263
FEATURES
• Ultra-low-voltage operation possible: VDD = 2.0 to 6.0 V • Instruction execution time adjustment function
• Can be driven by two 1.5-V manganese batteries.
• On-chip memory
• Program memory (ROM)
: 16256 × 8 bits (µ PD75316B)
: 12160 × 8 bits (µ PD75312B)
• Data memory (RAM)
: 1024 × 4 bits
convenient in high-speed operation and power
saving
• 0.95 µ s, 1.91 µs, 15.3 µs (@ 4.19 MHz)
• 122 µs (@ 32.768 kHz)
• On-chip programmable LCD controller/driver
• LCD drive voltage: 2.0 V to VDD
• Ultra small-sized plastic TQFP (12 x 12 mm)
• Suitable for small-sized set, such as a camera.
• PROM version µPD75P316B also available.
APPLICATIONS
Remote control, camcorder, camera, gas meter, etc.
ORDERING INFORMATION
Part number
Package
µ PD75312BGC-×××-3B9
µ PD75312BGK-×××-BE9
80-pin plastic QFP (14 x 14 mm)
µ PD75316BGC-×××-3B9
80-pin plastic QFP (14 x 14 mm)
µ PD75316BGK-×××-BE9
80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
Remark
80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
×××: ROM code suffix
Unless stated otherwise, the explanations in this document will use the µPD75316B as a representative part.
The information in this document is subject to change without notice.
Document No. IC-3196A
(O. D. No. IC-8698A)
Date Published December 1994 P
Printed in Japan
© NEC Corporation 1993
µPD75312B, 75316B
FUNCTION OUTLINE (1/2)
Item
Function
Number of basic instructions
41
Instruction cycle
0.95 µs, 1.91 µs, 15.3 µs (main system clock: @ 4.19 MHz)
122 µs (subsystem clock: @ 32.768 kHz)
ROM
16256 × 8 bits (µPD75316B), 12160 × 8 bits (µPD75312B)
RAM
1024 × 4 bits
On-chip memory
General register
• 4-bit access: 8 (B, C, D, E, H, L, X, A)
• 8-bit access: 4 (BC, DE, HL, XA)
Accumulators
• Bit accumulator (CY)
• 4-bit accumulator (A)
• 8-bit accumulator (XA)
Instruction set
•
•
•
•
Various bit manipulation instructions
Efficient 4-bit data manipulation instructions
8-bit data transfer instructions
GETI instruction that can implement 2-byte/3-byte instructions with 1 byte
8
CMOS input
16
CMOS input/output
8
CMOS output
Used with segment pins
8
N-ch open-drain
input/output
10-V withstand voltage, with mask option pullup resistors: 8
with software-specifiable pull-up resistors : 23
40
I/O lines
LCD controller/driver
• Number of segments selection: 24/28/32 segments (4/8 can be switched at bit
port output.)
• Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty
• LCD drive split resistor can be incorporated by mask option
Supply voltage range
VDD = 2.0 to 6.0 V
• 8-bit timer/event counter
• Clock source: 4 stages
• Event count possible
Timer
2
3 channels
• 8-bit basic interval timer
• Standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms
(@ 4.19 MHz)
• Watchdog timer application possible
µPD75312B, 75316B
FUNCTION OUTLINE (2/2)
Item
Timer
8-bit serial interface
Function
3 channels
• Clock timer
• 0.5-second time interval generation
• Count clock source: Main system clock and subsystem clock
switchable
• Clock fast count mode (3.9-ms time interval generation)
• Buzzer output possible (2 kHz)
• Three modes application possible
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode
• LSB first/MSB first switchable
Bit sequential buffer
Special bit manipulation memory: 16 bits
• Perfect for remote control application
Timer/event counter output (PTO0): square-wave output frequency specifiable
Clock output function
Clock output (PCL): Φ, 524, 262, 65.5 kHz (@ 4.19 MHz)
Buzzer output (BUZ): 2 kHz (@ 4.19 MHz or 32.768 kHz)
Vectored interrupt
• External : 3
• Internal : 3
Test input
• External : 1
• Internal : 1
System clock oscillator
• Ceramic or crystal oscillator for main system clock oscillation: 4.194304 MHz
• Crystal oscillator for subsystem clock oscillation: 32.768 kHz
Standby
STOP/HALT mode
Package
• 80-pin plastic QFP (14 x 14 mm)
• 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
3
µPD75312B, 75316B
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ........................................................................................................... 5
2. BLOCK DIAGRAM ........................................................................................................................................ 6
3. PIN FUNCTIONS .......................................................................................................................................... 7
3.1
3.2
3.3
PORT PINS .............................................................................................................................................................. 7
NON-PORT PINS .................................................................................................................................................... 9
PIN INPUT/OUTPUT CIRCUITS .......................................................................................................................... 10
3.4
RECOMMENDED CONNECTION OF UNUSED PINS ....................................................................................... 12
4. MEMORY CONFIGURATION .................................................................................................................... 13
5. PERIPHERAL HARDWARE FUNCTIONS ..................................................................................................17
5.1
5.2
5.3
5.4
PORTS ................................................................................................................................................................... 17
CLOCK GENERATOR ........................................................................................................................................... 18
CLOCK OUTPUT CIRCUIT ................................................................................................................................... 19
BASIC INTERVAL TIMER .................................................................................................................................... 20
5.5
5.6
5.7
5.8
WATCH TIMER ..................................................................................................................................................... 21
TIMER/EVENT COUNTER ................................................................................................................................... 22
SERIAL INTERFACE ............................................................................................................................................. 24
LCD CONTROLLER/DRIVER ............................................................................................................................... 26
5.9
BIT SEQUENTIAL BUFFER ..... 16 BITS .............................................................................................................. 28
6. INTERRUPT FUNCTION ............................................................................................................................ 29
7. STANDBY FUNCTION ............................................................................................................................... 31
8. RESET FUNCTION ..................................................................................................................................... 32
9. INSTRUCTION SET .................................................................................................................................... 35
10. MASK OPTION SELECTION ..................................................................................................................... 42
11. ELECTRICAL SPECIFICATIONS ................................................................................................................ 43
12. CHARACTERISTIC CURVES (For Reference Only)................................................................................ 65
13. PACKAGE DRAWINGS .............................................................................................................................. 69
14. RECOMMENDED SOLDERING CONDITION .......................................................................................... 71
APPENDIX A. DIFFERENCES AMONG µPD75308B SERIES PRODUCTS ................................................. 73
APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 74
APPENDIX C. RELATED DOCUMENTATION ...............................................................................................75
4
µPD75312B, 75316B
S28/BP4
S29/BP5
S30/BP6
*
P61/KR1
S1
S0
RESET
P73/KR7
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
51
50
49
48
47
46
45
44
43
P31/SYNC
P30/LCDCL
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P10/INT0
P03/SI/SB1
10
11
12
13
14
15
16
17
18
COM0
S31/BP7
IC*
XT2
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
S25/BP1
S26/BP2
S27/BP3
X2
X1
XT1
VDD
P33
P32
P40
P41
P42
P43
VSS
S22
S23
S24/BP0
P60/KR0
57
56
55
54
53
52
µPD75312BGC-×××-3B9
µPD75312BGK-×××-BE9
µPD75316BGC-×××-3B9
µPD75316BGK-×××-BE9
S17
S18
S19
S20
S21
4
5
6
7
8
9
COM3
BIAS
VLC0
VLC1
VLC2
S14
S15
S16
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
2
59
3
58
1
COM1
COM2
S12
S13
S6
S5
S4
S3
S2
S11
S10
S9
S8
S7
1. PIN CONFIGURATION (TOP VIEW)
IC (Internally Connected) pin should be directly connected to VDD.
P00 to 03
P10 to 13
P20 to 23
P30 to 33
P40 to 43
P50 to 53
P60 to 63
P70 to 73
BP0 to 7
KR0 to 7
SCK
SI
SO
SB0,1
RESET
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Bit Port
Key Return
Serial Clock
Serial Input
Serial Output
Serial Bus 0, 1
Reset Input
S0 to 31
COM0 to 3
VLC0-2
BIAS
LCDCL
SYNC
TI0
PTO0
BUZ
PCL
INT0, 1, 4
INT2
X1, 2
XT1, 2
IC
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Segment Output 0 to 31
Common Output 0 to 3
LCD Power Supply 0 to 2
LCD Power Supply Bias Control
LCD Clock
LCD Synchronization
Timer Input 0
Programmable Timer Output 0
Buzzer Clock
Programmable Clock
External Vectored Interrupt 0, 1, 4
External Test Input 2
Main System Clock Oscillation 1, 2
Subsystem Clock Oscillation 1, 2
Internally Connected
5
INTBT
TI0/P13
PTO0/P20
PROGRAM
COUNTER (14)
SP(8)
TIMER/EVENT
COUNTER
#0
ALU
BANK
WATCH
TIMER
INTW
SI/SB1/P03
SO/SB0/P02
SCK/P01
f LCD
CLOCKED
SERIAL
INTERFACE
PROGRAM
MEMORY
(ROM)
16256 × 8 BITS
: µ PD75316B
12160 × 8 BITS
: µ PD75312B
4
P00-P03
PORT 1
4
P10-P13
PORT 2
4
P20-P23
PORT 3
4
P30-P33
PORT 4
4
P40-P43
PORT 5
4
P50-P53
PORT 6
4
P60-P63
PORT 7
4
P70-P73
CY
INTT0
BUZ/P23
PORT 0
2. BLOCK DIAGRAM
6
BASIC
INTERVAL
TIMER
GENERAL REG.
DECODE
AND
CONTROL
DATA
MEMORY
(RAM)
1024 × 4 BITS
INTCSI
24
S0-S23
INT0/P10
INT1/P11
INT2/P12
INT4/P00
INTERRUPT
CONTROL
N
fX / 2
BIT SEQ.
BUFFER (16)
CLOCK
OUTPUT
CONTROL
PCL/P22
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
SUB
MAIN
XT1 XT2 X1 X2
CPU
CLOCK
STAND BY
CONTROL
VDD
VSS RESET
fLCD
S24/BP0
–S31/BP7
4
COM0–COM3
3
VLC0–VLC2
BIAS
LCDCL/P30
SYNC/P31
µPD75312B, 75316B
KR0/P60
–KR7/P73
LCD
CONTROLLER
/DRIVER
8
µPD75312B, 75316B
3. PIN FUNCTIONS
3.1
PORT PINS (1/2)
Pin Name
Input/Output
DualFunction Pin
P00
Input
INT4
P01
Input/output
SCK
P02
Input/output
SO/SB0
P03
Input/output
SI/SB1
INT0
P10
Input
P12
INT2
P13
TI0
P20
PTO0
—
P21
Input/output
P22
PCL
P23
BUZ
P30 *2
LCDCL
SYNC
P31 *2
Input/output
P32 *2
—
P33 *2
—
P50 to P53 *2
*
8-bit I/O
Reset
I/O Circuit
Type *1
B
4-bit input port (PORT 0)
On-chip pull-up resistor can be specified for
P01 to P03 as a 3-bit unit by software.
F -A
×
Input
F -B
M-C
With noise elimination function
INT1
P11
P40 to P43 *2
Function
Input/output
Input/output
4-bit input port (PORT 1)
On-chip pull-up resistor can be specified as a
4-bit unit by software.
4-bit input/output port (PORT 2)
On-chip pull-up resistor can be specified as a
4-bit unit by software.
Programmable 4-bit input/output port (PORT 3)
Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified as a
4-bit unit by software.
×
Input
B -C
×
Input
E-B
×
Input
E-B
—
N-ch open-drain 4-bit input/output port (PORT
4)
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: 10-V withstand voltage
High level (onchip pull-up
resistor) or highimpedance
—
N-ch open-drain 4-bit input/output port (PORT
5)
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: 10-V withstand voltage
High level (onchip pull-up
resistor) or highimpedance
M
M
1.
: Schmitt triggered input
2. LED direct drive possible
7
µPD75312B, 75316B
3.1
PORT PINS (2/2)
Pin Name
Input/Output
P60
DualFunction Pin
Reset
I/O Circuit
Type *1
Programmable 4-bit input/output port (PORT 6)
Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified as a
4-bit unit by software.
Input
F -A
4-bit input/output port (PORT 7)
On-chip pull-up resistor can be specified as a
4-bit unit by software.
Input
F -A
*2
G-C
Function
8-bit I/O
KR0
P61
KR1
Input/output
P62
KR2
P63
KR3
P70
KR4
P71
KR5
Input/output
P72
KR6
P73
KR7
BP0
S24
BP1
S25
Output
BP2
S26
BP3
S27
BP4
S28
BP5
1-bit output port (BIT PORT)
Also used as segment output pin.
×
S29
Output
*
BP6
S30
BP7
S31
1.
: Schmitt triggered input
2. BP0 to BP7 select VLC1 as the input source.
However, the output level depends on BP0 to BP7 and VLC1 external circuit.
Example
BP0 to BP7 are connected mutually within the µPD75316B. Therefore, the output level of BP0 to BP7
is determined by the value of R1, R2 and R3.
µPD75316B
VDD
R2
BP0
ON
VLC1
R1
BP1
ON
8
R3
µPD75312B, 75316B
3.2
NON-PORT PINS
Reset
I/O Circuit
Type *1
External event pulse input pin to timer/event counter
Input
B -C
P20
Timer/event counter output pin
Input
E-B
Input/output
P22
Clock output pin
Input
E-B
BUZ
Input/output
P23
Fixed frequency output pin (for buzzer or system clock
trimming)
Input
E-B
SCK
Input/output
P01
Serial clock input/output pin
Input
F -A
SO/SB0
Input/output
P02
Serial data output pin
Serial bus input/output pin
Input
F -B
SI/SB1
Input/output
P03
Serial data input pin
Serial bus input/output pin
Input
M -C
INT4
Input
P00
Edge detection vectored interrupt input pin (both rising
edge and falling edge detection effective)
Input
B
Input
B -C
P11
Edge detection vectored
interrupt input pin (detection
edge selectable)
Edge detection testable input
pin (rising edge detection)
Input
B -C
Pin Name
Input/Output
DualFunction Pin
TI0
Input
P13
PTO0
Input/output
PCL
P10
INT0
INT1
Input
Function
Clocked
Asynchronous
Asynchronous
INT2
Input
P12
KR0 to KR3
Input/output
P60 to P63
Parallel falling edge detection testable input pin
Input
F -A
KR4 to KR7
Input/output
P70 to P73
Parallel falling edge detection testable input pin
Input
F -A
S0 to S23
Output
—
Segment signal output pin
*2
G-A
S24 to S31
Output
BP0 to BP7
Segment signal output pin
*2
G-C
COM0 to COM3
Output
—
Common signal output pin
*2
G-B
VLC0 to VLC2
—
—
LCD drive power supply pin
On-chip split resistor (mask option)
—
—
BIAS
Output
—
External split resistor cut output pin
*3
—
LCDCL *4
Input/output
P30
External expansion driver drive clock output pin
Input
E-B
SYNC *4
Input/output
P31
External expansion driver synchronization clock output
pin
Input
E-B
X1, X2
Input
––
Main system clock oscillation crystal/ceramic connection
pin. For external clock, the external clock signal is input
to X1 and the inverted phase is input to X2.
—
––
XT1
Input
––
––
XT2
—
—
Subsystem clock oscillation crystal connection pin. For
external clock, the external clock signal is input to XT1
and XT2 is opened. XT1 can be used as a 1-bit input
(test) pin.
RESET
Input
—
System reset input pin
—
B
IC
—
—
Internally Connected. Directly connected to VDD.
—
—
VDD
—
—
Positive power supply pin
—
—
VSS
—
—
GND potential pin
—
—
—
* 1.
: Schmitt triggered input
* 2. Display outputs are selected with VLCX shown below as the input source.
S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0
However, the level of each display output depends on the display output and VLCX external circuit.
* 3. On-chip split resistor………Low level
No on-chip split resistor… High-impedance
* 4. Pins provided for system expansion. Currently, only used as P30 and P31 pins.
9
µPD75312B, 75316B
3.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuits of each pin of the µPD75316B are shown in schematic form.
TYPE D (For TYPE E-B, F-A)
TYPE A (For TYPE E-B)
VDD
VDD
data
P-ch
P-ch
OUT
IN
N-ch
output
disable
N-ch
Push-pull output that can be made high-impedance output
CMOS Standard Input Buffer
TYPE B
(P-ch and N-ch OFF)
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
data
IN/OUT
Type D
output
disable
Type A
P.U.R.:Pull-Up Resistor
Schmitt-Triggered Input with Hysteresis Characteristic
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
P-ch
P.U.R.
enable
P-ch
data
IN/OUT
Type D
output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R.:Pull-Up Resistor
10
µPD75312B, 75316B
TYPE F-B
TYPE G-C
VDD
P.U.R.
P.U.R.
enable
VDD
P-ch
P-ch
VDD
output
disable
(P)
VLC0
P-ch
VLC1
IN/OUT
P-ch
data
output
disable
SEG
data/Bit Port data
N-ch
output
disable
(N)
OUT
N-ch
VLC2
N-ch
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M
VDD
P.U.R.
enable
(Mask Option)
IN/OUT
VLC0
P-ch
data
N-ch
VLC1
P-ch
SEG
data
output
disable
OUT
N-ch
VLC2
N-ch
Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)
P.U.R.:Pull-Up Resistor
TYPE G-B
TYPE M-C
VDD
VLC0
P-ch
P.U.R.
VLC1
P.U.R.
enable
P-ch
P-ch N-ch
IN/OUT
OUT
COM
data
N-ch
P-ch
data
N-ch
output
disable
VLC2
N-ch
P.U.R.:Pull-Up Resistor
11
µPD75312B, 75316B
3.4
RECOMMENDED CONNECTION OF UNUSED PINS
Table 3-1 List of Recommended Connection of Unused Pins
Pin
P00/INT4
Recommended Connection
Connect to VSS.
P01/SCK
P02/SO/SB0
Connect to VSS or VDD.
P03/SI/SB1
P10/INT0 to P12/INT2
Connect to VSS.
P13/T10
P20/TO0
P21
P22/PCL
P23/BUZ
P30/LCDCL
P31/SYNC
Input state
: Connect to VSS or VDD.
Output state : Leave open.
P32
P33
P40 to P43
P50 to P53
P60/KR0 to P63/KR3
P70/KR4 to P73/KR7
S0 to S23
S24/BP0 to S31/BP7
Leave open.
COM0 to COM3
VLC0 to VLC2
BIAS
Connect to VSS.
Connect to VSS when VLC0 to V LC2 unused.
Otherwise leave open.
12
XT1
Connect to VSS or VDD.
XT2
Leave open.
IC
Directly connect to VDD.
µPD75312B, 75316B
4. MEMORY CONFIGURATION
• Program memory (ROM) ... 16256 × 8 bits (0000H to 3F7FH) : µPD75316B
... 12160 × 8 bits (0000H to 2F7FH) : µPD75312B
• 0000H to 0001H : Vector table in which program start address by reset is written.
• 0002H to 000BH : Vector table in which program start address by interrupt is written.
• 0020H to 007FH : Table area that is referred by GETI instruction.
• Data Memory
• Data area ... 1024 × 4 bits (000H to 3FFH)
• Peripheral hardware area ... 128 × 4 bits (F80H to FFFH)
13
µPD75312B, 75316B
Fig. 4-1 Program Memory Map
(a) µPD75316B
Address
0000H
7
6
MBE
0
0
5
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H
MBE
0
INTBT/INT4 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
0004H
MBE
0
INT0 Start Address (High-Order 6 Bits)
CALLF
! faddr
Instruction
Entry
Address
INT0 Start Address (Low-Order 8 Bits)
0006H
MBE
0
INT1 Start Address (High-Order 6 Bits)
CALL !addr
Instruction
Subroutine
Entry Address
INT1 Start Address (Low-Order 8 Bits)
0008H
MBE
0
INTCSI Start Address (High-Order 6 Bits)
INTCSI Start Address (Low-Order 8 Bits)
000AH
MBE
0
BRCB
! caddr
Instruction
Branch
Address
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
≈
BR !addr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
≈
0020H
GETI Instruction Reference Table
007FH
0080H
≈
≈
07FFH
0800H
Branch Destination
Address and Subroutine
Entry Address
by GETI Instruction
≈
≈
≈
≈
BRCB !caddr
Instruction
Branch Address
≈
≈
BRCB !caddr
Instruction
Branch Address
≈
≈
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3F7FH
14
BRCB !caddr
Instruction
Branch Address
µPD75312B, 75316B
(b) µPD75312B
Address
0000H
7
6
MBE
0
5
0
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H
MBE
0
INTBT/INT4 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
0004H
MBE
0
INT0 Start Address (High-Order 6 Bits)
CALLF
! faddr
Instruction
Entry
Address
INT0 Start Address (Low-Order 8 Bits)
0006H
MBE
0
INT1 Start Address (High-Order 6 Bits)
CALL !addr
Instruction
Subroutine
Entry Address
INT1 Start Address (Low-Order 8 Bits)
0008H
MBE
0
INTCSI Start Address (High-Order 6 Bits)
INTCSI Start Address (Low-Order 8 Bits)
000AH
MBE
0
BRCB
! caddr
Instruction
Branch
Address
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
≈
BR !addr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
≈
0020H
GETI Instruction Reference Table
007FH
0080H
≈
≈
Branch Destination
Address and Subroutine
Entry Address
by GETI Instruction
07FFH
0800H
≈
≈
≈
≈
≈
≈
0FFFH
1000H
BRCB !caddr
Instruction
Branch Address
1FFFH
2000H
BRCB !caddr
Instruction
Branch Address
2F7FH
15
µPD75312B, 75316B
Fig. 4-2 Data Memory Map
Data Memory
Memory Bank
000H
(8 × 4)
General Register Area
007H
008H
Stack Area
0
256 × 4
(248 × 4)
0FFH
100H
256 × 4
(224 × 4)
1
1DFH
1E0H
(32 × 4)
Display Data Memory Area
1FFH
200H
Data Area
Static RAM
(1024 × 4)
256 × 4
2
256 × 4
3
2FFH
300H
3FFH
Not On-Chip
F80H
128 × 4
Peripheral Hardware Area
FFFH
16
15
µPD75312B, 75316B
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
I/O Ports has 4 types
•
•
•
•
CMOS input (PORT0, 1)
: 8
CMOS input/output (PORT2, 3, 6, 7) : 16
N-ch open-drain (PORT4, 5)
: 8
CMOS output (BP0 to BP7)
: 8
Total
40
Table 5-1 Port Function
Port (Symbol)
Function
Operation/Features
4-bit input
This port can be used for reading or testing
regardless of the operating mode of the dualfunction pin.
PORT0
PORT1
PORT3*
Remarks
Dual-function as pins INT4, SCK,
SO/B0, SI/B1.
Dual-function as pins INT0 to INT2 and TI0.
Dual-function as pins LCDCL and SYNC.
Can be set to 1-bit input or output mode.
PORT6
Can be set to 4-bit input or output mode. Ports
6 and 7 can be paired for 8-bit data input or
output.
PORT2
PORT7
PORT4*
PORT5*
BP0 to BP7
*
Dual-function as pins KR0 to KR3.
4-bit input/output
4-bit input/output
(N-ch open-drain,
10-V withstand
voltage)
1-bit output
Dual-function as pins PTO0, PCL, BUZ.
Dual-function as pins KR4 to KR7.
Can be set to 4-bit input or output mode. Ports
On-chip pull-up resistor specifiable bit4 and 5 can be paired for 8-bit data input or
wise by mask oftion.
output.
Data output in 1-bit units. It is possible to switch
The drive capability is small. For
the output drive segment output S24 to S31
CMOS load drive.
using the software.
LED can be driven directly.
17
µPD75312B, 75316B
5.2 CLOCK GENERATOR
The operation of the clock generator circuit is determined by the processor clock control register (PCC) and the
system clock control register (SCC).
There are two kinds of clocks; the main system clock and the subsystem clock.
It is also possible to change the instruction execution time.
• 0.95 µs/1.91 µs/15.3 µs (main system clock: @ 4.19 MHz)
• 122 µs (sub-system clock: @ 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
• Basic Interval Timer (BT)
• Timer/Event Counter
• Serial Interface
• Watch Timer
• LCD Controller/Driver
• INT0 Noise Eliminator
• Clock Output Circuit
XT1
VDD
XT2
Subsystem
Clock Oscillator
fXT
Main System
Clock Oscillator
fX
LCD Controller/
Driver
Watch Timer
X1
VDD
X2
1/8 to 1/4096
Frequency Divider
Oscillation
Stop
Selector
WM. 3
SCC
Selector
1/2 1/16
SCC3
Internal Bus
SCC0
Frequency
Divider
1/4
Φ
• CPU
• INT0 Noise
Eliminator
• Clock Output
Circuit
PCC
PCC0
PCC1
4
HALT F/F
HALT *
PCC2
S
PCC3
STOP *
R
PCC2,
PCC3
Clear
STOP F/F
Q
Q
Wait Release Signal from BT
S
RESET Signal
R
fX:
Main system clock frequency
fXT:
Φ:
PCC:
SCC:
Subsystem clock frequency
CPU clock
Processor clock control register
System clock control register
Remarks
18
1.
2.
Standby Release Signal from
Interrupt Control Circuit
* indicates instruction execution.
Φ one clock cycle (tCY) is one machine cycle instruction. For tCY, refer to AC characteristics in "11
ELECTRICAL SPECIFICATIONS."
µPD75312B, 75316B
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is used for outputting the clock pulse from the P22/PCL pins. It is used, for example,
when a clock pulse is to be output to the remote control output, peripheral LSI, etc..
• Clock output (PCL) : Φ , 524, 262, 65.5 kHz (4.19 MHz operation)
The configuration of the clock output circuit is shown below.
Fig. 5-2 Clock Output Circuit Configuration
From Clock
Generator
Φ
fX/2
3
Output Buffer
Selector
fX/2
fX/2
4
PCL/P22
6
PORT2.2
CLOM3
0
CLOM1CLOM0
CLOM
P22
Output Latch
Bit 2 of PMGB
Bit Specified
In Port 2
Input/Output
Mode
4
Internal Bus
Remark
Consideration is given so that a low-amplitude pulse is not output when switching between clocks.
19
µPD75312B, 75316B
5.4 BASIC INTERVAL TIMER
The basic interval timer includes the following functions.
• It operates as an interval timer which generates reference time interrupts.
• It can be applied as a watchdog timer which detects inadvertent program loop.
• Selects and counts wait times when the standby mode is released.
• It reads count contents.
Fig. 5-3 Basic Interval Timer Configuration
From Clock
Generator
fX/2
fX/2
Clear
5
7
fX/2
Set
Basic Interval Timer
(8-Bit Frequency Divider)
MPX
fX/2
Clear
9
BT
12
3
BTM3
*SET1
BTM2
BTM1
Wait Release
Signal during
Standby Release
BTM0 BTM
8
4
Internal Bus
Remark
20
* indicates instruction execution.
BT Interrupt
Request Flag
IRQBT
Vectored
Interrupt
Request
Signal
µPD75312B, 75316B
5.5 WATCH TIMER
The µPD75316B incorporates a watch timer channel. The watch timer has the following functions.
• Sets test flags (IRQW) at 0.5-second intervals.
The standby mode can be released with IRQW.
• 0.5-second time intervals can be created in either the main system clock or the subsystem clock.
• In the rapid feed mode, time intervals which are 128 times normal (3.91 ms) can be set, making this
function convenient for program debugging and testing.
• A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and
trimming system clock oscillator frequencies.
• The frequency divider can be cleared, enabling creation of watches that can start from 0 second.
Fig. 5-4 Watch Timer Block Diagram
fW
6
2
(512 Hz : 1.95 ms)
fLCD
fW
(256 Hz : 3.91 ms)
7
2
From
Clock
Generator
fX
128
(32.768 kHz)
Selector
fW
14
2
fW
Frequency Divider
(32.768 kHz)
fXT
(32.768 kHz)
INTW
IRQW Set
Signal
Selector
2Hz
0.5 sec
fW
16
(2.048 kHz) Clear
Output Buffer
P23/BUZ
WM
WM7
PORT2.3
0
0
0
WM3 WM2 WM1 WM0
8
P23
Output
Latch
Bit 2 of PMGB
Port 2
Input/Output
Mode
Bit Test Instruction
Internal Bus
Remark
Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz.
21
µPD75312B, 75316B
5.6 TIMER/EVENT COUNTER
The µPD75316B incorporates a timer/event counter channel. The functions of the timer/event counter are as
follows.
•
•
•
•
•
•
22
Operates as a programmable interval timer.
Outputs square waves in the desired frequency to the PTO0 pin.
Operates as an event counter.
Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation).
Supplies a serial shift clock to the serial interface circuit.
Count status read function.
Fig. 5-5 Timer/Event Counter Block Diagram
Internal Bus
SET1
8
*1
8
8
TM0
TMOD0
Modulo Register (8)
TM06 TM05 TM04 TM03 TM02
8
PORT1.3
Match
Input Buffer
8
Reset
P13/TI0
T0
Count Register (8)
MPX
CP
PORT2.0 Bit 2 of PGMB
Port 2
P20
Input/
Output
Output
Latch
Mode
To Serial
Interface
TOUT
F/F
Comparator (8)
*2
From Clock
Generator
TOE0
TO
Enable
Flag
P20/PTO0
Output
Buffer
INTT0
IRQT0 Set
Signal
Clear
Timer Operation Start
*
1. SET1: Instruction execution
2. For detail, see Fig. 5-1.
23
µPD75312B, 75316B
RESET
IRQT0
Clear Signal
µPD75312B, 75316B
5.7 SERIAL INTERFACE
The µPD75316B incorporates a clocked 8-bit serial interface which has the following three types of mode.
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode (serial bus interface mode)
24
Fig. 5-6 Serial Interface Block Diagram
Internal Bus
8/4 Bit
Test
CSIM
8
8
Bit Manipulation
Slave Address Register (SVA)
Addres Comparator
(8)
(8)
RELT
CMDT
SO
SET CLR Latch
D
Q
ACKT
ACKE
BSYE
Shift Register (SIO)
SBIC
Match
Signal
(8)
P03/SI/SB1
Selector
Bit Test
8
Selector
P02/SO/SB0
Busy/
Acknowledge
Output Circuit
Bus Release/
Command/
Acknowledge
Detector
P01/SCK
Serial Clock
Counter
INTCSI
INTCSI Control
Circuit
 IRQCSI



 set signal 
3
Serial Clock
Control Circuit
Serial
Clock
Slector
fX/24
fX/2
6
fX/2
TOUT F/F
(From Timer/
Event Counter)
External
SCK
25
µPD75312B, 75316B
P01
Output
Latch
RELD
CMDD
ACKD
µPD75312B, 75316B
5.8 LCD CONTROLLER/DRIVER
The µPD75316B has an on-chip display controller which generates segment signals and common signals in
accordance with data in display data memory as well as a segment driver and common driver capable of directly
driving the LCD panel.
The configuration of the LCD controller/driver is shown in Fig. 5-7.
The functions of the LCD controller/driver are as follows.
• Display data memory are read automatically through DMA operations and segment signals and common
signals are generated.
• 5 different display modes can be selected.
1 Static
2 1/2 duty (1/2 bias)
3 1/3 duty
4 1/3 duty
5 1/4 duty
• In each of
(1/2 bias)
(1/3 bias)
(1/3 bias)
the display modes, 4 types of frame frequency can be selected.
• The segment signal output is a maximum of 32 segments (S0 to S31) and 4 common outputs (COM0 to
COM3).
• Segment signal outputs (S24 to S27, S28 to S31) are in 4-segment units and they can be switched for use
as output ports (BP0 to BP3, BP4 to BP7).
• Split resistors can be incorporated for the LCD drive power supply (mask option).
Conformity to various bias methods and LCD drive voltages is possible.
• When the display is OFF, the current flowing to the split resistors is cut.
• Display data memory not used for the display can be used as ordinary data memory.
•
• Operation by the subsystem clock is also possible.
26
Fig. 5-7 LCD Controller/Driver Block Diagram
4
Display Data
Memory
1FFH
1FEH
1F9H
1E0H
1F8H
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3 2
1 0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3 2
1 0
8
4
4
8
Display Mode
Register
Display
Control
Register
Port 3
Output
Latch
1 0
Port Mode
Register
Group A
1
0
Timing
Controller
fLCD
Multiplexer
Selector
Common Driver
Segment Driver
S30/BP6
S24/BP0
S23
S0
COM3 COM2COM1COM0 V
LC2
VLC1
VLC0 P31/ P30/
SYNC LCDCL
27
µPD75312B, 75316B
S31/BP7
LCD Drive Voltage
Control
µPD75312B, 75316B
5.9 BIT SEQUENTIAL BUFFER ..... 16 BITS
The bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for bit
manipulations where addresses and bit specifications are changed sequentially, so it is convenient for processing
data with long bit lengths bit-wise.
Fig. 5-8 Bit Sequential Buffer Format
Address
Bit
FC3H
3
Symbol
L Register L = F
2
1
FC2H
0
3
2
BSB3
1
FC1H
0
3
2
BSB2
L=CL=B
1
0
FC0H
3
2
1
BSB1
L=8L=7
0
BSB0
L=4 L=3
L=0
DECS L
INCS L
Remark
28
In "pmem.@L" addressing, the specified bit corresponding to the L register is moved.
µPD75312B, 75316B
6. INTERRUPT FUNCTION
The µPD75316B has six interrupt sources which enable multiple interrupt by software control. It also has two
test sources, of which the INT2 has two edge detection testable inputs.
Table 6-1. Types of Interrupt Sources
Interrupt sources
INTBT
(standard interval signal from basic
interval timer)
INT4
(both rising and falling edge
detection are valid.)
INT0
(Rising or falling detection edge is
selected.)
Internal/external
Interrupt priorityNote 1
Vectored interrupt request
signal (vector table address)
Internal
1
VRQ1 (0002H)
External
2
VRQ2 (0004H)
INT1
External
3
VRQ3 (0006H)
INTCSI (serial data transfer end signal)
Internal
4
VRQ4 (0008H)
Internal
5
VRQ5 (000AH)
INTT0
(match signal between the count
register and modulo register of
programmable timer/counter)
External
INT2Note 2 (rising edge detection of input to
INT2 pin or falling edge detection of
input to KR0-KR7)
External
INTWNote 2 (signal from clock timer)
Internal
Notes 1.
2.
Testable input signal (IRQ2 and IRWQ are set.)
Interrupt priority is serviced according to the order of priority, when several interrupt requests are
generated simultaneously.
Test source. They are affected by the interrupt enable flag in the same way as the interrupt source,
but no vectored interrupt is generated.
The µPD75316B interrupt control circuit has the following functions:
• Hardware control vectored interrupt function that can control interrupt acknowledgement by interrupt flag
(IE×××) and interrupt master enable flag (IME).
• Interrupt start address can be set.
• Interrupt request flag (IRQ×××) test function (interrupt generation confirmation by software possible).
• Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
29
30
Fig.6-1 Interrupt Control Circuit Block Diagram
Internal Bus
2
1
3
IM2
IM1
IM0
Interrupt Enable Flag (IE XXX )
INT1
/P11
INT2
/P12
KR7/P73
Both Edges
Detector
*
Edge
Detector
IRQ0
Edge
Detector
IRQ1
INTCSI
IRQCSI
INTT0
IRQT0
INTW
IRQW
Rising Edge
Detector
VRQn
IRQ4
Priority Control
Circuit
Vector
Table
Address
Generator
IRQ2
Standby Release
Signal
Falling Edge
Detector
IM2
*
Noise Eliminator
µPD75312B, 75316B
KR0/P60
IRQBT
Selector
INT0
/P10
IST0
Decoder
INT
BT
INT4
/P00
IME
µPD75312B, 75316B
7. STANDBY FUNCTION
To reduce the power consumption during program wait, the µPD75316B has two standby modes: STOP mode
and HALT mode.
Table 7-1 Operation Status at Standby Mode
STOP Mode
STOP instruction
HALT instruction
System clock at setting
Only main system clock settable
Main system clock or subsystem
clock settable
Clock generator
Only main system clock oscillation
stopped
Only CPU clock Φ stopped
(oscillation continued)
Basic interval timer
Stopped
Operable (IRQBT set at reference time
intervals)*
Serial interface
Operable only when external SCK
input selected as serial clock
Operable*
Timer/event counter
Operable only when TI0 pin input
specified as count clock
Operable*
Watch timer
Operable only when fXT selected as
count clock
Operable
LCD controller
Operable only when fXT selected as
LCDCL
Operable
External interrupt
INT1, 2, 4: Operable
Only INT0 inoperable
CPU
Stopped
Operation Status
Setting instruction
Release signal
*
HALT Mode
Interrupt request signal from operable
hardware enabled by interrupt enable
flag, or RESET input
Interrupt request signal from operable
hardware enabled by interrupt enable
flag, or RESET input
Cannot be operable during main system clock stop.
31
µPD75312B, 75316B
8. RESET FUNCTION
The µ PD75316B is reset and the hardware is initialized as shown in Table 8-1 by RESET input. The reset operation
timing is shown in Fig. 8-1.
Fig. 8-1 Reset Operation by RESET Input
Wait
(31.3 ms/4.19 MHz)
RESET Input
Operating Mode or Standby
Mode
HALT Mode
Operating Mode
Internal Reset Operation
Table 8-1 Status of Each Hardware after Resetting (1/3)
RESET Input in Standby
Mode
RESET Input During
Operation
Low-order 6 bits of program
memory address 0000H are
set in PC13 to 8 and the
contents of address 0001H
are set in PC7 to 0.
Same as the left
Held
Undefined
Skip flag (SK0 to 2)
0
0
Interrupt status flag (IST0)
0
0
Hardware
Program counter (PC)
Carry flag (CY)
PSW
Bank enable flag (MBE)
Stack pointer (SP)
32
Same as the left
Undefined
Undefined
Data memory (RAM)
Held*
Undefined
General register (X, A, H, L, D, E, B, C)
Held
Undefined
0
0
Bank selection register (MBS)
*
Bit 7 of program memory
address 0000H is set in
MBE.
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
µPD75312B, 75316B
Table 8-1 Status of Each Hardware after Resetting (2/3)
RESET Input in Standby
Mode
RESET Input During
Operation
Undefined
Undefined
Mode register (BTM)
0
0
Counter (T0)
0
0
FFH
FFH
0
0
0, 0
0, 0
0
0
Held
Undefined
Operating mode register (CSIM)
0
0
SBI control register (SBIC)
0
0
Held
Undefined
Processor clock control register (PCC)
0
0
System clock control register (SCC)
0
0
Clock output mode register (CLOM)
0
0
Display mode register (LCDM)
0
0
Display control register (LCDC)
0
0
Interrupt request flag (IRQ×××)
Reset (0)
Reset (0)
Interrupt enable flag (IE×××)
0
0
Interrupt master enable flag (IME)
0
0
0, 0, 0
0, 0, 0
Hardware
Basic interval
timer
Timer/event
counter
Counter (BT)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
Watch timer
Mode register (WM)
Shift register (SIO)
Serial interface
Slave address register (SVA)
Clock generator,
clock output
circuit
LCD controller
Interrupt function
INT0, 1, 2 mode registers (IM0, 1, 2)
33
µPD75312B, 75316B
Table 8-1 Status of Each Hardware after Resetting (3/3)
RESET Input in Standby
Mode
RESET Input During
Operation
Output buffer
OFF
OFF
Output latch
Clear (0)
Clear (0)
I/O mode register (PMGA, B)
0
0
Pull-up resistor specification register
(POGA)
0
0
Held
Undefined
Hardware
Digital port
Bit sequential buffer (BSB0 to 3)
34
µPD75312B, 75316B
9
INSTRUCTION SET
(1) Operand identifier and description method
The operand is described in the operand field of each instruction in accordance with the description method for
the operand identifier of the instruction. For details refer to RA75X Assembler Package User's Manual Language
Volume (EEU-1363). When there are multiple elements in the description method, one of the elements is selected.
Uppercase letters and symbols (+,–) are keywords and should be described without change as shown.
For immediate data, a suitable value or label is described.
Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (see the µPD75308
User’s Manual (IEM-1263) for details). However, there are restrictions on the labels for which fmem and pmem can
be used.
Identifier
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
XA, BC, DE, HL
BC, DE, HL
rp2
BC, DE
rpa
rpa1
HL, DE, DL
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem*
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
pmem
FB0H to FBFH, FF0H to FFFH immediate data or label
FC0H to FFFH immediate data or label
addr
*
Description
µPD75312B
0000H to 2F7FH immediate data or label
µPD75316B
0000H to 3F7FH immediate data or label
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
IE×××
MBn
IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW
MB0, MB1, MB2, MB3, MB15
PORT 0 to PORT 7
For mem, only even addresses can be entered in the case of 8-bit data processing.
35
µPD75312B, 75316B
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register;
36
C
D
E
H
:
:
:
:
C register;
D register;
E register;
H register;
L
X
XA
BC
:
:
:
:
L register;
X register;
Register pair (XA); 8-bit accumulator
Register pair (BC)
DE
HL
PC
SP
:
:
:
:
Register pair (DE)
Register pair (HL)
Program counter
Stack pointer
CY
PSW
MBE
PORTn
:
:
:
:
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Portn (n = 0 to 7)
IME
IE×××
MBS
PCC
:
:
:
:
Interrupt master enable flag
Interrupt enable flag
Memory bank selection register
Processor clock control register
.
(××)
××H
: Address, bit delimiter
: Contents addressed by ××
: Hexadecimal data
µPD75312B, 75316B
(3) Description of addressing area field symbols
*1
MB = MBE • MBS (MBS = 0 to 3, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0 to 3, 15)
*4
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
*7
µPD75312B
µPD75316B
Data Memory
Addressing
addr = 0000H to 2F7FH
addr = 0000H to 3F7FH
addr = (Current PC) –15 to (Current PC) –1,
(Current PC) +2 to (Current PC) + 16
caddr = 0000H to 0FFFH (PC13 = 0, PC12 = 0)or
µPD75312B
1000H to 1FFFH (PC13 = 0, PC12 = 1) or
2000H to 2F7FH (PC13 = 1, PC12 = 0)
*8
Program Memory
Addressing
caddr = 0000H to 0FFFH (PC13 = 0, PC12 = 0) or
µPD75316B
1000H to 1FFFH (PC13 = 0, PC12 = 1) or
2000H to 2FFFH (PC13 = 1, PC12 = 0) or
3000H to 3F7FH (PC13 = 1, PC12 = 1)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
Remarks
1.
MB indicates the accessible memory bank.
2.
3.
4.
For *2, MB = 0 without regard to MBE and MBS.
For *4 and *5, MB = 15 without regard to MBE and MBS.
*6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field
S shows the number of machine cycles required when skip is performed by an instruction with skip. The value
of S changes as follows:
• No skip ....................................................................................................................................................................... S = 0
• When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1
• When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction) ............................. S = 2
Caution One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (= tCY) of the CPU clock Φ. Three times can be selected by PCC
setting.
37
Bytes
Machine
Cycles
Note 1
µPD75312B, 75316B
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
Stack A
HL, #n8
2
2
HL ← n8
Stack B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
*1
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg
2
2
A ← reg
XA, rp
2
2
XA ← rp
reg1, A
2
2
reg1 ← A
rp1, XA
2
2
rp1 ← XA
A, @HL
1
1
A ↔ (HL)
*1
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A,reg1
1
1
A ↔ reg1
XA, rp
2
2
XA ↔ rp
XA, @PCDE
1
3
XA ← (PC13–8 + DE)ROM
XA, @PCXA
1
3
XA ← (PC13–8 + XA)ROM
A, #n4
1
1+S
A ← A + n4
A, @HL
1
1+S
A ← A + (HL)
*1
ADDC
A, @HL
1
1
A, CY ← A + (HL) + CY
*1
SUBS
A, @HL
1
1+S
A ← A – (HL)
*1
SUBC
A, @HL
1
1
A, CY ← A – (HL) – CY
*1
A, #n4
2
2
A ← A ∧ n4
A, @HL
1
1
A ← A ∧ (HL)
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
Mnemonic
Transfer
MOV
Note 2
XCH
Operand
MOVT
Operation
ADDS
AND
OR
XOR
Notes 1. Instruction Group
2. Table reference
38
Operation
Addressing Area
Skip Condition
Stack A
carry
*1
*1
*1
carry
borrow
Bytes
Machine
Cycles
Note 3
Note 2
Note 1
µPD75312B, 75316B
RORC
A
1
1
CY ← A0, A3 ← CY, An–1 ← An
NOT
A
2
2
A←A
reg
1
1+S
reg ← reg + 1
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1+S
reg ← reg – 1
reg = FH
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
A, reg
2
2+S
Skip if A = reg
SET1
CY
1
1
CY ← 1
CLR1
CY
1
1
CY ← 0
SKT
CY
1
1+S
NOT1
CY
1
1
CY ← CY
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem7–2 + L 3–2.bit (L1–0)) ← 1
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem7–2 + L 3–2.bit (L1–0)) ← 0
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 1
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 1
*1
(@H + mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 0
*5
(pmem.@L) = 0
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 0
*1
(@H + mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 1 and clear
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 1 and clear
*1
(@H + mem.bit) = 1
Mnemonic
INCS
Note 4
Comparison
DECS
SKE
SET1
Memory bit manipulation
CLR1
SKT
SKF
SKTCLR
Operand
Operation
Addressing Area
Skip Condition
reg = 0
A = reg
CY = 1
Skip if CY = 1
Notes 1. Instruction Group
2. Accumulator operation
3. Increment/decrement
4. Carry flag manipulation
39
Bytes
Machine
Cycles
Memory bit manipulation
Branch
2
CY ← CY ∧ (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY ∧ (pmem7–2 + L3–2.bit (L1–0))
*5
CY, @H + mem.bit 2
2
CY ← CY ∧ (H + mem3-0.bit)
*1
CY, fmem.bit
2
2
CY ← CY V (fmem.bit)
*4
OR1
CY, pmem.@L
2
2
CY ← CY V (pmem7–2 + L3–2.bit (L1–0))
*5
CY, @H + mem.bit 2
2
CY ← CY V (H + mem3-0.bit)
*1
CY, fmem.bit
2
2
CY ← CY V (fmem.bit)
*4
XOR1
CY, pmem.@L
2
2
CY ← CY V (pmem7–2 + L3–2.bit (L1–0))
*5
CY, @H + mem.bit 2
2
CY ← CY V (H + mem3-0.bit)
*1
*6
Addressing Area
addr
—
—
PC13–0 ← addr
(The assembler selects the optimum instruction
from among the BR !addr, BRCB !caddr, and BR
$addr instructions.)
!addr
3
3
PC13–0 ← addr
*6
$addr
1
2
PC13–0 ← addr
*7
BRCB
!caddr
2
2
PC13–0 ← PC13, 12 + caddr11–0
*8
CALL
!addr
3
3
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, 0, PC13, PC12
PC13–0 ← addr, SP ← SP – 4
*6
CALLF
!faddr
2
2
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, 0, PC13, PC12
PC13–0 ← 00, faddr, SP ← SP – 4
*9
RET
1
3
MBE, PC13, PC12 ← (SP + 1)3, 1, 0
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
RETS
1
3+S
MBE, PC13, PC12 ← (SP + 1)3, 1, 0
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4, then skip unconditionally
RETI
1
3
PC13, PC12 ← (SP + 1)1, 0
PC11–0 ← (SP) (SP + 3) (SP + 2)
PSW ← (SP + 4) (SP + 5), SP ← SP + 6
rp
1
1
(SP – 1) (SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← 0, SP ← SP – 2
rp
1
1
rp ← (SP + 1) (SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), SP ← SP + 2
2
2
IME ← 1
2
2
IE × × × ← 1
2
2
IME ← 0
2
2
IE × × × ← 0
BR
POP
EI
DI
IE × × ×
IE × × ×
Notes 1. Instruction Group
2. Interrupt control
40
Operation
V
Subroutine stack control
2
Operand
V
AND1
PUSH
Note 2
CY, fmem.bit
Mnemonic
V
Note 1
µPD75312B, 75316B
Skip Condition
Unconditional
Bytes
Machine
Cycles
Note 2
Input/output
Note 1
µPD75312B, 75316B
A, PORTn
2
2
A ← PORT n
(n = 0–7)
XA, PORTn
2
2
XA ← PORTn+1, PORTn
(n = 4, 6)
PORTn, A
2
2
PORTn ← A
(n = 2–7)
PORTn, XA
2
2
PORTn+1, PORTn ← XA
(n =4, 6)
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
2
2
MBS ← n (n = 0 to 3, 15)
Mnemonic
IN
OUT
Special
SEL
Operand
MBn
Addressing Area
Operation
• TBR Instruction
PC13–0 ← (taddr) 5–0 + (taddr + 1)
----------------------------------------------------------------------• TCALL Instruction
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
GETI
Caution:
taddr
1
3
(SP – 3) ← MBE, 0, PC 13, PC12
PC13–0 ← (taddr) 5–0 ← (taddr + 1)
SP ← SP – 4
----------------------------------------------------------------------• Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
Skip Condition
-----------------------------
*10
----------------------------Conforms to
referenced
instruction.
At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance.
Notes 1. Instruction Group
2. CPU control
Remark
The TBR and TCALL instructions are assembler pseudo instructions for GETI instruction table definition.
41
µPD75312B, 75316B
10. MASK OPTION SELECTION
The following mask options are available at the pins:
Pin Function
42
Mask Option
P40 to P43,
• Pull-up resistor (specifiable bit-wise)
P50 to P53
• No pull-up resistor (specifiable bit-wise)
VLC0 to VLC2,
• LCD drive power supply split resistor (specified in units of 4)
BIAS
• No LCD drive power supply split resistor (specified in units of 4)
µPD75312B, 75316B
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
Supply voltage
TEST CONDITIONS
SYMBOL
VDD
VI1
Except ports 4, 5
Input voltage
On-chip pull-up resistor
VI2
Output voltage
VO
Output current, high
IOH
Ports 4, 5
Open-drain
IOL*
–0.3 to +7.0
V
–0.3 to VDD +0.3
V
–0.3 to VDD +0.3
V
–0.3 to +11
V
–0.3 to VDD +0.3
V
–15
mA
All output pins
–30
mA
Peak value
30
mA
Effective value
15
mA
Peak value
100
mA
Effective value
60
mA
Peak value
100
mA
Effective value
60
mA
Total of ports 0, 2, 3, 5
Total of ports 4, 6, 7
*
UNIT
Per pin
Per pin
Output current, low
RATING
Operating temperature
Topt
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Calculate the effective value with the formula [Effective value] = [Peak value] × √duty.
Caution:
If even one parameter exceeds the absolute maximum rating, even momentarily, the quality of the
product may be impaired. The absolute maximum rating is a rated threshold value at which the product
can be physically damaged. Be sure to use the product within the absolute maximum ratings.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
Input /output
capacitance
SYMBOL
TEST CONDITIONS
CIN
COUT
CIO
f = 1 MHz
Unmeasured pin returned to 0 V
MIN.
TYP.
MAX.
UNIT
15
pF
15
pF
15
pF
43
µPD75312B, 75316B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
X1
Ceramic
resonator
C2
Oscillation stabilization
time *2
VDD
X1
TEST CONDITIONS
Oscillator frequency
(fXX) *1
X2
C1
PARAMETER
Crystal
resonator
TYP.
1.0
After VDD reaches the
minimum value in the
oscillation voltage
range
Oscillator frequency
(fXX) *1
X2
MIN.
1.0
4.19
VDD = 4.5 to 6.0 V
C1
C2
Oscillation stabilization
time *2
VDD
X1
X2
External
clock
µPD74HCU04
MAX.
UNIT
5.0*3
MHz
4
ms
5.0*3
MHz
10
ms
30
ms
X1 input frequency
(fX) *1
1.0
5.0*3
MHz
X1 input high and low
level widths (tXH, tXL)
100
500
ns
* 1.
For the oscillator frequency and the X1 input frequency, only the characteristics of the oscillation circuit are
shown. For the instruction execution time, refer to the AC characteristics.
2. Time required for oscillation to become stabilized after VDD application or STOP mode release.
3.
When the oscillator frequency is 4.19 MHz < fXX ≤ 5.0 MHz, do not select PPC = 0011 as instruction execution
time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 µs, with the result that specified MIN.
value 0.95 µs cannot be observed.
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
XT1
R
C3
TEST CONDITIONS
Oscillator frequency
(f XT)
XT2
Crystal
resonator
PARAMETER
C4
MIN.
TYP.
MAX.
UNIT
32
32.768
35
kHz
1.0
2
s
10
s
VDD = 4.5 to 6.0 V
Oscillation stabilization
time*
VDD
X1
X2
XT1 input frequency
(f XT)
32
100
kHz
XT1 input high and low
level widths (t XTH, tXTL)
5
15
µs
External
clock
Open
*
44
Time required for oscillation to become stabilized after VDD application.
µPD75312B, 75316B
Caution:
When the main system clock oscillator or subsystem clock oscillator is used, the shaded area in the
figures should be wired as follows to prevent influence from the wiring capacitance, etc.
• Wiring should be as short as possible.
• Do not cross signal lines.
• Do not place the circuit close to a line in which varying high current flows.
• The connecting point of oscillator capacitor should always be the same potential as VDD. Do not connect
it to the power supply pattern in which high current flows.
• Do not fetch a signal from the oscillator.
When the subsystem clock is used, special care is needed for the wiring. The subsystem clock oscillator
is designed to be low-amplification circuit for low current consumption, thus mulfunction due to noise
occurs more often than with the main system clock oscillator.
45
µPD75312B, 75316B
RECOMMENDED OSCILLATOR CONSTANTS
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (Ta = –40 to +85 ˚C)
Recommended constants
Manufacture
Product Name
C1 (pF)
MURATA
Oscillator voltage range (V)
Frequency (MHz)
CSB × × × × J
1.000 to 1.250
CSA×. × × ×MK040
1.251 to 1.799
C2 (pF)
R (kΩ)
MIN.
MAX.
2.0
6.0
5.6
100
100
Internal
Internal
30
30
Internal
Internal
CSA ×. × × MG040
CST ×. × × MG040
1.800 to 2.440
CSA ×. × × MG
CST ×. × × MGW
–
2.450 to 5.000
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (Ta = –40 to +85 ˚C)
Recommended constants Oscillator voltage range (V)
Manufacture
KYOCERA
Product Name
Frequency (MHz)
C1 (pF)
C2 (pF)
100
100
33
33
MIN.
MAX.
2.0
6.0
KBR-1000Y
1.00
KBR-1000F
KBR-2.0MS
2.00
PBRC 2.00A
KBR-4.0MSA
PBRC 4.00A
4.00
KBR-4.0MKS
Internal
Internal
33
33
Internal
Internal
KBR-4.0MWS
KBR-5.0MSA
PBRC 5.00A
6.00
KBR-5.0MKS
KBR-5.0MWS
46
µPD75312B, 75316B
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (Ta = –40 to +85 ˚C)
Recommended constants Oscillator voltage range (V)
Manufacture
TOKOU
Product Name
Frequency (MHz)
CRHF 2.50
2.5
CRHF 3.00
3.0
CRHF 4.00
4.0
CRHF 5.00
5.0
C1 (pF)
C2 (pF)
MIN.
MAX.
30
30
2.0
6.0
SUBSYSTEM CLOCK: CRYSTAL RESONATOR (Ta = –15 to +60 ˚C)
Recommended constants
Manufacture
KYOCERA
Caution:
Product Name
KF-38G
Oscillator voltage range (V)
Frequency (MHz)
32.768
C3 (pF)
C4 (pF)
R (kΩ)
MIN.
MAX.
18
33
220
2.0
6.0
Make the fine-adjustment of crystal resonator frequency with external capacitor C1 or C3.
47
µPD75312B, 75316B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V ) (1/2)
PARAMETER
Input voltage,
high
SYMBOL
TEST CONDITIONS
TYP.
MAX.
UNIT
VIH1
Ports 2 and 3
0.7 VDD
VDD
V
VIH2
Ports 0, 1, 6, 7, RESET
0.8 VDD
VDD
V
VIH3
Ports 4 and 5
On-chip pull-up resistor 0.7 VDD
Open-drain
Input voltage,
low
MIN.
VDD
V
0.7 VDD
10
V
VDD –0.5
VDD
V
VIH4
X1, X2, XT1
VIL1
Ports 2, 3, 4 and 5
0
0.3 VDD
V
VIL2
Ports 0, 1, 6, 7, RESET
0
0.2 VDD
V
VIL3
X1, X2, XT1
0
0.4
V
VOH1
Ports
0, 2, 3, 6, 7,
BIAS
Output voltage,
high
V0H2
VOL1
BP0 to BP7
(with 2 IOH outputs)
Ports
0, 2, 3, 4, 5, 6
and 7
Output voltage,
low
SB0, 1
VOL2
BP0 to BP7
(with 2 IOL outputs)
ILIH1
VDD = 4.5 to
6.0 V
IOH = –1mA
VDD –1.0
V
IOH = –100 µA
VDD –0.5
V
VDD = 4.5 to
6.0 V
IOH = –100 µA
VDD –2.0
V
IOH = –30 µA
VDD –1.0
V
Ports 3, 4, 5
VDD = 4.5 to
6.0 V
IOL = 15 mA
0.5
2.0
V
VDD = 4.5 to
6.0 V
IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
Open-drain
pull-up
resistor ≥ 1 kΩ
0.2 VDD
V
VDD = 4.5 to
6.0 V
IOL = 100 µA
1.0
V
IOL = 50 µA
1.0
V
3
µA
X1, X2, XT1
20
µA
Ports 4 and 5
(when open
-drain)
20
µA
Other than below
-3
µA
-20
µA
Other than below
VIN = VDD
Input leakage
current, high
ILIH2
ILIH3
Input leakage
current, low
ILIL1
VIN = 0 V
ILIL2
48
VIN = 10 V
X1, X2, XT1
µPD75312B, 75316B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V ) (2/2)
PARAMETER
SYMBOL
TEST CONDITIONS
TYP.
MAX.
UNIT
ILOH1
VOUT = VDD
Other than
below
3
µA
ILOH2
VOUT = 10 V
Ports 4 and 5
(when opendrain)
20
µA
ILOL
VOUT = 0 V
–3
µA
80
kΩ
RL1
Ports 0, 1, 2, 3, 6
and 7 (Except P00)
VIN = 0 V
200
kΩ
Output leakage
current, high
Output leakage
current, low
MIN.
On-chip pull-up
resistor
RL2
Ports 4, 5
VOUT = V DD -2.0 V
VDD = 5.0 V
±10%
15
VDD = 3.0 V
±10%
30
VDD = 5.0 V
±10%
15
40
70
kΩ
VDD = 3.0 V
±10%
15
40
70
kΩ
VDD
V
150
kΩ
0
±0.2
V
0
±0.2
V
LCD drive voltage
VLCD
2.0
LCD split resistor
RLCD
60
LCD output
voltage
deviation*1
(common)
VODC
IO = ±5 µA
LCD output
voltage
deviation*1
(segment)
VODS
IO = ±1µA
IDD1
4.19 MHz*3 crystal
oscillation C1=C2=
22 pF
VLCD0 = VLCD
VLCD1 =
VLCD × 2/3
VLCD2 = VLCD
× 1/3
2.7 V ≤ VLCD
≤ V DD
3.0
9
mA
VDD = 3 V
±10%*5
0.4
1.2
mA
VDD =
5V
±10%
1
3
mA
VDD =
3V
±10%
300
900
µA
VDD = 3 V
±10%
20
60
µA
HALT
mode
7
21
µA
1
25
µA
0.5
15
µA
0.5
5
µA
Supply current *2
IDD3
32 kHz *6
crystal oscillation
IDD4
VDD =
3V
±10%
VDD = 5 V±10%
IDD5
XT1 = 0 V
STOP mode
100
VDD = 5 V
±10%*4
HALT
mode
IDD2
40
VDD =
3V
±10%
Ta =
25°C
49
µPD75312B, 75316B
* 1.
2.
3.
4.
5.
6.
50
The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n =
0, 1, 2) and output voltage.
Current flowing in the internal pull-up resistor and LCD split resistor are not included.
Includes the case when the subsystem clock is oscillated.
When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode.
When the PCC is set to 0000 and operated in low-speed mode.
When operated by the subsystem clock with the system clock control register (SCC) set to 1001 and the
main system clock oscillation stopped.
µPD75312B, 75316B
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V )
PARAMETER
SYMBOL
tCY
TI0 input frequency
fTI
TI0 input high- and lowlevel widths
tTIH,
Interrupt input high- and
low-level widths
tINTH,
* 1.
TYP.
MAX.
UNIT
0.95
64
µs
3.8
64
µs
125
µs
Operation with
subsystem clock
114
VDD = 4.5 to 6.0 V
0
1
MHZ
0
275
kHz
122
0.48
µs
1.8
µs
INT0
*2
µs
INT1, 2, 4
10
µs
KR0–7
10
µs
10
µs
VDD = 4.5 to 6.0 V
tTIL
tINTL
tRSL
CPU clock (Φ) cycle time is determined by oscillation frequency of the connected resonator, system
clock control register (SCC) and processor clock
tCY
64
60
6
5
Operation guarantee range
4
Cycle Time tCY [µs]
It becomes 2tCY or 128/fX by interrupt mode register
(IM0) setting.
VS VDD
(Main System Clock in Operation)
70
control register (PCC).
Characteristics for supply voltage VDD vs. Cycle
time t CY in main system clock operation is shown
below.
2.
MIN.
VDD = 4.5 to 6.0 V
Operation with main
system clock
CPU clock cycle time
(minimum instruction
execution time = one
machine cycle)*1
RESET low-level width
TEST CONDITIONS
3
2
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
51
µPD75312B, 75316B
SERIAL TRANSFER OPERATION
2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY1/2–50
ns
tKCY1
tKL1
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH1
tKCY1/2–150
ns
SI setup time (to SCK↑)
tSIK1
150
ns
SI hold time (from SCK↑)
tKSI1
400
ns
SO output delay time
from SCK↓
tKSO1
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
250
ns
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
2-wire and 3-wire serial I/O mode (SCK...External clock input): (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY2
tKL2
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH2
1600
ns
SI setup time (to SCK↑)
tSIK2
100
ns
SI hold time (from SCK↑)
tKSI2
400
ns
SO output delay time
from SCK↓
tKSO2
*
52
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
RL and CL are SO output line load resistance and load capacitance, respectively.
300
ns
1000
ns
µPD75312B, 75316B
SBI mode (SCK...Internal clock output (master)): (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY3/2–50
ns
tKCY3
tKL3
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH3
t KCY3/2–150
ns
SB0 and SB1 setup time (to SCK↑)
tSIK3
150
ns
SB0 and SB1 hold time (from SCK↑)
tKSI3
tKCY3/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO3
SB0, SB1↓ from SCK↑
tKSB
tKCY3
ns
SCK↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0 and SB1 low-level widths
tSBL
tKCY3
ns
SB0 and SB1 high-level widths
tSBH
tKCY3
ns
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively.
SBI mode (SCK...External clock input (slave)): (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY4
tKL4
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH4
1600
ns
SB0 and SB1 setup time (to SCK↑)
tSIK4
100
ns
SB0 and SB1 hold time (from SCK↑)
tKSI4
tKCY4/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO4
SB0, SB1↓ from SCK↑
tKSB
tKCY4
ns
SCK↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0 and SB1 low-level widths
tSBL
tKCY4
ns
SB0 and SB1 high-level widths
tSBH
tKCY4
ns
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively.
53
µPD75312B, 75316B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V ) (1/2)
PARAMETER
Input voltage,
high
SYMBOL
TEST CONDITIONS
TYP.
MAX.
UNIT
VIH1
Ports 2 and 3
0.8 VDD
VDD
V
VIH2
Ports 0, 1, 6, 7, RESET
0.8 VDD
VDD
V
VIH3
Ports 4 and 5
On-chip pull-up resistor 0.8 VDD
VDD
V
0.8 VDD
10
V
VDD –0.3
VDD
V
Open-drain
Input voltage,
low
MIN.
VI H4
X1, X2, XT1
VIL1
Ports 2, 3, 4 and 5
0
0.2 VDD
V
VIL2
Ports 0, 1, 6, 7, RESET
0
0.2 VDD
V
VIL3
X1, X2, XT1
0
0.25
V
VOH1
Ports
0, 2, 3, 6, 7,
BIAS
IOH = –100 µA
VDD –0.5
V
VOH2
BP0 to BP7
(with 2 IOH outputs)
IOH = –10 µA
VDD –0.4
V
Output voltage,
high
Ports
0, 2, 3, 4, 5, 6
and 7
IOL = 400 µA
0.5
V
VOL1
Output voltage,
low
SB0, 1
VOL2
BP0 to BP7
(with 2 IOL outputs)
ILIH1
Open-drain
pull-up
resistor ≥ 1 kΩ
IOL = 10 µA
0.2 VDD
0.4
V
V
3
µA
X1, X2, XT1
20
µA
Ports 4 and 5
(when open
-drain)
20
µA
Other than below
–3
µA
X1, X2, XT1
–20
µA
Other than below
3
µA
Ports 4 and 5
(when open
-drain)
20
µA
–3
µA
Other than below
VIN = VDD
Input leakage
current, high
ILIH2
ILIH3
Input leakage
current, low
VIN = 10 V
ILIL1
VIN = 0 V
ILIL2
ILOH1
VOUT = VDD
ILOH2
VOUT = 10 V
ILOL
VOUT = 0 V
Output leakage
current, high
Output leakage
current, low
54
µPD75312B, 75316B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V ) (2/2)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
600
kΩ
70
kΩ
VDD
V
150
kΩ
0
±0.2
V
0
±0.2
V
RL1
Ports 0, 1, 2, 3, 6
and 7 (except P00)
VIN = 0 V
VDD = 2.5 V
±10%
50
RL2
Ports 4, 5
VOUT = V DD -1.0 V
VDD = 2.5 V
±10%
15
TYP.
On-chip pull-up
resistor
LCD drive voltage
VLCD
2.0
LCD split resistor
RLCD
60
LCD output
voltage
deviation*1
(common)
VODC
IO = ±5 µA
LCD output
voltage
deviation*1
(segment)
VODS
IO = ±1µA
VLCD0 = VLCD
VLCD1 =
VLCD × 2/3
VLCD2 = VLCD
× 1/3
2.0 V ≤ VLCD
≤ V DD
40
100
VDD = 3 V
±10%*4
0.4
1.2
mA
VDD = 2.5 V
±10%*4
0.3
0.9
mA
VDD =
3V
±10%
300
900
µA
VDD =
2.5 V
±10%
200
600
µA
VDD = 3 V
±10%
20
60
µA
VDD = 2.5 V
±10%
15
45
µA
VDD =
3V
±10%
7
21
µA
VDD =
2.5 V
±10%
4
12
µA
0.5
15
µA
0.5
5
µA
0.4
15
µA
0.4
5
µA
IDD1
4.19 MHz*3 crystal
oscillation
C1=C2=22 pF
Low-speed mode
HALT
mode
IDD2
Supply current *2
IDD3
32 kHz *5
crystal oscillation
IDD4
HALT
mode
VDD =
3V
±10%
IDD5
XT1 = 0 V
STOP mode
VDD =
2.5 V
±10%
Ta =
25°C
Ta =
25°C
55
µPD75312B, 75316B
* 1.
2.
3.
4.
5.
56
The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n =
0, 1, 2) and output voltage.
Current flowing in the on-chip pull-up resistor and LCD split resistor are not included.
Includes the case when the subsystem clock is oscillated.
When the PCC is set to 0000 and operated in low-speed mode.
When operated by the subsystem clock with the system clock control register (SCC) set to 1001 and the
main system clock stopped.
µPD75312B, 75316B
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V )
PARAMETER
CPU clock cycle time
(minimum instruction
execution time = one
machine cycle)*1
SYMBOL
tCY
TEST CONDITIONS
Operation with main
system clock
MIN.
tTIH,
Interrupt input high- and
low-level widths
tINTH,
RESET low-level width
* 1.
UNIT
3.8
64
µs
VDD = 2.0 to 6.0 V
5
64
µs
Ta = –4.0 to +6.0 V
VDD = 2.2 to 6.0 V
3.4
64
µs
125
µs
275
kHz
114
fTI
TI0 input high- and lowlevel widths
MAX.
VDD = 2.7 to 6.0 V
Operation with
subsystem clock
TI0 input frequency
TYP.
122
0
1.8
µs
INT0
*2
µs
INT1, 2, 4
10
µs
KR0–7
10
µs
10
µs
tTIL
tINTL
tRSL
CPU clock (Φ) cycle time is determined by oscillation frequency of the connected resonator, system
clock control register (SCC) and processor clock
control register (PCC).
Characteristics for supply voltage VDD vs. Cycle
tCY
VS VDD
(Main System Clock in Operation)
70
64
60
time t CY in main system clock operation is shown
below.
2. It becomes 2tCY or 128/fX by interrupt mode register
(IM0) setting.
6
5
Operation guarantee range
Cycle Time tCY [µs]
4
3
2
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
57
µPD75312B, 75316B
SERIAL TRANSFER OPERATION
2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY1/2–50
ns
tKCY1
tKL1
VDD = 4.5 to 6.0 V
SCK high- and low-level
width
tKH1
t KCY1/2–150
ns
SI setup time (to SCK↑)
tSIK1
250
ns
SI hold time (from SCK↑)
tKSI1
400
ns
SO output delay time
from SCK↓
tKSO1
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
250
ns
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
2-wire and 3-wire serial I/O mode (SCK...External clock input): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY2
tKL2
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH2
1600
ns
SI setup time (to SCK↑)
tSIK2
100
ns
SI hold time (from SCK↑)
tKSI2
400
ns
SO output delay time
from SCK↓
tKSO2
*
58
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
RL and CL are SO output line load resistance and load capacitance, respectively.
300
ns
1000
ns
µPD75312B, 75316B
SBI mode (SCK...Internal clock output (master)): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY3/2–50
ns
tKCY3
tKL3
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH3
tKCY3/2–150
ns
SB0 and SB1 setup time (to SCK↑)
tSIK3
250
ns
SB0 and SB1 hold time (from SCK↑)
tKSI3
tKCY3/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO3
SB0, SB1↓ from SCK↑
tKSB
tKCY3
ns
SCK from SB0, SB1↓
tSBK
tKCY3
ns
SB0 and SB1 low-level widths
tSBL
tKCY3
ns
SB0 and SB1 high-level widths
tSBH
tKCY3
ns
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively.
SBI mode (SCK...External clock input (slave)): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V )
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY4
tKL4
VDD = 4.5 to 6.0 V
SCK high- and low-level
widths
tKH4
1600
ns
SB0 and SB1 setup time (to SCK↑)
tSIK4
100
ns
SB0 and SB1 hold time (from SCK↑)
tKSI4
tKCY4/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO4
SB0, SB1↓ from SCK↑
tKSB
tKCY4
ns
SCK from SB0, SB1↓
tSBK
tKCY4
ns
SB0 and SB1 low-level widths
tSBL
tKCY4
ns
SB0 and SB1 high-level widths
tSBH
tKCY4
ns
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively.
59
µPD75312B, 75316B
AC Timing Test Points (except X1 and XT1 input)
0.8 VDD
0.8 VDD
Test points
0.2 VDD
0.2 VDD
Clock Timing
1/fX
tXL
tXH
X1 input
V DD -0.5 V
0.4 V
1/fXT
tXTL
tXTH
XT1 input
V DD -0.5 V
0.4 V
TI0 Timing
1/fTI
tTIL
TI0
60
tTIH
µPD75312B, 75316B
Serial Transfer Timing
3-wire serial I/O mode:
tKCY1
tKL1
tKH1
SCK
tSIK1
SI
tKSI1
Input data
tKSO1
SO
Output data
2-wire serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
tKSI2
SBO, 1
tKSO2
61
µPD75312B, 75316B
Serial Transfer Timing
Bus release signal transfer:
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSIK3, 4
tSBK
tSBH
SB0, 1
tKSO3, 4
Command signal transfer:
tKCY3, 4
tKL3, 4
CK
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
SB0, 1
B0, 1
tKSO3, 4
Interrupt Input Timing
tINTL
INT0, 2, 4
KR0–7
RESET Input Timing
tRSL
RESET
62
tINTH
tKSI3, 4
tKSI3, 4
µPD75312B, 75316B
DATA RETENTION CHARACTERISTICS IN DATA MEMORY STOP MODE AND LOW SUPPLY VOLTAGE
(Ta = –40 to +85 °C)
PARAMETER
SYMBOL
Data retention supply voltage
VDDDR
Data retention supply current *1
IDDDR
Release signal set time
tSREL
Oscillation stabilization wait
time *2
tWAIT
* 1.
2.
3.
TEST CONDITIONS
MIN.
TYP.
2.0
VDDDR = 2.0 V
0.3
MAX.
UNIT
6.0
V
15
µA
µs
0
Release by RESET
217/fX
ms
*3
ms
Release by interrupt request
Current to the on-chip pull-up resistor is not included.
Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
According to the setting of the basic interval timer mode register (BTM) (see below).
Wait Time
BTM3
BTM2
BTM1
BTM0
(Values at f X = 4.19 MHz in parentheses)
—
0
0
0
220/f X (approx. 250 ms)
—
0
1
1
217/fX (approx. 31.3 ms)
—
1
0
1
215/fX (approx. 7.82 ms)
—
1
1
1
213/fX (approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
63
µPD75312B, 75316B
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
64
µPD75312B, 75316B
12. CHARACTERISTIC CURVES (For Reference Only)
IDD vs VDD (Ceramic Oscillation: 4.19 MHz)
(Ta = 25 ˚C)
5000
High-speed mode PCC = 0011
Middle-speed mode PCC = 0010
Low-speed mode PCC = 0000
Main system clock
HALT mode
1000
Power supply current IDD (µA)
500
100
Main system clock
STOP mode
+ subsystem clock
operating mode
50
Main system clock
STOP mode
+ 32 kHz oscillation
only or subsystem
clock HALT mode
10
5
X1
X2
Ceramic
resonator
CSA4.19 MG
30 pF
30 pF
VDD
XT1
XT2
Crystal
32.768 kHz
330 kΩΩ
22 pF
22 pF
VDD
1
0
1
2
3
5
4
Power supply voltage VDD (V)
6
7
65
µPD75312B, 75316B
IDD vs VDD (Ceramic Oscillation: 2.00 MHz)
(Ta = 25 ˚C)
5000
High-speed mode PCC = 0011
Middle-speed mode PCC = 0010
Low-speed mode PCC = 0000
Main system clock
HALT mode
1000
Power supply current IDD (µA)
500
100
Main system clock
STOP mode
+ subsystem clock
operating mode
50
Main system clock
STOP mode
+ 32 kHz oscillation
only or subsystem
clock HALT mode
10
5
X1
X2
Ceramic
resonator
CSA2.00 MG 040
100 pF
100 pF
VDD
1
0
66
1
2
3
4
Power supply voltage VDD (V)
5
6
XT1
XT2
Crystal
32.768 kHz
330 kΩΩ
22 pF
22 pF
VDD
7
µPD75312B, 75316B
IOL vs VOL (Port 0, 2, 6, and 7)
(Ta = 25˚C)
VDD = 5 V
VDD = 4 V
VDD = 6 V
20
IOL (mA)
VDD = 3 V
10
VDD = 2.0 V
0
0
1.0
3.0
2.0
VOL (V)
IOL vs VOL (Port 3, 4, and 5)
(Ta = 25˚C)
VDD = 5 V
VDD = 6 V
VDD = 4 V
20
IOL (mA)
VDD = 3 V
10
VDD = 2.0 V
0
0
1.0
2.0
VOL (V)
3.0
67
µPD75312B, 75316B
IOH vs V OH
(Ta = 25˚C)
VDD = 5 V
VDD = 6 V
VDD = 4 V
10
IOH (mA)
VDD = 3 V
5
VDD = 2.0 V
0
0
1.0
2.0
VDD–VOH (V)
68
3.0
µPD75312B, 75316B
13. PACKAGE DRAWINGS
80 PIN PLASTIC QFP ( 14)
A
B
41
40
60
61
Q
5°±5°
S
C
D
detail of lead end
21
20
F
80
1
G
H
I M
J
M
P
K
N
L
S80GC-65-3B9-3
NOTE
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2 ± 0.4
0.677 ± 0.016
B
14.0 ± 0.2
0.551+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.2 ± 0.4
0.677 ± 0.016
F
0.8
0.031
G
0.8
0.031
H
0.30 ± 0.10
0.012+0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6 ± 0.2
0.063 ± 0.008
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
69
µPD75312B, 75316B
80 PIN PLASTIC TQFP (FINE PITCH) (
12)
A
B
60
41
61
40
21
F
80
1
20
H
I
M
J
K
M
P
G
R
Q
S
D
C
detail of lead end
N
L
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
14.0±0.2
INCHES
0.551 +0.009
–0.008
B
12.0±0.2
0.472 +0.009
–0.008
C
12.0±0.2
0.472 +0.009
–0.008
D
14.0±0.2
0.551 +0.009
–0.008
F
1.25
0.049
G
1.25
0.049
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.145 +0.055
–0.045
0.006±0.002
N
0.10
0.004
P
1.05
0.041
Q
0.05±0.05
0.002±0.002
R
5°±5°
5°±5°
S
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-4
70
µPD75312B, 75316B
14. RECOMMENDED SOLDERING CONDITIONS
The product should be soldered and mounted under the conditions recommended in the table below.
For the details of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 14-1 Surface Mounting Type Soldering Conditions
µPD75312BGC-×××-3B9 : 80-pin plastic QFP (14 x 14 mm)
µPD75316BGC-×××-3B9 : 80-pin plastic QFP (14 x 14 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235 °C, Time: Within 30 s (at 210 °C or higher), Count:
Twice or less
<Attention>
Infrared reflow
(1)
(2)
Perform the second reflow when the device temperature has come down to
the room temperature from the heating by the first reflow.
Do not wash flux away with water after the first reflow.
IR35-00-2
Package peak temperature: 215 °C, Time: Within 40 s (at 200 °C or higher), Count:
Twice or less
<Attention>
VPS
(1)
(2)
Perform the second reflow when the device temperature has come down to
the room temperature from the heating by the first reflow.
Do not wash flux away with water after the first reflow.
Wave soldering
Soldering tank temperature: 260 °C or less, Time: Within 10 s, Count: Once,
Preheating temperature: 120 °C MAX. (package surface temperature)
Partial heating
Pin temperature: 300 °C or less, Time: Within 3 s (per side of device)
Caution:
VP15-00-2
WS60-00-1
Do not use several soldering methods in combination (except partial heating).
71
µPD75312B, 75316B
µPD75312BGK-×××-3B9 : 80-pin plastic QFP (12 x 12 mm)
µPD75316BGK-×××-3B9 : 80-pin plastic QFP (12 x 12 mm)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235 °C, Time: Within 30 s (at 210 °C or higher), Count:
Twice or less, Exposure limit : Seven* days (after seven days, prebake at 125 °C
is required for 10 hours)
<Attention>
(1)
(2)
(1)
(2)
Partial heating
*
VP15-107-2
Perform the second reflow at the time the device temperature has come down
to the room temperature from the heating by the first reflow.
Do not wash flux away with water after the first reflow.
Pin temperature: 300 °C or less, Time: Within 3 s (per side of device)
For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65 % RH.
Caution:
72
IR35-107-2
Perform the second reflow when the device temperature has come down to
the room temperature from the heating by the first reflow.
Do not wash flux away with water after the first reflow.
Package peak temperature: 215 °C, Time: Within 40 s (at 200 °C or higher), Count:
Twice or less, Exposure limit : Seven*days (after seven days, prebake at 125 °C
is required for 10 hours)
<Attention>
VPS
Recommended
Condition Symbol
Do not use several soldering methods in combination (except partial heating).
µPD75312B, 75316B
APPENDIX A. DIFFERENCES AMONG µPD75308B SERIES PRODUCTS
Name
Item
µPD75304B/75306B/75308B µPD75312B µPD75316B
Supply voltage range
µPD75P316A
2.0 to 6.0 V
ROM configuration
EPROM/one-time PROM
Mask ROM
Program memory (bytes)
4096/6016/8064
12160
16256
512
Data memory (× 4 bits)
Instruction cycle
µPD75P316B
1024
0.95 µs, 1.91 µs, 15.3 µs (main system clock:@ 4.19 MHz)
122 µs (subsystem clock:@ 32.768 kHz)
8
CMOS input
Pull-up resistor can be incorporated by software: 23
Input/
output
port
16
CMOS input/output
40
CMOS output
8
Used with segment pin
N-ch open-drain
input/output
8
10-V withstand voltage, pull-up resistor
can be incorporated by mask option.
10-V withstand voltage,
without pull-up resistor option
• Common output: Static – 1/4 duty selected
• Segment output: Max. 32
LCD controller/driver
LCD drive split resistor can be incorporated
by mask option.
LCD drive voltage
2.0 V to VDD
Timer/counter
• 8-bit timer/event counter
• 8-bit basic interval timer
• Watch timer
Serial interface
• NEC standard serial bus interface (SBI)
• Clocked serial interface
Vectored interrupts
• External: 3
• Internal: 3
Test input
• External: 1
• Internal: 1
Clock output (PCL)
Φ, 524 kHz, 262 kHz, 65.5 kHz (main system clock:@ 4.19 MHz)
Buzzer output (BUZ)
2 kHz (main system clock:@ 4.19 MHz, or subsystem clock:@ 32.768 KHz)
Package
On-chip PROM product
*
No LCD drive split resistor
80-pin plastic QFP
(14 x 20 mm)
80-pin plastic QFP
(14 x 14 mm)
80-pin plastic TQFP
(Fine pitch) (12 x 12 mm)
GF package
: µPD75P316A
GC/GK package : µ PD75P316B
80-pin plastic QFP
(14 x 14 mm)
80-pin plastic TQFP
(Fine pitch)
(12 x 12 mm)
80-pin plastic QFP
(14 x 14 mm)
80-pin plastic TQFP
(Fine pitch)
(12 x 12 mm)
80-pin ceramic
WQFN*
80-pin plastic QFP
(14 x 20 mm)
80-pin ceramic
WQFN
µPD75P316B
Under development
73
µPD75312B, 75316B
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD75312B, 75316B.
IE-75000-R*1
75X series in-circuit emulator
IE-75001-R
IE-75000-R-EM*2
Emulation board for the IE-75000-R and the IE-75001-R
EP-75308BGC-R
Emulation probe for the µPD75312BGC and the 75316BGC.
80-pin conversion socket EV-9200GC-80 is also provided.
Hardware
EV-9200GC-80
EP-75308BGK-R
Software
EV-9200GK-80
PG-1500
PROM programmer
PA-75P316BGC
PROM programmer adapter for the µPD75P316BGC, connect to
PG-1500.
PA-75P316BGK
PROM programmer adapter for the µPD75P316BGK, connect to
PG-1500.
IE control program
PG-1500 controler
RA75X relocatable assembler
* 1.
2.
3.
Emulation probe for the µPD75312BGK and the 75316BGK.
80-pin conversion socket EV-9200GK-80 is also provided.
Host machine
PC-9800 series (MS-DOS Ver.3.30 to Ver.5.00A*3)
IBM PC/AT (See "OS for IBM PC")
Maintenance products
Not incorporated in IE-75001-R.
The task-swap function is provided with the Ver.5.00/5.00A and cannot be used with this software.
OS for IBM PC
The following OSs are supported for IBM PC
OS
Version
PC DOS
Ver.5.0.2 to Ver.6.1
J6.03/V
MS-DOS
Ver.3.30 to Ver.5.00A
5.0/V, J6.2/V
IBM DOS
J5.02/V
Caution:
74
Ver.5.0 or higher contains a task swap function; however, this function cannot be used by this software.
µPD75312B, 75316B
APPENDIX C. RELATED DOCUMENTATION
List of Device-Related Documents
Document Name
Document No.
User's Manual
IEM-1263
IEM-1239
Application Note
IEM-1245
75X Series Selection Guide
IF-1027
List of Development Tool-Related Documents
Software
Hardware
Document Name
Document No.
IE-75000-R/IE-75001-R User's Manual
EEU-1416
IE-75000-R-EM User's Manual
EEU-1294
EP-75308BGC-R User's Manual
EEU-1406
EP-75308BGK-R User's Manual
EEU-1408
PG-1500 User's Manual
EEU-1335
RA75X Assembler Package
User's Manual
Operation
EEU-1346
Language
EEU-1363
PG-1500 Controller User's Manual
EEU-1291
Others
Document Name
Document No.
Package Manual
IEI-1213
Semiconductor Device Mounting Technology Manual
IEI-1207
Quality Grade on NEC Semiconductor Device
IEI-1209
NEC Semiconductor Device Reliability and Quality Control
—
Electrostatic Discharge (ESD) Test
—
Semiconductor Device Quality Guarantee Guide
MEI-1202
Micro Computer-Related Products Guide Other Manufacture
Volume
—
Remark The related documents listed above may change without prior notice. The most up-to-date documents should be used for design work.
75
µPD75312B, 75316B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must
not be touched with bare hands. Similar precautions need to be taken for
PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction.
CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the
device. Immediately after the power source is turned ON, the devices
with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device
is not initialized until the reset signal is received. Reset operation must be
executed immediately after power-on for devices having reset function.
76
µPD75312B, 75316B
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.