DATA SHEET MOS INTEGRATED CIRCUIT µPD784927, 784928, 784927Y, 784928Y 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a highspeed, high-performance 16-bit CPU for VCR software servo control. The µPD784927Y and 784928Y are based on the µPD784928 with the addition of an I2C bus interface compatible with multi-master. They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer unit) for software servo control and VCR analog circuits. Flash memory models, the µPD78F4928 and µPD78F4928Y, are under development. The functions of the µPD784927 is described in detail in the following User’s Manual. Be sure to read this manual before designing your system. µPD784928, 784928Y Subseries User’s Manual - Hardware : U12648E 78K/IV Series User’s Manual - Instruction : U10905E FEATURES • High instruction execution speed realized by 16-bit CPU core • Minimum instruction execution time: 250 ns (with 8 MHz internal clock) • High internal memory capacity µPD784927, 784927Y µPD784928, 784928Y Internal ROM capacity 96K bytes 128K bytes Internal RAM capacity 2048 bytes 3584 bytes Part Number Item • VCR analog circuits conforming to VHS Standard • CTL amplifier • • • • • • • • • • DFG amplifier • Reel FG comparator (2 channels) • RECCTL driver (rewritable) • DPG amplifier • CSYNC comparator • CFG amplifier • DPFG separation circuit (ternary separation circuit) Timer unit (super timer unit) for servo control Serial interface : 3 channels 3-wire serial I/O : 2 channels I2C bus interface: 1 channel A/D converter: 12 channels (conversion time: 10 µs) Low-frequency oscillation mode: main system clock frequency = internal clock frequency Low-power consumption mode: CPU can operate with a subsystem clock. Supply voltage range: VDD = +2.7 to 5.5 V Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption Unless otherwise specified, the µPD784927 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12255EJ2V0DS00 (2nd edition) Date Published December 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1997,1999 µPD784927, 784928, 784927Y, 784928Y APPLICATION FIELDS Stationary VCR, video camera, In-TV VCR ORDERING INFORMATION (1) µPD784928 subseries Part Number Package µPD784927GC-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784927GF-×××-3BA 100-pin plastic QFP (14 × 20 mm) µPD784928GC-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784928GF-×××-3BA 100-pin plastic QFP (14 × 20 mm) (2) µPD784928Y subseries Part Number Package µPD784927YGC-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784927YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm) µPD784928YGC-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784928YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm) Note Under development Remark ××× indicates ROM code suffix. PRODUCT DEVELOPMENT OF VCR-SERVO MICROCONTROLLERS The product development of VCR-servo microcontrollers is shown below. Enclosed in a frame are subseries names. The Y subseries is a collection of products supporting the I2C bus. Products under mass production Products under development 78K/IV series µPD784928 µPD784915 100-pin QFP. Expanded internal memory capacity. Internal analog amplifier. Reinforced super timer. Low-power consumption mode added. µPD78148 100-pin QFP Expanded internal RAM capacity. Operational amplifier, watch function, multiplier added. 78K/I series µPD78138 2 µPD784928Y 100-pin QFP. With flash memory. Expanded internal memory capacity. More powerful analog amplifier. Improved VCR functions. Increased I/O. High-current port added. I2C function added (Y model only). 80-pin QFP Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y FUNCTION LIST (1/2) µPD784927, 784927Y Part Number µPD784928, 784928Y Item Internal ROM capacity 96K bytes 128K bytes Internal RAM capacity 2048 bytes 3584 bytes Operating clock 16 MHz (internal clock: 8 MHz) Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : 32.768 kHz (subsystem clock) Minimum instruction e x e c u tion time 250 ns (with 8 MHz internal clock) I/O port 74 Real-time output port 11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation) Timer/counter Capture register Super timer unit VCR special circuit • • • • General-purpose timer PWM output input : 20 I/O : 54 (including 8 ports for LED direct drive) Timer/counter TM0 (16 bits) TM1 (16 bits) FRC (22 bits) TM3 (16 bits) UDC (5 bits) EC (8 bits) EDV (8 bits) Compare register 3 3 — 2 1 4 1 Input signal CFG DFG HSW VSYNC CTL TREEL SREEL Number of bits 22 22 16 22 16 22 22 Remark For HSW signal generation For CFG signal division Measurable cycle 125 ns to 524 ms 125 ns to 524 ms 1 µs to 65.5 ms 125 ns to 524 ms 1 µs to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms Operating edge ↑ ↓ ↑ ↑ ↓ ↑ ↑ ↓ ↑ ↓ ↑ ↓ VSYNC separation circuit, HSYNC separation circuit VISS detection, wide aspect detection circuits Field identification circuit Head amplifier switch/chrominance rotation output circuit Timer TM2 (16 bits) TM4 (16 bits) TM5 (16 bits) • • Capture register — 1 6 1 — — — Compare register 1 1 (capture/compare) 1 Capture register — 1 — 16-bit resolution : 3 channels (carrier frequency: 62.5 kHz) 8-bit resolution : 3 channels (carrier frequency: 62.5 kHz) Serial interface 3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel) • I2C bus interface: 1 channel (µPD784928Y subseries only) A/D converter 8-bit resolution × 12 channels, conversion time: 10 µs Data Sheet U12255EJ2V0DS00 3 µPD784927, 784928, 784927Y, 784928Y FUNCTION LIST (2/2) µPD784927, 784927Y Part Number µPD784928, 784928Y Item Analog circuit • • • • • • Interrupt sources 4 levels (programmable), vectored interrupt, macro service, context switching CTL amplifier RECCTL driver (rewritable) DFG amplifier, DPG amplifier, CFG amplifier DPFG separation circuit (ternary separation circuit) Reel FG comparator (2 channels) CSYNC comparator External 9 (including NMI) Internal 22 (including software interrupt) Standby function 23 (including software interrupt) HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/ INTP2/KEY0-KEY4 pins Watch function 0.5-second measurement, low-voltage operation (VDD = 2.7 V) Buzzer output function 1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz) 2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz) Supply voltage VDD = +2.7 to 5.5 V Package • 100-pin plastic LQFP (fine pitch)(14 × 14 mm)Note • 100-pin plastic QFP (14 × 20 mm) Note 4 Under development Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y PIN CONFIGURATION (Top View) • 100-pin plastic LQFP (fine pitch)(14 × 14 mm) µPD784927GC-×××-8EUNote 1, 784928GC-×××-8EUNote 1 P85/PWM3/SCLNote 2 P86/PTO10 P87/PTO11 P30/PTO00 P31/PTO01 P32/PTO02 IC RESET X1 X2 VSS XT2 XT1 VDD P33/SI2/BUSY P34/SO2 P35/SCK2 P36/PWM1 P37/PWM0 P63/SI1 P62/SO1 P61/SCK1/BUZ P60/STRB/CLO P67/PWM5/CTLMON P66/PWM4/CFGMON µPD784928YGC-×××-8EU, 784928YGC-×××-8EUNote 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P65/HWIN/DPGMON P64/BUZ/DFGMON P103/CSYNCIN P102/REEL0IN/INTP3 P101/REEL1IN DFGIN P100/DPGIN CFGCPIN CFGAMP0 CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTL− RECCTL+ CTLDLY AVSS2 P113/ANI11 P112/ANI10 P111/ANI9 P110/ANI8 P77/ANI7 P04 P03 P02 P01 P00 P23/INTP2 P22/INTP1 P21/INTP0 P20/NMI P90/ENV P91/KEY0 P92/KEY1 P93/KEY2 P94/KEY3 P95/KEY4 P96 AVDD2 AVREF P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P84/PWM2/SDANote 2 P83/ROTC P82/HASW P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07 P06 P05 Notes 1. Under development 2. Pins SCL and SDA are provided for the µPD784928Y subseries only. Caution Directly connect the IC (Internally Connected) pins to VSS in the normal operation mode. Data Sheet U12255EJ2V0DS00 5 µPD784927, 784928, 784927Y, 784928Y • 100-pin plastic QFP (14 × 20 mm) µPD784927GF-×××-3BA, 784928GF-×××-3BA, CSYNCIN/P103 REEL0IN/INTP3/P102 REEL1IN/P101 DFGIN DPGIN/P100 CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTLRECCTL+ CTLDLY AVSS2 ANI11/P113 ANI10/P112 µPD784927YGF-×××-3BA, 784928YGF-×××-3BA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07 DFGMON/P64/BUZ DPGMON/P65/HWIN CFGMON/P66/PWM4 CTLMON/P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P37/PWM0 P36/PWM1 P35/SCK2 P34/SO2 P33/SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC P32/PTO02 P31/PTO01 P30/PTO00 P87/PTO11 P86/PTO10 Note SCL /P85/PWM3 Note SDA /P84/PWM2 P83/ROTC P82/HASW Note Pins SCL and SDA are provided for the µPD784928Y subseries only. Caution Directly connect the IC (Internally Connected) pins to VSS. 6 Data Sheet U12255EJ2V0DS00 ANI9/P111 ANI8/P110 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI/P20 INTP0/P21 INTP1/P22 INTP2/23 P00 P01 P02 P03 P04 P05 P06 µPD784927, 784928, 784927Y, 784928Y ANI0-ANI11 : Analog Input P20-P23 : Port2 AVDD1, AVDD2 : Analog Power Supply P30-P37 : Port3 AVSS1, AVSS2 : Analog Ground P40-P47 : Port4 AVREF : Analog Reference Voltage P50-P57 : Port5 BUSY : Serial Busy P60-P67 : Port6 BUZ : Buzzer Output P70-P77 : Port7 CFGAMPO : Capstan FG Amplifier Output P80, P82-P87 : Port8 CFGCPIN : Capstan FG Capacitor Input P90-P96 : Port9 CFGIN : Analog Unit Input P100-P103 : Port10 CFGMON : Capstan FG Monitor P110-P113 : Port11 CLO : Clock Output PTO00-PTO02, CSYNCIN : Analog Unit Input PTO10, PTO11 : Programmable Timer Output CTLDLY : Control Delay Input PWM0-PWM5 : Pulse Width Modulation Output CTLIN : CTL Amplifier Input Capacitor RECCTL+, RECCTL– : RECCTL Output/PBCLT Input CTLMON : CTL Amplifier Monitor REEL0IN, REEL1IN : Analog Unit Input CTLOUT1, CTLOUT2 : CTL Amplifier Output RESET : Reset DFGIN : Analog Unit Input ROTC : Chrominance Rotate Output DFGMON : DFG Monitor SCK1, SCK2 : Serial Clock DPGIN : Analog Unit Input SCLNote : Serial Clock DPGMON : DPG Monitor SDANote : Serial Data ENV : Envelope Input SI1, SI2 : Serial Input HASW : Head Amplifier Switch Output SO1, SO2 : Serial Output HWIN : Hardware Timer External Input STRB : Serial Strobe IC : Internally Connected VDD : Power Supply INTP0-INTP3 : Interrupt From Peripherals VREFC : Reference Amplifier Capacitor KEY0-KEY4 : Key Return VSS : Ground NMI : Nonmaskable Interrupt X1, X2 : Crystal (Main System Clock) P00-P07 : Port0 XT1, XT2 : Crystal (Subsystem Clock) Note Pins SCL and SDA are provided for the µPD784928Y subseries only. Data Sheet U12255EJ2V0DS00 7 µPD784927, 784928, 784927Y, 784928Y INTERNAL BLOCK DIAGRAM NMI INTP0-INTP3 INTERRUPT CONTROL SYSTEM CONTROL PWM0-PWM5 PTO00-PTO02 SUPER TIMER UNIT PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTLCTLDLY DFGMON DPGMON CFGMON CTLMON AVDD1, AVDD2 AVSS1, AVSS2 AVREF AN10-AN11 SI1 SO1 SCK1 SI2/BUSY SO2 SCK2 STRB SDA SCL Note CLOCK OUTPUT CLO BUZZER OUTPUT BUZ KEY INPUT KEY0-KEY4 P00-P07 78K/IV 16-BIT CPU CORE (RAM: 512 bytes) ANALOG UNIT & A/D CONVERTER RAM ROM SERIAL INTERFACE 1 SERIAL INTERFACE 2 SERIAL Note INTERFACE 3 REAL-TIME OUTPUT PORT P80, P82, P83 PORT0 P00-P07 PORT2 P20-P23 PORT3 P30-P37 PORT4 P40-P47 PORT5 P50-P57 PORT6 P60-P67 PORT7 P70-P77 PORT8 P80, P82-P87 PORT9 P90-P96 PORT10 P100-P103 PORT11 P110-P113 Only the µPD784928 subseries supports I2C bus interface. Remark Internal ROM and RAM capacities differ depending on the product. 8 VDD VSS X1 X2 XT1 XT2 RESET Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y SYSTEM CONFIGURATION EXAMPLE • Video camera µ PD784927 DFG DPG Drum motor M Driver M Driver Key matrix DPGIN PORT PWM0 CFG Capstan motor PORT DFGIN PORT SCK1 SI1 SO1 INTP0 CFGIN INTP0 SCK Cameracontrolling SO microcontroller SI µ PD784038 PORT PWM1 Camera block RECCTL+ PORT SCK2 SO2 BUSY CTL head RECCTL- Loading motor M Driver CS CLK DATA BUSY LCD C/D µ PD7225 PWM2 LCD display panel PORT Audio/video signal processing circuit Remote controller signal Remote controller reception signal CS CLK DATA BUSY STB PORT Composite sync signal CSYNCIN Video head switch PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 STRB PORT INTP2 µ PC2800A OSD µ PD6461 Mechanical block +VDD +VDD EEPROMTM Note SDA Note SCL SDA SCL Other ICs SDA X1 X2 16 MHz Note XT1 XT2 SCL 32.768 kHz Pins SCL and SDA are provided for the µPD784928Y subseries only. Data Sheet U12255EJ2V0DS00 9 µPD784927, 784928, 784927Y, 784928Y • Stationary VCR µ PD784927 DFG DPG Drum motor M Driver DFGIN PORT SCK1 SI1 SO1 DPGIN PWM0 CFG STB CLK FIPTM C/D DOUT µ PD16311 DIN CFGIN FIP Capstan motor M Driver Key matrix PWM1 PORT SCK2 SO2 CS OSD CLK µ PD6464A DATA RECCTL+ CTL head RECCTL- Loading motor M Driver Reel FG0 M Driver PWM2 PORT Composite sync signal Audio/video signal CSYNCIN Video head switch processing circuit PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 REEL0IN Driver Reel FG1 Tuner PORT Mechanical block PWM3 Reel motor M PWM5 PORT PWM4 INTP2 Remote controller reception signal REEL1IN Remote controller signal µ PC2800A +VDD +VDD EEPROM SDA Note SDA Note SCL SCL Other ICs Low frequency oscillation mode X1 X2 XT1 8 MHz Note 10 SDA XT2 SCL 32.768 kHz Pins SCL and SDA are provided for the µPD784928Y subseries only. Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y CONTENTS 1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES .................... 12 2. PIN FUNCTION ............................................................................................................................... 13 2.1 Port Pins ................................................................................................................................................ 13 2.2 Pins Other Than Port Pins .................................................................................................................. 14 2.3 I/O Circuits of Pins and Processing of Unused Pins ...................................................................... 16 3. INTERNAL BLOCK FUNCTION ..................................................................................................... 19 3.1 CPU Registers ...................................................................................................................................... 19 3.1.1 General-purpose registers ......................................................................................................... 19 3.1.2 Other CPU registers ................................................................................................................... 20 3.2 Memory Space ...................................................................................................................................... 21 3.3 Special Function Registers (SFRs) ................................................................................................... 24 3.4 Ports ....................................................................................................................................................... 30 3.5 Real-Time Output Port ......................................................................................................................... 31 3.6 Super Timer Unit .................................................................................................................................. 35 3.7 Serial Interface ..................................................................................................................................... 41 3.8 A/D Converter ....................................................................................................................................... 44 3.9 VCR Analog Circuits ............................................................................................................................ 45 3.10 Watch Function .................................................................................................................................... 50 3.11 Clock Output Function ........................................................................................................................ 51 3.12 Buzzer Output Function ...................................................................................................................... 52 4. INTERNAL/EXTERNAL CONTROL FUNCTION ........................................................................... 53 4.1 Interrupt Function ................................................................................................................................ 53 4.1.1 Vectored interrupt ....................................................................................................................... 56 4.1.2 Context switching ....................................................................................................................... 56 4.1.3 Macro service ............................................................................................................................. 57 4.1.4 Application example of macro service ...................................................................................... 59 4.2 Standby Function ................................................................................................................................. 62 4.3 Clock Generation Circuit ..................................................................................................................... 64 4.4 Reset Function ..................................................................................................................................... 65 5. INSTRUCTION SET ........................................................................................................................ 66 6. ELECTRICAL SPECIFICATIONS .................................................................................................. 70 7. PACKAGE DRAWING .................................................................................................................... 85 8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 87 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 88 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 91 Data Sheet U12255EJ2V0DS00 11 µPD784927, 784928, 784927Y, 784928Y 1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES The µPD78F4928 and 78F4928Y are based on the µPD784927 and 784927Y and are provided with a 128K-byte flash memory instead of a mask ROM. Table 1-1 shows the differences between the products in the µPD784928 subseries and 784928Y subseries. Table 1-1. Differences between µPD784928 Subseries and 784928Y Subseries Part Number Item Internal ROM 12 µPD784927, µPD784927Y µPD784928, µPD784928Y Mask ROM µPD78F4928, µPD78F4928Y Flash memory 96K bytes 128K bytes Internal RAM 2048 bytes 3584 bytes Internal memory capacity select register (IMS) Not provided Provided IC pin Provided Not provided VPP pin Not provided Provided Electrical characteristics Refer to the Data Sheet of each product. Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 2. PIN FUNCTION 2.1 Port Pins Pin Name P00-P07 I/O Function Real-time output port 8-bit I/O port (port 0). • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. NMI 4-bit I/O port (port 2). INTP0-INTP2 • Can be connected with software pull-up resistors (P22 and P23 only). PTO00-PTO02 8-bit I/O port (port 3). P33 SI2/BUSY • Can be set in input or output mode in 1-bit units. P34 SO2 • Can be connected with software pull-up resistors. P35 SCK2 P36, P37 PWM1, PWM0 P20 I/O Shared with: Input P21-P23 P30-P32 I/O P40-P47 I/O — 8-bit I/O port (port 4). • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. • Can directly drive LED. P50-P57 I/O — 8-bit I/O port (port 5). • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. P60 I/O STRB/CLO 8-bit I/O port (port 6). P61 SCK1/BUZ • Can be set in input or output mode in 1-bit units. P62 SO1 • Can be connected with software pull-up resistors. P63 SI1 P64 DFGMON/BUZ P65 DPGMON/HWIN P66 CFGMON/PWM4 P67 CTLMON/PWM5 P70-P77 P80 Input ANI0-ANI7 8-bit input port (port 7) I/O Real-time Pseudo VSYNC output 7-bit I/O port (port 8). output port HASW output • Can be set in input or output mode P82 P83 ROTC output P84 PWM2/SDANote P85 PWM3/SCLNote P86 PTO10 P87 PTO11 P90 I/O P91-P95 ENV — P100 Input DPGIN REEL1IN P102 REEL0IN/INTP3 P103 CSYNCIN Note Input • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. 4-bit input port (port 10). P101 P110-P113 pull-up resistors. 7-bit I/O port (port 9). KEY0-KEY4 P96 in 1-bit units. • Can be connected with software ANI8-ANI11 4-bit input port (port 11). Pins SCL and SDA are provided for the µPD784928Y subseries only. Data Sheet U12255EJ2V0DS00 13 µPD784927, 784928, 784927Y, 784928Y 2.2 Pins Other Than Port Pins (1/2) Pin Name REEL0IN I/O Input REEL1IN Shared with: P102/INTP3 Reel FG input P101 DFGIN — DPGIN P100 CFGIN P103 CFGCPIN CFGAMPO Output PTO00 Output P31 PTO02 P32 PTO10 P86 PTO11 P87 Output Capstan FG input Composite SYNC input — CFG comparator input — CFG amplifier output P30 PTO01 Drum FG, PFG input (ternary) Drum PG input — CSYNCIN PWM0 Function Programmable timer output of super timer unit P37 PWM output of super timer unit PWM1 P36 PWM2 P84/SDANote PWM3 P85/SCLNote PWM4 P66/CFGMON PWM5 P67/CTLMON HASW Output P82 Head amplifier switch signal output ROTC Output P83 Chrominance rotation signal output ENV Input P90 Envelope signal input SI1 Input P63 Serial data input (serial interface channel 1) SO1 Output P62 Serial data output (serial interface channel 1) P61/BUZ Serial clock I/O (serial interface channel 1) P33/BUSY Serial data input (serial interface channel 2) SCK1 I/O SI2 Input SO2 Output P34 Serial data output (serial interface channel 2) SCK2 I/O P35 Serial clock I/O (serial interface channel 2) BUSY Input P33/SI2 Serial busy signal input (serial interface channel 2) STRB Output P60/CLO Serial strobe signal output (serial interface channel 2) SDA I/O P84/PWM2 I2C bus data I/O SCL I/O P85/PWM3 I2C bus clock I/O P70-P77 Analog signal input of A/D converter ANI0-ANI7 Analog input ANI8-ANI11 CTLIN P110-P113 — — CTL amplifier input capacitor connection CTLOUT1 Output — CTL amplifier output CTLOUT2 I/O — Logic signal input/CTL amplifier output RECCTL+, RECCTL– I/O — RECCTL signal output/PBCTL signal input CTLDLY — — External time constant connection (for RECCTL rewriting) Note 14 Pins SCL and SDA are provided for the µPD784928Y subseries only. Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 2.2 Pins Other Than Port Pins (2/2) Pin Name VREFC DFGMON I/O Shared with: — — Output Function VREF amplifier AC connection P64/BUZ Drum FG signal output DPGMON P65/HWIN Drum PG signal output CFGMON P66/PWM4 CFG signal output CTLMON P67/PWM5 CTL signal output NMI Input P20 Non-maskable interrupt request input INTP0-INTP2 Input P21-P23 External interrupt request input INTP3 Input P102/REEL0IN KEY0-KEY4 Input P91-P95 Key input signal input CLO Output P60/STRB Clock output BUZ Output P61/SCK1 Buzzer output P64/DFGMON HWIN Input P65/DPGMON External input of hardware watch counter RESET Input — Reset input X1 Input — Crystal connection for main system clock oscillation X2 — — Crystal connection for subsystem clock oscillation. XT1 Input XT2 — AVDD1 — — Positive power supply to analog amplifier circuit AVDD2 — — Positive power supply to A/D converter and analog circuits input buffer AVSS1 — — GND of analog amplifier circuit AVSS2 — — GND of A/D converter and analog circuits input buffer AVREF — — Reference voltage input to A/D converter VDD — — Positive power supply to digital circuits VSS — — GND of digital circuits IC — — Internally connected. Directly connect this pin to VSS. Crystal connection for watch clock oscillation Data Sheet U12255EJ2V0DS00 15 µPD784927, 784928, 784927Y, 784928Y 2.3 I/O Circuits of Pins and Processing of Unused Pins Table 2-1 shows the types of the I/O circuits of the respective pins and processing of the unused pins. Figure 2-1 shows the circuits of the respective types. Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (1/2) Pin P00-P07 I/O Circuit Type I/O 5-A I/O Recommended Connection of Unused Pins Input: Connect to VDD. Output: Leave unconnected. P20/NMI 2 Input P21/INTP0 Connect to VDD. Connect to VDD or VSS. P22/INTP1, P23/INTP2 2-A P30/PTO00-P32/PTO02 5-A P33/SI2/BUSY 8-A P34/SO2 5-A P35/SCK2 8-A P36/PWM1, P37/PWM0 5-A Connect to VDD. I/O Input: Connect to VDD. Output: Leave unconnected. P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ 8-A P62/SO1 5-A P63/SI1 8-A P64/DFGMON/BUZ 5-A P65/HWIN/DPGMON 8-A P66/PWM4/CFGMON 5-A P67/PWM5/CTLMON P70/ANI0-P77/ANI7 P80 9 Input 5-A I/O P82/HASW Connect to VSS. Input: Connect to VDD. Output: Leave unconnected. P83/ROTC P84/PWM2/SDANote 10-A P85/PWM3/SCLNote P86/PTO10 5-A P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 8-A P96 5-A Note 16 Pins SCL and SDA are provided for the µPD784928Y subseries only. Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (2/2) Pin P100/DPGIN I/O Circuit Type I/O — Input Recommended Connection of Unused Pins When ENDRUM = 0 or ENDRUM = 1 and SELPGSEPA = 0: Connect to VSS. P101/REEL1IN When ENREEL = 0: Connect to VSS. P102/REEL0IN/INTP3 P103/CSYNCIN P110/ANI8-P113/ANI11 When ENCSYN = 0: Connect to VSS. 9 Input RECCTL+, RECCTL– — I/O DFGIN — Input CFGIN, CFGCPIN Connect to VSS. When ENCTL = 0 and ENREC = 0: Connect to VSS. When ENDRUM = 0: Connect to VSS. When ENCAP = 0: Connect to VSS. CTLOUT1 — Output CTLOUT2 — I/O Leave unconnected. When ENCTL = 0 and ENCOMP = 0: Connect to VSS. When ENCTL = 1: Leave unconnected. CFGAMPO — Output CTLIN — — VREFC Leave unconnected. When ENCTL = 0: Leave unconnected. When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Leave unconnected. CTLDLY Leave unconnected. AVDD1, AVDD2 — — AVREF, AVSS1, AVSS2 Connect to VDD. Connect to VSS. RESET 2 — XT1 — — — Connect to VSS. XT2 Leave unconnected. IC Directly connect to VSS. Remark ENCTL : bit 1 of amplifier control register (AMPC) ENREC : bit 7 of amplifier mode register 0 (AMPM0) ENDRUM : bit 2 of amplifier control register (AMPC) SELPGSEPA : bit 2 of amplifier mode register 0 (AMPM0) ENCAP : bit 3 of amplifier control register (AMPC) ENCSYN : bit 5 of amplifier control register (AMPC) ENREEL : bit 6 of amplifier control register (AMPC) ENCOMP : bit 4 of amplifier control register (AMPC) Data Sheet U12255EJ2V0DS00 17 µPD784927, 784928, 784927Y, 784928Y Figure 2-1. I/O Circuits of Respective Pins Type 2 Type 8-A VDD IN Pull-up enable P-ch VDD Schmitt trigger input with hysteresis characteristics Data P-ch IN/ OUT Type 2-A Output disable VDD N-ch Pull-up enable P-ch Type 9 IN Schmitt trigger input with hysteresis characteristics IN P-ch N-ch + Comparator - Type 5-A VREF (Threshold voltage) VDD Input enable Pull-up enable P-ch VDD Data Type 10-A P-ch VDD IN/ OUT Output disable Input enable N-ch Pull-up Enable P-ch VDD Data P-ch IN/OUT Open drain Output disable 18 Data Sheet U12255EJ2V0DS00 N-ch µPD784927, 784928, 784927Y, 784928Y 3. INTERNAL BLOCK FUNCTION 3.1 CPU Registers 3.1.1 General-purpose registers The µPD784927 has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-purpose registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit general-purpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register. These eight banks of general-purpose registers can be selected by software or context switching function. The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the internal RAM. Figure 3-1. Configuration of General-Purpose Register A (R1) X (R0) B (R3) AX (RP0) C (R2) BC (RP1) R5 R4 RP2 R7 R6 RP3 V R9 R8 VP (RP4) VVP (RG4) U R11 R10 UP (RP5) UUP (RG5) T D (R13) E (R12) DE (RP6) TDE (RG6) W H (R15) L (R14) HL (RP7) WHL (RG7) ( ): absolute name 8 banks Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series. Data Sheet U12255EJ2V0DS00 19 µPD784927, 784928, 784927Y, 784928Y 3.1.2 Other CPU registers (1) Program counter The program counter of the µPD784927 is 20 bits wide. The value of the program counter is automatically updated as the program is executed. 19 0 PC (2) Program status word This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed. PSWH PSW PSWL Note 15 14 13 12 11 UF RBS2 RBS1 RBS0 7 S 6 Z 5 Note RSS 4 AC 3 IE 10 9 8 2 P/V 1 0 0 CY The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series. Always clear this flag to 0 except when the software of the 78K/III Series is used. (3) Stack pointer This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits. SP 20 23 0 0 0 20 0 Data Sheet U12255EJ2V0DS00 0 µPD784927, 784928, 784927Y, 784928Y 3.2 Memory Space A memory space of 1M bytes can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed after reset has been cleared, and cannot be used more than once. (1) When LOCATION 0H instruction is executed Part Number Internal Data Area Internal ROM Area µPD784927, 784927Y 0F700H-0FFFFH 00000H-0F6FFH 10000H-17FFFH µPD784928, 784928Y 0F100H-0FFFFH 00000H-0F0FFH 10000H-1FFFFH Remark The area of the internal ROM overlapping the internal data area cannot be used when the LOCATION 0 instruction is executed. Part Number Unusable Area µPD784927, 784927Y 0F700H-0FFFFH (2304 bytes) µPD784928, 784928Y 0F100H-0FFFFH (3840 bytes) (2) When LOCATION 0FH instruction is executed Part Number Internal Data Area Internal ROM Area µPD784927, 784927Y FF700H-FFFFFH 00000H-17FFFH µPD784928, 784928Y FF100H-FFFFFH 00000H-1FFFFH Data Sheet U12255EJ2V0DS00 21 22 Figure 3-2. Memory Map of µPD784927, 784927Y When LOCATION 0H instruction is executed When LOCATION 0FH instruction is executed FFFFFH 0FEFFH Cannot be used 18000H 17FFFH FFEFFH FFFFFH Special function registers (SFRs) FFFDFH Note 1 FFFD0H (256 bytes) FFF00H FFEFFH Internal RAM (2048 bytes) General-purpose registers (128 bytes) 0FE80H 0FE7FH FFE80H FFE7FH 0FE3BH FFE3BH FF700H FF6FFH Internal ROM (32768 bytes) 10000H 0FFFFH Special function registers (SFRs) 0FFDFH 0FFD0H Note 1 (256 bytes) 0FF00H 0FEFFH FFE06H Data area (512 bytes) 0FD00H 0FCFFH FFD00H FFCFFH Program/data area (1536 bytes) 0F700H 0F6FFH 0F700H FF700H 17FFFH 10000H 17FFFH Cannot be used Note 2 0F6FFH Program/data areaNote 3 Note 4 Internal ROM (63232 bytes) 01000H 00FFFH CALLF entry area (2K bytes) 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H 00000H 18000H 17FFFH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (96K bytes) Note 4 00000H Notes 1. Accessed in external memory expansion mode 2. The 2304 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. When LOCATION 0H instruction is executed: 96000 bytes, when LOCATION 0FH instruction is executed: 98304 bytes 4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset. µPD784927, 784928, 784927Y, 784928Y Data Sheet U12255EJ2V0DS00 Internal RAM (2048 bytes) Macro service control 0FE06H word area (54 bytes) Figure 3-3. Memory Map of µPD784928, 784928Y When LOCATION 0H instruction is executed When LOCATION 0FH instruction is executed FFFFFH 0FEFFH Cannot be used 20000H 1FFFFH FFEFFH FFFFFH Special function registers (SFRs) FFFDFH Note 1 FFFD0H (256 bytes) FFF00H FFEFFH Internal RAM (3584 bytes) General-purpose registers (128 bytes) 0FE80H 0FE7FH FFE80H FFE7FH 0FE3BH FFE3BH FF100H FF0FFH Internal ROM (65536 bytes) 10000H 0FFFFH Special function registers (SFRs) 0FFDFH 0FFD0H Note 1 (256 bytes) 0FF00H 0FEFFH FFE06H Data area (512 bytes) 0FD00H 0FCFFH FFD00H FFCFFH Program/data area (3072 bytes) 0F100H 0F0FFH 0F100H FF100H 1FFFFH 10000H 1FFFFH Cannot be used Note 2 0F0FFH Program/data areaNote 3 Note 4 Internal ROM (61696 bytes) 01000H 00FFFH CALLF entry area (2K bytes) 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H 00000H 20000H 1FFFFH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (128K bytes) Note 4 00000H Notes 1. Accessed in external memory expansion mode 2. The 3840 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. When LOCATION 0H instruction is executed: 127232 bytes, when LOCATION 0FH instruction is executed: 131072 bytes 23 4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset. µPD784927, 784928, 784927Y, 784928Y Data Sheet U12255EJ2V0DS00 Internal RAM (3584 bytes) Macro service control 0FE06H word area (54 bytes) µPD784927, 784928, 784927Y, 784928Y 3.3 Special Function Registers (SFRs) Special function registers are assigned special functions and mapped to a 256-byte space of addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units. Caution Do not access an address to which no SFR is assigned. If such an address is accessed by mistake, the µPD784927 may be deadlocked. This deadlock can be cleared only by reset input. Table 3-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: • Symbol .................................... Abbreviation of an SFR. This abbreviation is reserved for NEC’s assembler (RA78K4). With a C compiler (CC78K4), the abbreviation can be used as sfr variable by the #pragma sfr instruction. • R/W ......................................... Indicates whether the SFR in question can be read or written. R/W : Read/write R : Read only W : Write only • Bit length ................................. Indicates the bit length (word length) of the SFR. • Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that can be manipulated in 16-bit units can be used as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be used for a bit manipulation instruction. • After clearing reset ................. Indicates the status of each register immediately after clearing reset. Caution The addresses shown in Table 3-1 are used when the LOCATION 0H instruction is executed. Add “F0000H” to the address values shown in the table when the LOCATION 0FH instruction is executed. 24 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Table 3-1. Special Function Registers (1/5) Address Special Function Register (SFR) Name Symbol R/W Bit Length FF00H Port 0 P0 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Bit Units for Manipulation After Clearing 1 bit 8 bits 16 bits R/W 8 — P2 R 8 — P3 R/W 8 — P4 8 — Port 5 P5 8 — FF06H Port 6 P6 8 — FF07H Port 7 P7 R 8 — FF08H Port 8 P8 R/W 8 — FF09H Port 9 P9 8 — FF0AH Port 10 P10 8 — FF0BH Port 11 P11 8 — FF0EH Port 0 buffer register L P0L 8 — FF0FH Port 0 buffer register H P0H 8 — FF10H Timer 0 compare register 0 CR00 16 — FF11H Event counter compare register 0 ECC0 W 8 — FF12H Timer 0 compare register 1 CR01 R/W 16 — FF13H Event counter compare register 1 ECC1 W 8 — FF14H Timer 0 compare register 2 CR02 R/W 16 — FF15H Event counter compare register 2 ECC2 W 8 — FF16H Timer 1 compare register 0 CR10 R/W 16 — FF17H Event counter compare register 3 ECC3 W 8 — R R/W — Reset Undefined Cleared to 0 — — — — — — — FF18H Timer 1 compare register 1 CR11 R/W 16 — — FF1AH Timer 1 compare register 2 CR12 R 16 — — FF1CH Timer 1 compare register 3 CR13 R/W 16 — — FF1EH Timer 2 compare register 0 CR20 16 — — FF20H Port 0 mode register PM0 8 — FF23H Port 3 mode register PM3 8 — FF24H Port 4 mode register PM4 8 — FF25H Port 5 mode register PM5 8 — FF26H Port 6 mode register PM6 8 — FF28H Port 8 mode register PM8 8 — FDH FF29H Port 9 mode register PM9 8 — 7FH FF2EH Real-time output port 0 control register RTPC 8 — 00H FF30H Timer counter 0 FF31H Event counter FF32H TM0 R 16 — EC R/W 8 — — Timer counter 1 TM1 R 16 — — FF34H Free running counter (bits 0-15) FRCL 16 — — FF35H Free running counter (bits 16-21) FRCH 8 — FF36H Timer counter 2 TM2 16 — FFH Cleared to 0 — 0000H — — 00H Cleared to 0 Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined). Data Sheet U12255EJ2V0DS00 25 µPD784927, 784928, 784927Y, 784928Y Table 3-1. Special Function Registers (2/5) Address Special Function Register (SFR) Name Symbol R/W Bit Length FF38H Timer control register 0 TMC0 R/W Bit Units for Manipulation After Clearing 1 bit 8 bits 16 bits 8 — FF39H Timer control register 1 TMC1 8 — FF3AH Timer control register 2 TMC2 8 — FF3BH Timer control register 3 TMC3 8 — FF3CH Timer counter 3 TM3 R 16 — — TMC4 R/W 8 TM4 R 16 — — R/W 8 — Reset 00H 00×00000 Cleared to 0 FF3DH Timer control register 4 FF3EH Timer counter 4 — FF43H Port 3 mode control register PMC3 FF48H Port 8 mode control register PMC8 8 — ××000000 Cleared to 0 00H FF4BH Control mode select register CMS 8 — FF4DH Trigger source select register 0 TRGS0 8 — FF4EH Pull-up resistor option register L PUOL 8 — FF4FH Pull-up resistor option register H PUOH 8 — FF50H Input control register ICR 8 — 10H FF51H Up/down counter count register UDC 8 — — Undefined FF52H Event divider counter EDV R 8 — — Cleared to 0 FF53H Capture mode register CPTM R/W 8 — 00H FF54H Timer counter 5 TM5 R FF56H Timer 3 capture register 0 CPT30 FF58H Timer 0 output mode register TOM0 FF59H Timer 0 output control register TOC0 FF5AH Timer 1 output mode register TOM1Note 1 FF5BH Timer 1 output control register TOC1 FF5CH Timer 3 compare register 0 CR30 FF5EH Timer 3 compare register 1 CR31 FF60H Port 8 buffer register L FF63H Up/down counter compare register UDCC W 8 FF65H Trigger source select register 1 TRGS1 R/W FF66H Port 6 mode control register FF68H A/D converter mode register FF6AH A/D conversion result register FF6CH 16 — — 16 — — 8 — — ××000000 8 — — 00H R/W 8 — — 80H W 8 — — 00H R/W 16 — — 16 — — W P8L 8 Cleared to 0 Cleared to 0 — 000×0×0× — Undefined 8 — 00H PMC6 8 — ADM 16 ADMLNote 2 8 — — — 0000H — ADCR R 8 — Hardware watch counter 0 HW0 R/W 16 — — FF6EH Hardware watch counter 1 HW1 R 16 — — FF6FH Watch mode register WM R/W 8 — 00××0×00 FF70H PWM control register 0 8 — 05H PWMC0 — Undefined Not affected by reset Notes 1. When the TOM1 is read, the write sequence of the REC driver is read (bits 0 and 1). 2. ADML is the low-order 8 bits of ADM and can be manipulated in 1- or 8-bit units. Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined). 26 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Table 3-1. Special Function Registers (3/5) Address Special Function Register (SFR) Name Symbol R/W Bit Length 1 bit 8 bits 16 bits PWM control register 1 PWMC1 FF72H PWM0 modulo register PWM0 16 — FF73H PWM2 modulo register PWM2 8 — FF74H PWM1 modulo register PWM1 16 — FF75H PWM3 modulo register PWM3 8 — FF76H PWM5 modulo register PWM5 16 — FF77H PWM4 modulo register PWM4 8 — — 00H FF78H Event divider control register EDVC W 8 — — Cleared to 0 FF79H Clock output mode register CLOM R/W 8 — 00H FF7AH Timer 4 capture/compare register 0 CR40 16 FF7BH Clock control register CC 8 FF7CH Timer 4 capture register 1 CR41 R 16 — FF7DH Capture/compare control register CRC W 8 — FF7EH Timer 5 compare register CR50 R/W 16 — FF80H I2C control register IICC 8 — FF82H I2C IICCL 8 — FF84H Serial mode register 1 CSIM1 8 — FF85H Serial shift register 1 SIO1 8 — Undefined FF86H Slave address register SVA 8 — 00H FF88H Serial mode register 2 CSIM2 8 — FF89H Serial shift register 2 SIO2 8 — — Undefined 8 — — 00H CSIC2 8 — Reset FF71H clock select register R/W Bit Units for Manipulation After Clearing — — 0000H — — 00H 0000H — — 00H 0000H — Cleared to 0 — — 00H Cleared to 0 — — — 15H 00H Cleared to 0 00H FF8AH Serial control register 2 FF8CH I2C bus status registerNote FF8EH I2C bus shift registerNote FF90H Amplifier mode register 2 FF91H Head amplifier switch output control register FF94H Amplifier control register FF95H Amplifier mode register 0 FF96H Amplifier mode register 1 FF97H Gain control register CTLM 8 FF98H VISS detection circuit shift register 0 VSFT0 16 — — VISS detection circuit shift register 1 VSFT1 16 — — FFA0H External interrupt mode register INTM0 8 — 000000×0 FFA1H External capture mode register 1 INTM1 8 — 00H FFA2H External capture mode register 2 INTM2 8 — FFA3H VISS detection circuit control register VDC 8 — IICS R 8 — IIC R/W 8 — 8 — HAPC 8 — AMPC 8 — AMPM0 8 — AMPM1 8 — AMPM2 — 0000H FF99H FF9AH FF9BH Note These registers are provided for the µPD784928Y subseries only. Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined). Data Sheet U12255EJ2V0DS00 27 µPD784927, 784928, 784927Y, 784928Y Table 3-1. Special Function Registers (4/5) Address Special Function Register (SFR) Name Symbol R/W 1 bit 8 — — — — VISS detection circuit up/down counter register VUDC FFA5H VUDC value setting register VUDST 8 FFA6H Key interrupt control register KEYC 8 FFA7H VISS pulse pattern setting register VPS 8 FFA8H In-service priority register ISPR R IMC R/W FFAAH Interrupt mode control register Interrupt mask flag register MK0L FFADH MK0H FFAEH MK1L FFAFH Bit Units for Manipulation After Clearing Length FFA4H FFACH R/W Bit 8 bits 16 bits — 00H — 70H — 00H 8 — 8 — 8 MK0 Reset 80H FFH 8 8 MK1 MK1H FFB0H FRC capture register 0L CPT0L FFB1H FRC capture register 0H FFB2H 8 R 16 — CPT0H 8 — FRC capture register 1L CPT1L 16 — FFB3H FRC capture register 1H CPT1H 8 — FFB4H FRC capture register 2L CPT2L 16 — FFB5H FRC capture register 2H CPT2H 8 — FFB6H FRC capture register 3L CPT3L 16 — FFB7H FRC capture register 3H CPT3H 8 — FFB8H FRC capture register 4L CPT4L 16 — FFB9H FRC capture register 4H CPT4H 8 — FFBAH FRC capture register 5L CPT5L 16 — CPT5H 8 — — Cleared to 0 — — — — — — — — — — FFBBH FRC capture register 5H FFBDH VSYNC separation circuit control register FFBEH VSYNC separation circuit up/down counter register VSUDC 8 — — FFBFH VSYNC separation circuit compare register VSCMP 8 — — FFH FFC0H Standby control register 8 — — 0011×000 FFC4H Execution speed select register MM W 8 — — 20H FFCEH CPU clock status register PCS R 8 — 00H FFCFH Oscillation stabilization time specification register OSTS W 8 FFE0H Interrupt control register (INTP0) PIC0 R/W 8 — FFE1H Interrupt control register (INTCPT3) CPTIC3 8 — FFE2H Interrupt control register (INTCPT2) CPTIC2 8 — FFE3H Interrupt control register (INTCR12) CRIC12 8 — FFE4H Interrupt control register (INTCR00) CRIC00 8 — FFE5H Interrupt control register (INTCLR1) CLRIC1 8 — FFE6H Interrupt control register (INTCR10) CRIC10 8 — VSC R/W STBC 8 — — — 00H — 43H Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined). 28 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Table 3-1. Special Function Registers (5/5) Address Special Function Register (SFR) Name Symbol R/W Bit Length FFE7H Interrupt control register (INTCR01) CRIC01 FFE8H Interrupt control register (INTCR02) FFE9H Interrupt control register (INTCR11) FFEAH FFEBH 1 bit 8 bits 16 bits 8 — CRIC02 8 — CRIC11 8 — Interrupt control register (INTCPT1) CPTIC1 8 — Interrupt control register (INTCR20) CRIC20 8 — (INTIIC)Note 1 R/W Bit Units for Manipulation After Clearing FFECH Interrupt control register IICIC 8 — FFEDH Interrupt control register (INTTB) TBIC 8 — FFEEH Interrupt control register (INTAD) ADIC 8 — PIC2 8 — FFEFH Interrupt control register (INTP2)Note 2 Interrupt control register (INTCR40)Note 2 Reset 43H CRIC40 FFF0H Interrupt control register (INTUDC) UDCIC 8 — FFF1H Interrupt control register (INTCR30) CRIC30 8 — FFF2H Interrupt control register (INTCR50) CRIC50 8 — FFF3H Interrupt control register (INTCR13) CRIC13 8 — FFF4H Interrupt control register (INTCSI1) CSIIC1 8 — FFF5H Interrupt control register (INTW) WIC 8 — ×1000011 FFF6H Interrupt control register (INTVISS) VISIC 8 — 43H FFF7H Interrupt control register (INTP1) PIC1 8 — FFF8H Interrupt control register (INTP3) PIC3 8 — FFFAH Interrupt control register (INTCSI2) CSIIC2 8 — Notes 1. µPD784928Y subseries only. 2. PIC2 and CRIC40 are at the same address (register). Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined). Data Sheet U12255EJ2V0DS00 29 µPD784927, 784928, 784927Y, 784928Y 3.4 Ports The µPD784927 is provided with the ports shown in Figure 3-3. Table 3-2 shows the function of each port. Figure 3-4. Port Configuration P00 P60 Port 0 Port 6 P07 P67 P20 P70-P77 Port 2 P23 8 Port 7 P80 P82 P30 Port 8 Port 3 P87 P37 P90 P40 Port 9 Port 4 P96 P47 P100 Port 10 P50 P103 Port 5 P110 P57 Port 11 P113 Table 3-2. Port Function Name Port 0 30 Pin Name P00-P07 Function Specification of Pull-up Resistor Can be set in input or output mode in Pull-up resistors are connected to all 1-bit units. pins in input mode. Port 2 P20-P23 Input port Pull-up resistors are connected to pins P22 and P23. Port 3 P30-P37 Can be set in input or output mode in 1-bit units. Pull-up resistors are connected to all pins in input mode. Port 4 P40-P47 Can be set in input or output mode in 1-bit units. Can directly drive LED. Port 5 P50-P57 Can be set in input or output mode in Port 6 P60-P67 1-bit units. Port 7 P70-P77 Input port Pull-up resistor is not provided. Port 8 P80, P82-P87 Can be set in input or output mode in Pull-up resistors are connected to all pins Port 9 P90-P96 1-bit units. in input mode. Port 10 P100-P103 Input port Pull-up resistor is not provided. Port 11 P110-P113 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 3.5 Real-Time Output Port A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5). The function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such as a timer interrupt occurs, and output the data to an external device is called a real-time output function. A port used in this way is called a real-time output port (RTP). Table 3-3 shows the real-time output ports of the µPD784927. Table 3-4 shows the trigger sources of RTPs. Figure 3-5. Configuration of RTP Buffer register Output trigger Port output latch Port Table 3-3. Bit Configuration of RTP RTP RTP0 Shared with: Port 0 Number of Bits of Number of Bits That Can Real-Time Output Data Be Specified as RTP 4 bits × 2 channels or Remark 4-bit units — 8 bits × 1 channel RTP8 Port 8 1 bit × 1 channel and 1-bit units 2 bits × 1 channel Pseudo VSYNC output: 1 channel (RTP80) Head amplifier switch: 1 channel (RTP82) Chrominance rotation signal output: 1 channel (RTP83) Table 3-4. Trigger Sources of RTP Trigger Source INTCR00 INTCR01 INTCR02 INTCR13 INTCR50 INTP0 Remark RTP RTP0 High-order 4 bits Low-order 4 bits All 8 bits RTP8 Bit 0 Note 1 Bits 2 and 3 Note 2 Notes 1. Select one of the four trigger sources. 2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence signal). However, the set signal is output immediately when the HAPC register is rewritten. Data Sheet U12255EJ2V0DS00 31 µPD784927, 784928, 784927Y, 784928Y Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger sources. Figure 3-6. Block Diagram of RTP0 Internal bus 8 4 Buffer register P0H P0L Real-time output port 0 control register (RTPC) INTP0 INTCR01 INTCR02 4 4 Output trigger 8 4 Control circuit Output latch (P0) P07 P00 Remark INTCR01: TM0-CR01 coincidence signal INTCR02: TM0-CR02 coincidence signal Figure 3-7. Block Diagram of RTP8 Internal bus 8 8 Head amplifier output control register (HAPC) SEL SEL SEL PB PB PB 0 0 ROTC HASW ENV MOD2 MOD1 MOD0 Port 8 buffer register L (P8L) SEL 0 0 0 P8L4 P8L2 0 P8L0 MD80 TRGP80 HASW, ROT-C TM0-CR00 control circuit coincidence signal Pseudo VSYNC output control circuit PMC80 0 PMC82 PMC83 PMC8 Output latch (P8) HSYNC superimposition circuit P83 P82 32 P80 Data Sheet U12255EJ2V0DS00 8 µPD784927, 784928, 784927Y, 784928Y Figure 3-8. Types of RTP Output Trigger Sources Real-time output port 0 control register (RTPC) INTP0 TM0 Selector Trigger of P0H Trigger of P0L CR00 CR01 Interrupt and timer output Trigger of P82 and P83 CR02 Selector Trigger of P80 TM1 CR10 Interrupt and timer output Trigger source select register 0 (TRGS0) CR11 Capture CR12 Interrupt CR13 TM5 CR50 Interrupt Data Sheet U12255EJ2V0DS00 33 µPD784927, 784928, 784927Y, 784928Y RTP80 can output low-level, high-level, and high-impedance values real-time. Because RTP80 can superimpose a horizontal sync signal, it can be used to create pseudo vertical sync signal. When RTP80 is set in the pseudo VSYNC output mode, it repeatedly outputs a specific pattern when an output trigger occurs. Figure 3-9 shows the operation timing of RTP80. Figure 3-9. Example of Operation Timing of RTP80 (a) When HSYNC signal is superimposed High level P80 High impedance Low level Trigger signal (b) Pseudo VSYNC output mode High level P80 High impedance Low level Trigger signal 34 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 3.6 Super Timer Unit The µPD784927 is provided with a super timer unit that consists of the timers, and VCR special circuits such as a VISS detection circuit and a VSYNC separation circuit, etc., shown in Table 3-5. Table 3-5. Configuration of Super Timer Unit Unit Name Timer/Counter Resolution Maximum Register Remark Count Time Timer 0 1 µs TM0 65.5 ms (16-bit timer) EC — — (8-bit counter) Free FRC running (22-bit counter) CR00 Controls delay of video head switching signal CR01 Controls delay of audio head switching signal CR02 Controls pseudo VSYNC output timing ECC0, ECC1, Creates internal head switching signal ECC2, ECC3 125 ns 524 ms CPT0 Detects reference phase (to control drum phase) CPT1 Detects phase of drum motor (to control drum CPT2 Detects speed of drum motor (to control drum counter phase) speed) CPT3 Detects speed of capstan motor (to control speed of capstan motor) Timer 1 1 µs TM1 65.5 ms CPT4, CPT5 Detects remaining tape for reel FG CR10 Playback: Creates internal reference signal (16-bit timer) Recording: Buffer oscillator in case VSYNC is missing CR11 Controls RECCTL output timing CR12 Detects phase of capstan motor (to control capstan CR13 Controls VSYNC mask as noise preventive measures CR30, CR31 Controls duty detection timing of PBCTL signal phase) TM3 1 µs or 65.5 ms or (16-bit timer) 1.1 µs 71.5 ms CPT30 Measures cycle of PBCTL signal — — EDVC Divides CFG signal frequency 1 µs 65.5 ms CR20 Can be used as interval timer (to control system) 2 µs 131 ms CR40 Detects duty of remote controller signal (to decode EDV (8-bit counter) Timer 2 TM2 (16-bit timer) Timer 4 TM4 (16-bit timer) remote controller signal) CR41 Measures cycle of remote controller signal (to de code remote controller signal) Timer 5 TM5 Up/down UDC counter (5-bit counter) 2 µs 131 ms CR50 Can be used as interval timer (to control system) — — UDCC Creates linear tape counter — — PWM0, PWM1, 16-bit resolution (carrier frequency: 62.5 kHz) (16-bit timer) PWM output unit — PWM5 PWM2, PWM3, 8-bit resolution (carrier frequency: 62.5 kHz) PWM4 Data Sheet U12255EJ2V0DS00 35 µPD784927, 784928, 784927Y, 784928Y (1) Timer 0 unit Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the drum motor. This unit consists of an event counter (EC: 8 bits), compare registers (ECC0 through ECC3), a timer (TM0: 16 bits), and compare registers (CR00 through CR02). A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used as the output trigger of the real-time output port. (2) Free running counter unit The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed of the capstan motor. This unit consists of a free running counter (FRC), capture registers (CPT0 through CPT5), a VSYNC separation circuit, and a HSYNC separation circuit. (3) Timer 1 unit Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the following three groups: • Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12) • Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30) • Event divider counter (EDV) and compare register (EDVC) The TM1-CR13 coincidence signal can be used for automatic unmasking of VSYNC or as the output trigger of the real-time output port. 36 Data Sheet U12255EJ2V0DS00 Selector Selector Selector Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1) DPGIN Divider Clear EC F/F CFGIN Selector RTP, A/D RTP, A/D (Superimposition) PTO01 INTCR01 PTO02 INTCR02 To P80 CPT0 CPT1 CPT2 CPT3 CPT4 CPT5 INTCPT1 INTCPT2 INTCPT3 Selector Capture Capture Capture Capture Capture Capture Clear EDV INTP3 Output control circuit Clear TM3 37 CR30 CR31 Capture CPT30 RTP FRC Selector Mask Selector Selector Output control circuit PTO00 INTCR00 INTCLR1 EDVC PBCTL PTO10 PTO11 Output control circuit (Superimposition) Selector Selector REEL1IN CR00 CR01 CR02 HSYNC separation circuit Selector REEL0IN Output control circuit F/F VSYNC separation circuit Selector Selector Analog circuit ECC3 ECC2 ECC1 ECC0 Clear TM0 Capture CTL F/F FFLVL Clear TM1 CR10 CR11 CR12 CR13 PTO10 INTCR10 Output control circuit PTO11 INTCR11 INTCR12 INTCR13 INTCR30 To PBCTL signal input block µPD784927, 784928, 784927Y, 784928Y Data Sheet U12255EJ2V0DS00 CSYNCIN Selector Selector DFGIN Selector Mask Selector Writes 00H to EC µPD784927, 784928, 784927Y, 784928Y (4) Timer 2 unit Timer 2 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM2) and a compare register (CR20). The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, an interrupt request is generated. Figure 3-11. Block Diagram of Timer 2 Unit Clear TM2 INTCR20 CR20 (5) Timer 4 unit Timer 4 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM4), a capture/compare register (CR40), and a capture register (CR41). The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to decode a remote controller signal. Figure 3-12. Block Diagram of Timer 4 Unit Mask Clear INTP2 Selector TM4 CR40 INTCR40 CR41 (6) Timer 5 unit Timer 5 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM5) and a compare register (CR50). The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt request is generated. Figure 3-13. Block Diagram of Timer 5 Unit Clear TM5 CR50 INTCR50 RTP, A/D 38 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y (7) Up/down counter unit The up/down counter unit is a counter that realizes a linear time counter. This unit consists of an up/down counter (UDC) and a compare register (UDCC). The up/down counter counts up the rising edges of PBCTL and counts down the falling edges of PBCTL. When the value of the up/down counter coincides with the value of the compare register, or when the counter underflows, an interrupt request is generated. PTO10 PTO11 Selector EDVC output Selector PBCTL P77 UP/DOWN Selector SELUD Selector Figure 3-14. Block Diagram of Up/Down Counter Unit UDC UDCC INTUDC (8) PWM output unit The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy output lines (PWM2 through PWM4). The carrier frequency of all the output lines is 62.5 kHz (fCLK = 8 MHz). PWM0 and PWM1 can be used to control the drum motor and capstan motor. Figure 3-15. Block Diagram of 16-Bit PWM Output Unit (n = 0, 1, 5) Internal bus 16 PWMn 15 8 7 8 0 PWMC0 8 Reload 16 MHz 8 To selector Reload Reload control PWM pulse generation circuit 8-bit down counter 1/256 PWMn Output control circuit 8-bit counter RESET Data Sheet U12255EJ2V0DS00 39 µPD784927, 784928, 784927Y, 784928Y Figure 3-16. Block Diagram of 8-Bit PWM Output Unit Internal bus PWM2 PWM3 PWM4 8-bit comparator 8-bit comparator 8-bit comparator 16 MHz PWM counter PWMC1 Output control circuit PWM4 Output control circuit PWM3 Output control circuit PWM2 (9) VISS detection circuit Figure 3-17. Block Diagram of VISS Detection Circuit PBCTL UP/DOWN fCLK/16 fCLK/64 Selector CFG signal VUDST (VUDC value setting register) VUDC (8-bit up/down counter) fCLK/256 VISS malfunction prevention circuit VSFT0 (shift register 0) VSFT1 (shift register 1) Coincidence VPS (VISS pulse pattern setting register) 40 VCMP (compare register) Data Sheet U12255EJ2V0DS00 INTVISS µPD784927, 784928, 784927Y, 784928Y (10) VSYNC separation circuit Figure 3-18. Block Diagram of VSYNC Separation Circuit CSYNC signal Digital noise rejection circuit Selector fCLK/4 fCLK/8 VSUDC (8-bit up/down counter) VSCMP (8-bit compare register) Selector VSYNC F/F S VSYNC Q R "00" 3.7 Serial Interface The µPD784927 is provided with the serial interfaces shown in Table 3-6. Data can be automatically transmitted or received through these serial interfaces, when the macro service is used. Table 3-6. Types of Serial Interfaces Name Serial interface channel 1 Function • Clocked serial interface (3-wire) • Bit length: 8 bits • Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) • MSB first/LSB first selectable Serial interface channel 2 • Clocked serial interface (3-wire) • Bit length: 8 bits • Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) • MSB first/LSB first selectable • BUSY/STRB control function Serial interface channel 3 • I2C bus interface For multimaster Data Sheet U12255EJ2V0DS00 41 µPD784927, 784928, 784927Y, 784928Y (1) Serial interface channels 1, 2 Figure 3-19. Block Diagram of Serial Interface Channel n (n = 1 or 2) SIn /BUSY Selector Internal bus SIOn register CSIMn register SOn Serial clock counter INTCSIn Busy detection circuit STRB Selector SCKn fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 fCLK/256 Strobe generation circuit CSIC2 register Internal bus Remark The circuits enclosed in the broken line are provided to serial interface channel 2 only. 42 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y (2) Serial interface channel 3 (µPD784928Y subseries only) This channel transfers 8-bit data with multiple devices using two lines: serial clock (SCL) and serial data bus (SDA). It conforms to the I2C bus format, and can output a “start condition”, “data”, and “stop condition” onto the serial data bus during transmission. This data is automatically detected by hardware during reception. SCL and SDA are open-drain output pins and therefore, must be connected with a pull-up resistor. Figure 3-20. Serial Interface Channel 3 +VDD +VDD Master CPU1 Slave CPU1 SDA SCL Serial data bus Serial clock Data Sheet U12255EJ2V0DS00 SDA Master CPU2 Slave CPU2 SCL Address 1 SDA Slave CPU3 SCL Address 2 SDA Slave IC SCL Address 3 SDA Slave IC SCL Address N 43 µPD784927, 784928, 784927Y, 784928Y 3.8 A/D Converter The µPD784927Y has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 through ANI11). This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion result register (ADCR) (conversion time: 10 µs at fCLK = 8 MHz). A/D conversion can be started in the following two modes: • Hardware start : Conversion is started by a hardware triggerNote. • Software start : Conversion is started by setting a bit of the A/D converter mode register (ADM). After conversion has been started, the A/D converter operates in the following modes: • Scan mode : Sequentially selects more than one analog input to obtain data to be converted from all the pins. • Select mode: Use only one pin for analog input to obtain successive data to be converted. When the conversion result is transferred to ADCR, interrupt request INTAD is generated. By processing this interrupt with the macro service, the conversion result can be successively transferred to memory. A mode in which starting A/D conversion of the next pin is kept pending until the value of ADCR is read is also available. When this ode is used, reading the conversion result by mistake when timing is shifted because an interrupt is disabled can be prevented. Note A hardware trigger is the following coincidence signals, one of which is selected by the trigger source select register 1 (TRGS1): • TM0-CR01 coincidence signal • TM0-CR02 coincidence signal • TM1-CR13 coincidence signal • TM5-CR50 coincidence signal 44 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Figure 3-21. Block Diagram of A/D Converter ADM.7 (CS) ANI0 ANI3 . . . . . . 1 : ON Voltage comparator ANI11 TM0-CR01 coincidence TM0-CR02 coincidence TM1-CR13 coincidence Selector Successive approximation register (SAR) TM5-CR50 coincidence AVSS2 Control circuit Trigger source select register 1 (TRGS1) A/D converter mode register (ADM) R R/2 Conversion trigger Trigger enable AVREF R/2 Tap selector ANI2 Series resistor string Sample & hold circuit Input selector ANI1 8 Delay detection circuit 16 INTAD A/D conversion end interrupt A/D conversion result register (ADCR) 8 Internal bus 3.9 VCR Analog Circuits The µPD784927 is provided with the following VCR analog circuits: • CTL amplifier • RECCTL driver (rewritable) • DPG amplifier • DFG amplifier • DPFG separation circuit (ternary separation circuit) • CFG amplifier • Reel FG comparator (2 channels) • CSYNC comparator Data Sheet U12255EJ2V0DS00 45 µPD784927, 784928, 784927Y, 784928Y (1) CTL amplifier/RECCTL driver The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal recorded on a VCR tape. The gain of the CTL amplifier is set by the gain control register (CTLM). Thirty-two types of gains can be set in increments of about 1.78 dB. The µPD784927 is also provided with a gain control signal generation circuit that monitors the status of the amplifier output to perform optimum gain control by software. The gain control signal generation circuit generates a CTL detection flag that identifies the amplitude status of the CTL amplifier output. By using this CTL detection flag, the gain of the CTL amplifier can be optimized. The RECCTL driver writes a control signal onto a VCR tape. This driver operates in two modes: REC mode that is used for recording, and rewrite mode used to rewrite the VISS signal. The output status of the RECCTL± pin is changed by hardware, by using the timer output from the super timer unit as a trigger. Figure 3-22. Block Diagram of CTL Amplifier and RECCTL Driver ANI11 CTLDLY RECCTL+ RECCTL driver RECCTL- CTL head Selector TOM1.4-TOM1.6 TM1-CR11 coincidence signal TM1-CR13 coincidence signal TM3-CR30 coincidence signal VREF AMPC. 1 + - AMPC. 1 CTLIN + Gain control signal generation circuit CTLOUT1 CTL detection flag L (AMPM0. 1) CTL detection flag S (AMPM0. 3) CTL detection flag clear (1 write to AMPM0. 6) CTLM. 0-CTLM. 4 CTLOUT2 Waveform shaping circuit PBCTL signal (to timer unit) CTLMON (to P67) 46 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y (2) DPG amplifier, DFG amplifier, and DFPG separation circuit The DPG amplifier converts the drum PG (DPG) signal that indicates the phase information of the drum motor into a logic signal. The DFG amplifier amplifies the drum FG (DFG) signal that indicates the speed information of the drum motor. The DPFG separation circuit (ternary separation circuit) separates a drum PFG (DPFG) signal having speed and phase information into a DFG and DPG signals. Figure 3-23. Block Diagram of DPG Amplifier, DFG Amplifier, and DPFG Separation Circuit AMPC.7 VREF AMPC.2 AMPM0.2 AMPC.2 1 DPGIN VREF 0 DPG comparator + 1 0 Selector 0 : ON Drum PG signal Selector AMPM0.0 DPG signal (to timer unit) DPGMON (to P65) – DPG amplifier VREF + AMPM0.0 DFG amplifier – DFGIN AMPM0.2 AMPM0.2 1 AMPC.2 AMPC.2 DPFG separation circuit (ternary separation circuit) 1 0 AMPM0.2 1 Selector 0 Selector Drum FG signal or drum PFG signal AMPC.2 0 Data Sheet U12255EJ2V0DS00 DFG signal (to timer unit) DFGMON (to P64) 47 µPD784927, 784928, 784927Y, 784928Y (3) CFG amplifier The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational amplifier is set by using an external resistor. When the gain of the operational amplifier is set to 50 dB, the output duty accuracy of the CFG signal can be improved to 50.0 ± 0.3%. Figure 3-24. Block Diagram of CFG Amplifier VREF AMPC.3 + CFG amplifier - Capstan FG signal CFGIN AMPM0.0 VREF AMPC.3 AMPC.3 - CFG comparator CFGCPIN 1 + 0 Selector CFGAMPO CFG signal (to timer unit) CFGMON (to P66) (4) Reel FG comparators The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into a logic signal. Two comparators, one for take-up and the other for supply, are provided. Figure 3-25. Block Diagram of Reel FG Comparators VREF AMPC.6 AMPM0.0 REEL0IN Reel FG comparator 0 Selector 1 Supply reel signal Reel FG0 signal (to timer unit) VREF AMPC.6 AMPC.6 AMPM0.0 REEL1IN Reel FG comparator 0 48 Data Sheet U12255EJ2V0DS00 Selector 1 Take-up reel signal Reel FG1 signal (to timer unit) µPD784927, 784928, 784927Y, 784928Y (5) CSYNC comparator The CSYNC comparator converts the COMPSYNC signal into a logic signal. Figure 3-26. Block Diagram of COMPSYNC Comparator VREF AMPM1.7 AMPC.5 AMPC.5 AMPM0.0 CSYNCIN CSYNC comparator 0 Selector 1 COMPSYNC signal CSYNC signal (to timer unit) (6) Reference amplifier The reference amplifier generates a reference voltage (VREF) to be supplied to the internal amplifiers and comparators of the µPD784927. Figure 3-27. Block Diagram of Reference Amplifier ENCAP (AMPC.3) AVDD1 VREFC + AVSS1 VREF (CFG amplifier) + VREF (CFG amplifier) ENCTL (AMPC.1) + VREF (CTL amplifier) ENDRUM (AMPC.2) ENREEL (AMPC.6) ENCSYN (AMPC.5) + VREF DFG amplifier, DPG comparator, reel FG comparator, and CSYNC comparator) Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators. Data Sheet U12255EJ2V0DS00 49 µPD784927, 784928, 784927Y, 784928Y (7) Analog circuit monitor function This function is to output the following signals to port pins, and is mainly used for debugging. • Comparator output of CTL amplifier → CTLMON (multiplexed port: P67) • Comparator output of CFG amplifier → CFGMON (multiplexed port: P66) • Comparator output of DPG amplifier → DPGMON (multiplexed port: P65) • Comparator output of DFG amplifier → DFGMON (multiplexed port: P64) 3.10 Watch Function The µPD784927 has a watch function that counts the overflow signals of the watch timer by hardware. As the clock, the subsystem clock (32.768 kHz) is used. Because this watch function is independent of the CPU, it can be used even while the CPU is in the standby mode (STOP mode) or is reset. In addition, this function can be used at a low voltage of VDD = 2.7 V (MIN.). Therefore, by using only the watch function with the CPU set in the standby mode or reset, a watch operation can be performed at a low voltage and low current consumption. In addition, the watch function can also be used while the CPU is in the normal operation mode, because a dedicated counter is provided. The watch function can be used to count up to about 17 years of data. The hardware watch counters (HW0 and HW1) are shared with external input counters. These counters execute counting at the falling edge of input to the P65 pin, and can be used to count the HSYNC signals. Figure 3-28. Block Diagram of Watch Counter PM65 PMC65 P65 CMS5 Edge detection P65 Pin level read 13 0 Watch timer Normal 1 Fast forward 0 WM.2 (enables/disables operation) 0 15 0 HW0 WM.2 Selector WM.1 Subclock BUZ signal WM.7 WM.5 WM.4 WM.2 50 13 HW1 Selector 0 Selector fXT (32.768 kHz) 1 Selector WM.2 (enables/disables operation) Data Sheet U12255EJ2V0DS00 To NMI generation block WM.6 INTW µPD784927, 784928, 784927Y, 784928Y 3.11 Clock Output Function The µPD784927 can output a square wave (with a duty factor of 50%) to the P60/STRB/CLO pin as the operating clock for the peripheral devices or other microcomputers. To enable or disable the clock output, and to set the frequency of the clock, the clock output mode register (CLOM) is used. When setting the frequency, the division ratio can be set to fCLK/n (where n = 1, 2, 4, 8, 16, 32, 64, or 128) (fCLK = fOSC/2: fOSC is the oscillation frequency of the resonator). Figure 3-29 shows the block diagram of the clock output circuit. The clock output (CLO) pin is shared with P60 and STRB. Figure 3-29. Block Diagram of Clock Output Circuit CLOM CLOM7 CLOM6 CLOM5 ENCLO 0 SELFRQ2 SELFRQ1 SELFRQ0 fCLK fCLK/2 Selector fCLK/4 fCLK/16 1 fCLK/32 P60 (Output latch) fCLK/64 0 Selector fCLK/8 P60/STRB/CLO RESET fCLK/128 Remark fCLK: internal system clock Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP mode. Figure 3-30. Application Example of Clock Output Function µ PD784927 µ PD7503A LCD 24 CLO SCK1 SI1 SO1 System clock CL1 SCK SO SI Data Sheet U12255EJ2V0DS00 51 µPD784927, 784928, 784927Y, 784928Y 3.12 Buzzer Output Function The BUZ signal can be superimposed on P61 or P64. The buzzer output frequency can be generated from the subsystem clock frequency or main system clock frequency. Figure 3-31 shows the block diagram of the BUZ output circuit. The BUZ signal can be also used for trimming the subsystem clock. Figure 3-31. Block Diagram of BUZ Output Circuit WM4 CMS4 WM5 WM7 P61 (Output latch) 32.768 kHz 1 CLOM5 CLOM6 1 fCLK/2048 fCLK/4096 52 Selector fCLK/512 Selector 0 fCLK/1024 0 Selector CLOM7 P61/BUZ Selector 4.096 kHz Selector 2.048 kHz P64/BUZ BUZ output 0 P64 (Output latch) 1 BUZ output Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 4. INTERNAL/EXTERNAL CONTROL FUNCTION 4.1 Interrupt Function The µPD784927 has as many as 32 interrupt sources, including internal and external sources. For 28 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by software. Table 4-1 lists the interrupt sources. Data Sheet U12255EJ2V0DS00 53 µPD784927, 784928, 784927Y, 784928Y Table 4-1. Interrupt Sources Interrupt Interrupt Request Source Request Priority Name Type Reset — RESET Non- — NMI 0 INTP0 Trigger Interrupt Control Register Name RESET pin input — NMI pin input edge — Macro Context Macro Service Service Switching Control Word No No Vector Table Address Address — 0000H — 0002H FE06H 0006H maskable Maskable INTP0 pin input edge PIC0 Yes Yes 1 INTCPT3 EDVC output signal (CPT3 capture) CPTIC3 FE08H 0008H 2 INTCPT2 DFGIN pin input edge (CPT2 capture) CPTIC2 FE0AH 000AH 3 INTCR12 PBCTL input edge/EDVC output signal CRIC12 FE0CH 000CH (CR12 capture) 4 INTCR00 TM0-CR00 coincidence signal CRIC00 FE0EH 000EH 5 INTCLR1 CSYNCIN pin input edge CLRIC1 FE10H 0010H 6 INTCR10 TM1-CR10 coincidence signal CRIC10 FE12H 0012H 7 INTCR01 TM0-CR01 coincidence signal CRIC01 FE14H 0014H 8 INTCR02 TM0-CR02 coincidence signal CRIC02 FE16H 0016H 9 INTCR11 TM1-CR11 coincidence signal CRIC11 FE18H 0018H 10 INTCPT1 Pin input edge/EC output signal CPTIC1 FE1AH 001AH (CPT1 capture) 11 INTCR20 TM2-CR20 coincidence signal CRIC20 FE1CH 001CH 12 I2 C IICICNote FE1EH 001EH INTIIC End of bus transfer 13 INTTB Time base from FRC TBIC FE20H 0020H 14 INTAD A/D converter conversion end ADIC FE22H 0022H 15 INTP2 INTP2 pin input edge PIC2 FE24H 0024H INTCR40 TM4-CR40 coincidence signal Operand 16 INTUDC UDCIC FE26H 0026H 17 INTCR30 TM3-CR30 coincidence signal CRIC30 FE28H 0028H 18 INTCR50 TM5-CR50 coincidence signal CRIC50 FE2AH 002AH 19 INTCR13 TM1-CR13 coincidence signal CRIC13 FE2CH 002CH 20 INTCSI1 CSIIC1 FE2EH 002EH 21 INTW WIC FE30H 0030H 22 INTVISS VISS detection signal VISIC FE32H 0032H 23 INTP1 INTP1 pin input edge PIC1 FE34H 0034H 24 INTP3 25 INTCSI2 — — error End of serial transfer (channel 1) Overflow of watch timer INTP3 pin input edge End of serial transfer (channel 2) PIC3 FE36H 0036H CSIIC2 FE3AH 003AH — 003CH — 003EH — — Illegal operand of MOV STBC, #byte or — — Execution of BRK instruction — — — Execution of BRKCS instruction — µPD784928Y subseries only. Remark EVDC : Event divider compare register EC : Event counter FRC : Free running counter MSCW : Macro service control register 54 — No No LOCATION instruction Software Note UDC-UDCC coincidence/UDC underflow CRIC40 Data Sheet U12255EJ2V0DS00 Yes µPD784927, 784928, 784927Y, 784928Y Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode Macro service Main routine Macro service processing Main routine Context Note 1 switching Main routine Note 2 Vectored Note 1 interrupt Main routine Note 4 SEL RBn Main routine Note 4 Saving general-purpose register Vectored interrupt Interrupt processing Interrupt processing Initializing general-purpose register Note 3 Main routine Restoring PC and PSW Interrupt processing Main routine Restoring general-purpose register Restoring PC and PSW Main routine Interrupt request generated Notes 1. When the register bank switching function is used and when initial values are set in advance to the registers 2. Selecting a register bank and saving PC and PSW by context switching 3. Restoring register bank, PC, and PSW by context switching 4. Saves PC and PSW to stack and loads vector address to PC Data Sheet U12255EJ2V0DS00 55 µPD784927, 784928, 784927Y, 784928Y 4.1.1 Vectored interrupt When an interrupt request is acknowledged, an interrupt processing program is executed according to the data stored in the vector table area (the first address of the interrupt processing program created by the user). In addition, four levels of priorities can be specified by software. 4.1.2 Context switching When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched to an interrupt processing routine more quickly than the vectored interrupt. Figure 4-2. Context Switching Operation When Interrupt Request Is Generated Register bank (0-7) <7> 0H Register bank n (n = 0-7) PC19-16 PC15-0 A <6> Exchange <2> Save Bits 8-11 of temporary register B C R5 R4 R7 <5> Save Temporary register <1> Save X V R6 VP U UP T D E W H L PSW 56 Data Sheet U12255EJ2V0DS00 <3> Switching register bank (RBS0-RBS2 ← n) <4> RSS ← 0 IE ← 0 µPD784927, 784928, 784927Y, 784928Y 4.1.3 Macro service The macro service is a function to transfer data between the memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data. Because the status of the CPU is not saved or restored, data can be transferred more quickly than context switching. The processing that can be executed with the macro service is described below. Figure 4-3. Macro Service CPU Memory Read Write Macro service controller Write Read SFR Internal bus (1) Counter mode In this mode, the value of the macro service counter (MSC) is decremented when an interrupt request occurs. This mode can be used to execute the division operation of an interrupt request or count the number of times an interrupt request has occurred. When the value of the macro service counter has been decremented to 0, a vectored interrupt occurs. MSC -1 (2) Compound data transfer mode When an interrupt request occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX. for each transfer). This mode can also be used to exchange data, instead of transferring data. This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/ timing by the serial output port. When the value of the macro service counter reaches to 0, a vectored interrupt request occurs. Memory SFR<4>-1 SFR<4>-2 SFR<4>-3 SFR<3>-1 SFR<3>-2 SFR<3>-3 SFR<1>-2 SFR<1>-3 .. . Internal bus SFR<2>-1 SFR<2>-2 SFR<2>-3 SFR<1>-1 Internal bus Data Sheet U12255EJ2V0DS00 57 µPD784927, 784928, 784927Y, 784928Y (3) Macro service type A When an interrupt request occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from memory (byte/word) to an 8-/16-bit SFR. Data is transferred the number of times set in advance by the macro service counter. This mode can be used to store the result of A/D conversion or for automatic transfer (or reception) by the serial interface. Because transfer data is stored at an address FE00H to FEFFH, if only a small quantity of data is to be transferred, the data can be transferred at high speeds. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. Data storage buffer (memory) Data storage buffer (memory) Data n Data n Data n - 1 Data n - 1 Data 2 Data 2 Data 1 Data 1 Internal bus Internal bus SFR SFR (4) Data pattern identification mode (VISS detection mode) This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width detection circuit. When an interrupt request occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer 1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in the compare area. If the two data coincide, a vectored interrupt request is generated. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates). Buffer area (memory) Coefficient (memory) Compare area (memory) CPT30 Multiplier TM3 Coincidence CR30 CTL F/F (bit 7 of TMC3) 58 Data Sheet U12255EJ2V0DS00 Vectored interrupt µPD784927, 784928, 784927Y, 784928Y 4.1.4 Application example of macro service (1) Automatic transfer/reception of serial interface Automatic transfer/reception of 3-byte data by serial interface channel 1 Setting of macro service register: compound data transfer mode (exchange mode) 7 0 FE50H High-order address Mode register (= 10110011B) FE2EH Low-order address Macro service counter (MSC = 2) Memory pointer H (= FD) Macro service channel Memory pointer L (= 50) ddccbbaa (= 01000100B) SFR pointer <2> (SFRP2 = 85H) SFR pointer <4> (SFRP4 = 85H) Channel pointer (= 50H) Macro service control word (Before transfer) (Exchange 2) Transmit data 3 FD52H SI1 SIO1 (FF85H) <3> SO1 Transmit data 2 FD51H <2> (Exchange 1) (Transmit data 1) FD50H <1> Transfer is started by writing transmit data 1 to SIO1 by software. (After transfer) Receive data 2 FD51H Receive data 1 FD50H (Receive data 3 is the data of SIO1.) Data Sheet U12255EJ2V0DS00 59 µPD784927, 784928, 784927Y, 784928Y (2) Reception operation of serial interface Transfer of receive data by serial interface channel 1 (16 bytes) Setting of macro service mode register: macro service type A (1-byte data transfer from SFR to memory) Internal RAM FE7FH MSC 0FH SFR pointer 85H Setting of number of transfers Low-order 8 bits of address of SIO1 register Channel pointer (= 7FH) FE2EH Mode register (= 00010001B) Starts macro service when INTCSI1 occurs SI1 60 SIO1 (FF85H) Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y (3) VISS detection operation Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte comparison) CPT30 High-order address TM3 FE50H Macro service counter (MSC = FFH) SFR pointer 2 (SFRP2 = 56H) Multiplier Coefficient (6EH: 43%) CR30 SFR pointer 3 (SFRP3 = 5CH) Bit 7 SFR pointer 1 (SFRP1 = 3BH) Buffer size specification register (64 bits: 8H) 0 TMC3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 8 bytes 1050H 8 bytes Compare area pointer (high): 10H Compare area pointer (low): 50H Coincidence (vectored interrupt) Channel pointer (= 50H) FE0CH Mode register (= 00010100B) (CTL signal input edge detection interrupt) Low-order address Data Sheet U12255EJ2V0DS00 61 µPD784927, 784928, 784927Y, 784928Y 4.2 Standby Function The standby function is to reduce the power consumption of the chip and is used in the following modes: Mode Function HALT mode Stops operating clock of CPU. Reduces average power consumption when used in combination with normal mode for intermittent operation STOP mode Stops oscillator. Stops all internal operations of chip to minimize power consumption to leakage current only Low power consumption mode Stops main system clock with subsystem clock used as system clock. CPU can operate with subsystem clock to reduce current consumption Low power consumption HALT mode Standby function in low power consumption mode. Stops operating clock of CPU. Reduces power consumption of overall system These modes are programmable. The macro service can be started in the HALT mode. Figure 4-4. Status Transition of Standby Function Ma Sets low power consumption mode En st ue ss ing req ce ce rvi se cro Ma pro P TO sS ce ne put T in SE RE Set ode st HAL ion mpt nsu En Set s lo se ng Macro service 2 wp owe r co P2 Tm ue req pt rru inte 1 t Note INT pu st ssi rvi Note W, ue ce est I in req T t 1 Low power consumption HALT mode (standby) ro ce pro HAL te pu No I in INT Sets put requ ET in rupt Waits for stabilization of oscillation Inter RES E NM NM ac n st io cil at f os nd o rvi ne fm np se fo do eriod atio abiliz do fo Restores normal operation cro En Normal operation do Low power consumption mode (subsystem clock operation) STOP mode (standby) HALT mode (standby) Unmasked interrupt request Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input. 2. Unmasked interrupt request 62 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released INTM0.0 NMI Selector Standby control block Latch Interrupt control block Clear INTP1 INTP2 KEY0 KEY1 KEY2 S Q KEY3 KEYC.7 R KEY4 Cleared when "0" is written to KEYC.7 Mask KEYC.6 Mask KEYC.5 Mask KEYC.4 S Q KEYC.0 R Selector WM.6 Cleared when "0" is written to KEYC.0 Watch timer INTW (OVF) Divides INTW by 128 (HW0L.7) Mask WM.3 Data Sheet U12255EJ2V0DS00 63 Normal mode 1/2 1/2 1/2 1/2 fXX/8 (fXX/4)Note 1 fXX/4 (fXX/2)Note 1 Oscillation stop From standby control block STBC.6 fXX/16 (fXX/8)Note 1 fXX/2 (fXX)Note 1 Selector fXX Selector Low-frequency oscillation mode Selector X2 16 MHz or 8 MHz Main system clock oscillation circuit fCLK CPU Peripheral hardware operation clockNote 2 XT1 XT2 32.768 kHz fXT Watch timer Hardware watch function Watch interrupt Oscillation stop STBC.7 Notes 1. fXX: oscillation frequency, ( ): in low-frequency oscillation mode. 2. The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to µPD784928, 784928Y Subseries User’s Manual-Hardware (U12648E). µPD784927, 784928, 784927Y, 784928Y Data Sheet U12255EJ2V0DS00 Subsystem clock oscillation circuit 4.3 Clock Generation Circuit X1 STBC.4, 5 Oscillation stabilization timer The clock generation circuit generates and controls the internal system clock (CLK) to be supplied to the CPU and CC.7 µ PD784927 peripheral circuits. Figure 4-6 shows the configuration of this circuit. 64 Figure 4-6. Block Diagram of Clock Generation Circuit µPD784927, 784928, 784927Y, 784928Y 4.4 Reset Function When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the current consumption of the overall system can be reduced. When the RESET pin goes high, the reset status is cleared. After the count time of the oscillation stabilization timer (32.8 ms at 16 MHz or 65.6 ms at 8 MHz) has elapsed, the contents of the reset vector table are set to the program counter (PC), and execution branches to the address set to the PC, and the program is executed starting from the branch destination address. Therefore, execution can be reset and started from any address. Figure 4-7. Oscillation of Main System Clock during Reset Period Main system clock oscillation circuit During reset, oscillation is unconditionally stopped. fCLT RESET input Oscillation stabilization timer count time The RESET pin is provided with an analog delay noise rejection circuit to prevent malfunctioning due to noise. Figure 4-8. Accepting Reset Signal Analog delay Analog delay Oscillation Analog stabilization delay time RESET input Internal reset signal Internal clock Data Sheet U12255EJ2V0DS00 65 µPD784927, 784928, 784927Y, 784928Y 5. INSTRUCTION SET (1) 8-bit instructions (( ): combination realized by using A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA 2nd Operand # byte A r saddr r' saddr' sfr !addr16 !!addr24 1st Operand A r3 [saddrp] PSWL [%saddrg] PSWH [WHL+] [WHL–] (MOV) (MOV) MOV (MOV)Note 6 MOV (MOV) MOV (MOV) (MOV) ADDNote 1 (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH (XCH) (XCH) ADDNote 1 (ADD)Note 1 (ADD)Note 1 (ADD)Note 1 (ADD)Note 1 (ADD)Notes 1,6 (ADD)Note 1 ADDNote 1 r mem MOV (MOV) MOV MOV MOV MOV ADDNote 1 (XCH) XCH XCH XCH XCH MOV n NoneNote 2 RORNote 3 MULU DIVUW (ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1 INC DEC saddr MOV (MOV)Note 6 MOV MOV INC ADDNote 1 (ADD)Note 1 ADDNote 1 XCH DEC ADDNote 1 sfr MOV MOV DBNZ MOV PUSH ADDNote 1 (ADD)Note 1 ADDNote 1 POP CHKL CHKLA !addr16 MOV (MOV) MOV ADDNote 1 !!addr24 mem MOV [saddrp] ADDNote 1 [%saddrg] mem3 ROR4 ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM [TDE+] MOV MOVBKNote 5 (MOV) (ADD)Note 1 MOVMNote 4 [TDE–] MOVBKNote 5 (MOV) (ADD)Note 1 MOVMNote 4 Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operation is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 66 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y (2) 16-bit instructions (( ): combination realized by using AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW 2nd Operand # word AX rp saddrp rp' saddrp sfrp !addr16 !!addr24 1st Operand AX mem [WHL+] byte n None Note 2 [saddrp] [%saddrg] (MOVM) ADDW Note 1 (MOVW) (MOVW) (MOVW)Note 3 MOVW (MOVW) MOVW (MOVW) (XCHW) (XCHW) (XCHW)Note 3 (XCHW) XCHW XCHW (XCHW) (ADDW)Note 1 (ADDW)Note 1 (ADDW)Notes 1,3 (ADDW)Note 1 rp MOVW ADDW saddrp Note 1 MOVW ADDW Note 1 (MOVW) MOVW MOVW MOVW (XCHW) XCHW XCHW XCHW MOVW SHRW SHLW MULWNote 4 INCW (ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 DECW (MOVW)Note 3 MOVW INCW MOVW (ADDW)Note 1 ADDWNote 1 XCHW DECW ADDWNote 1 sfrp MOVW MOVW MOVW PUSH ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 MOVW (MOVW) POP MOVW MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operation is not an operand address. 3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 4. MULUW and DIVUX are the same as MULW. Data Sheet U12255EJ2V0DS00 67 µPD784927, 784928, 784927Y, 784928Y (3) 24-bit instructions (( ): combination realized by using WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP 2nd Operand # imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP NoneNote rg' 1st Operand WHL rg (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG MOVG (MOVG) MOVG MOVG ADDG (ADDG) ADDG SUBG (SUBG) SUBG (MOVG) MOVG MOVG MOVG MOVG INCG DECG PUSH POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG DECG Note Either the second operand is not used, or the second operation is not an operand address. (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET 2nd Operand CY 1st Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit Note 68 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit iaddr16.bit !addr24.bit /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit MOV1 AND1 OR1 XOR1 AND1 OR1 MOV1 NoneNote NOT1 SET1 CLR1 NOT1 SET1 CLR1 BF BT BTCLR BFSET Either the second operand is not used, or the second operation is not an operand address. Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y (5) Call/return and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Operand of $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn CALLF CALLT BRKCS None instruction address Basic BCNote CALL CALL CALL CALL CALL CALL CALL instruction BR BR BR BR BR BR BR BR Compound BF instruction BT BRK RET RETCS RETI RETCSB RETB BTCLR BFSET DBNZ Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS Data Sheet U12255EJ2V0DS00 69 µPD784927, 784928, 784927Y, 784928Y 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Conditions Analog input voltage Unit VDD | VDD – AVDD1 | ≤ 0.5 V –0.5 to +7.0 V AVDD1 | VDD – AVDD2 | ≤ 0.5 V –0.5 to +7.0 V AVDD2 | AVDD1 – AVDD2 | ≤ 0.5 V –0.5 to +7.0 V –0.5 to +0.5 V AVSS2 –0.5 to +0.5 V VI –0.5 to VDD + 0.5 V VDD ≥ AVDD2 –0.5 to AVDD2 + 0.5 V VDD < AVDD2 –0.5 to VDD + 0.5 V AVSS1 Input voltage Ratings VIAN (ANI0-ANI11) Output voltage VO Low-level output current IOL High-level output current IOH –0.5 to VDD + 0.5 V 15 mA Total of all pins 100 mA Pin 1 –10 mA Total of all pins –50 mA Pin 1 Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. Never exceed these values when using the product. Operating Conditions Clock Frequency 4 MHz ≤ fXX ≤ 16 MHz 32 kHz ≤ fXT ≤ 35 kHz Operating Ambient Temperature (TA) –10 to +70°C Operating Conditions +4.5 to +5.5 V CPU function only +4.0 to +5.5 V Subclock operation +2.7 to +5.5 V (CPU, watch, and port functions only) 70 Supply Voltage (VDD) All functions Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Oscillator Characteristics (main clock) (TA = –10 to +70°C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) Resonator Recommended Circuit Crystal resonator Parameter Oscillation frequency (fXX) X1 X2 C1 MIN. MAX. Unit 4 16 MHz VSS C2 Oscillator Characteristics (subclock) (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) Resonator Recommended Circuit Crystal resonator Oscillation frequency (fXT) XT1 C1 Caution Parameter XT2 MIN. MAX. Unit 32 35 kHz VSS C2 When using the main system clock and subsystem clock oscillator, wire the portion enclosed by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not route the wiring in the neighborhood of a signal line through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator to the same potential as VSS. Do not ground the capacitor to a ground pattern to which a high current flows. • Do not extract signals from the oscillation circuit. Exercise particular care in using the subsystem clock oscillator because the amplification factor of this circuit is kept low to reduce the current consumption. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U12255EJ2V0DS00 71 µPD784927, 784928, 784927Y, 784928Y DC Characteristics (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Symbol Conditions MIN. TYP. MAX. Unit VIL1 Pins other than those listed in Note 1 below 0 0.3 VDD V VIL2 Pins listed in Note 1 below 0 0.2 VDD V VIL3 X1, X2 VIH1 Pins other than those listed in Note 1 below VIH2 Pins listed in Note 1 below V IH3 X1, X2 0 0.4 V 0.7 VDD VDD V 0.8 V DD V DD V V DD – 0.5 V DD V V OL1 I OL = 8.0 mA (pins in Note 2) 1.0 V V OL2 I OL = 5.0 mA (pins in Note 4) 0.6 V V OL3 I OL = 2.0 mA 0.45 V V OL4 I OL = 100 µ A 0.25 V V OH1 I OH = –1.0 mA V DD – 1.0 V V OH2 I OH = –100 µ A V DD – 0.4 V Input leakage current I LI 0 ≤ V I ≤ V DD ±10 µA Output leakage current I LO 0 ≤ V O ≤ V DD ±10 µA V DD supply current I DD1 Operation f XX = 16 MHz 30 50 mA mode fXX = 8 MHz (low-frequency os- 50 80 µA 10 25 mA 25 50 µA cillation mode) Internally, 8 MHz main clock operation f XT = 32.768 kHz Subclock operation (CPU, watch, port) VDD = 2.7 V I DD2 HALT mode f XX = 16 MHz fXX = 8 MHz (low-frequency oscillation mode) Internally, 8 MHz main clock operation f XT = 32.768 MHz Subclock operation (CPU, watch, port) VDD = 2.7 V Data hold voltage Data hold current Note 3 V DDDR STOP mode I DDDR STOP mode Subclock oscillates 2.5 V 18 50 µA 2.5 10 µA 0.2 7.0 µA 55 110 kΩ VDDDR = 5.0 V STOP mode Subclock oscillates VDDDR = 2.7 V STOP mode Subclock stops VDDDR = 2.5 V Pull-up resistor RL VI = 0 V 25 Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0 to P95/KEY4 2. P40 to P47 3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and connect the XT1 pin to VDD. 4. P46, P47 72 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y AC Characteristics CPU and peripheral circuit operation clock (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter CPU operation clock cycle time Symbol Conditions fXX = 16 MHz tCLK VDD = AVDD = 4.0 to 5.5 V TYP. Unit 125 ns 125 ns MAX. Unit CPU function only fXX = 16 MHz fXX = 8 MHz low-frequency oscillation mode (Bit 7 of CC = 1) Peripheral operation clock cycle time fXX = 16 MHz tCLK1 fXX = 8MHz low-frequency oscillation mode (Bit 7 of CC = 1) Serial interface (1) SIOn: n = 1 or 2 (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Serial clock cycle time Serial clock high- and low-level widths Symbol tCYSK Conditions MIN. Input External clock 1.0 µs Output fCLK1/8 1.0 µs fCLK1/16 2.0 µs fCLK1/32 4.0 µs fCLK1/64 8.0 µs fCLK1/128 16 µs fCLK1/256 32 µs tWSKH Input External clock 420 ns tWSKL Output Internal clock tCYSK/2 – 50 ns SIn setup time (vs. SCKn ↑) tSSSK 100 ns SIn hold time (vs. SCKn ↑ ) tHSSK 400 ns SOn output delay time (vs. SCKn ↓ ) tDSSK 0 300 ns MIN. MAX. Unit Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz) 2. n = 1 or 2 (2) SIO2 only (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions SCK2(8) ↑→STRB ↑ tDSTRB tWSKH tCYSK Strobe high-level width tWSTRB tCYSK – 30 tCYSK + 30 BUSY setup time t SBUSY 100 ns t HBUSY 100 ns ns (vs. BUSY detection timing) BUSY hold time (vs. BUSY detection timing) BUSY inactive →SCK2(1) ↓ tLBUSY tCYSK + tWSKH Remarks 1. The value in ( ) following SCK2 indicates the number of SCK2. 2. BUSY is detected after the time of (n + 2) x tCYSK (n = 0, 1, and so on) in respect to SCK2 (8) ↑ . 3. BUSY inactive →SCK2 (1) ↓ is the value when data has been completely written to SIO2. Data Sheet U12255EJ2V0DS00 73 µPD784927, 784928, 784927Y, 784928Y I2C bus mode (µPD784928Y subseries only) Parameter Symbol Standard Mode MIN. MAX High-speed Mode MIN Unit MAX. SCL clock frequency fCLK 0 100 0 400 kHz Bus free time (between stop and start tBUF 4.7 – 1.3 – µs tHD : STA 4.0 – 0.6 – µs SCL clock low-level width tLOW 4.7 – 1.3 – µs SCL clock high-level width tHIGH 4.0 – 0.6 – µs Start/restart condition setup time tSU : STA 4.7 – 0.6 – µs Data hold CBUS compatible master tHD : DAT 5.0 – – – µs time I2 C 0Note 2 – 0Note 2 0.9Note 2 µs 250 – 100Note 4 – ns 300 ns 300 ns conditions) Hold time Note 1 bus Data setup time tSU : DAT SDA and SCL signal rise time tR – 1000 20+0.1CbNote 5 SDA and SCL signal fall time tF – 300 20+0.1CbNote 5 tSU : STO 4.0 – 0.6 – µs tSP – – 0 50 ns Cb – 400 – 400 pF Stop condition setup time Pulse width of spike restrained by input filter Each bus line capacitative load Notes 1. The first clock pulse is generated at the start condition after this period. 2. The device needs to internally supply a hold time of at least 300 ns for the SDA signal to fill the undefined area at the falling edge of the SCL (VIHmin. of the SCL signal). 3. Unless the device extends the low hold time (tLOW) of the SCL signal, it is necessary to fill only the maximum data hold time (tHD : DAT). 4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy the following conditions: • When the device does not extend the low hold time of the SCL signal tSU : DAT ≥ 250 ns • When the device extends the low hold time of the SCL signal Send the next data bit to the SDA line before releasing the SCL line (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns : in the standard mode I2C bus specification) 5. Cb: Total capacitance of one bus line (unit: pF) 74 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Other operations (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Timer input signal low-level width Symbol tWCTL Condition When DFGIN, CFGIN, DPGIN, REEL0IN, MIN. MAX. Unit tCLK1 ns tCLK1 ns or REEL1IN logic level is input Timer input signal high-level width tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input Timer input signal valid edge input cycle tPERIN When DFGIN, CFGIN, or DPGIN is input 2 µs CSYNCIN low-level width tWCR1L When digital noise rejection circuit is not used 8tCLK1 ns 108tCLK1 ns 180tCLK1 ns When digital noise rejection circuit is used (Bit 4 of INTM2 = 0) When digital noise rejection circuit is used (Bit 4 of INTM2 = 1) CSYNCIN high-level width tWCR1H When digital noise rejection circuit is not used When digital noise rejection circuit is used 8tCLK1 ns 108tCLK1 ns 180tCLK1 ns (Bit 4 of INTM2 = 0) When digital noise rejection circuit is used (Bit 4 of INTM2 = 1) Digital noise Rejected pulse width tWSEP rejection circuit Passed pulse width Bit 4 of INTM2 = 0 104tCLK1 ns Bit 4 of INTM2 = 1 176tCLK1 ns Bit 4 of INTM2 = 0 108tCLK1 ns Bit 4 of INTM2 = 1 180tCLK1 ns NMI low-level width tWNIL VDD = AVDD = 2.7 to 5.5 V 10 µs NMI high-level width tWNIH VDD = AVDD = 2.7 to 5.5 V 10 µs INTP0, INTP3 low-level widths tWIPL0 2tCLK1 ns INTP0, INTP3 high-level widths tWIPH0 2tCLK1 ns INTP1, KEY0-KEY4 low-level widths tWIPL1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP1, KEY0-KEY4 high-level widths tWIPH1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP2 low-level width tWIPL2 tWIPH2 Note µs 2tCLK1 ns 10 µs In normal mode, Sampling = fCLK 2tCLK1 ns Sampling = fCLK/128 32Note µs Normal mode, Sampling = fCLK with subclock Sampling = fCLK/128 61 µs 7.9Note ms 10 µs Sampling = fCLK 2tCLK1 ns with main clock Sampling = fCLK/128 32Note µs Normal mode, Sampling = fCLK with subclock Sampling = fCLK/128 In normal mode, In STOP mode, for releasing STOP mode RESET low-level width ns 10 with main clock In STOP mode, for releasing STOP mode INTP2 high-level width 2tCLK1 tWRSL 61 µs 7.9Note ms 10 µs 10 µs If a high or low level is successively input two times during the sampling period, a high or low level is detected. Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns) Data Sheet U12255EJ2V0DS00 75 µPD784927, 784928, 784927Y, 784928Y Clock output operation (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter MIN. MAX. Unit tCYCL nT 125 16000 ns CLO low-level width tCLL tCYCL/2 ± 25 37.5 8025 ns CLO high-level width tCLH tCYCL/2 ± 25 37.5 8025 ns CLO rise time tCLR 25 ns CLO fall time tCLF 25 ns CLO cycle time Symbol Condition Remarks 1. n: system clock division 2. T = 1/fCLK Data hold characteristics (TA = –10 to +70°C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Low-level input voltage VIL High-level input voltage VIH Note Condition Special pins (pins in Note) MIN. MAX. Unit 0 TYP. 0.1 VDDDR V 0.9 VDDDR VDDDR V RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/ KEY4 Watch function (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. MAX. Unit Subclock oscillation hold voltage VDDXT 2.7 V Hardware watch function operating voltage VDDW 2.7 V Subclock oscillation stop detection flag (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Oscillation stop detection width Symbol Condition MIN. tOSCF MAX. Unit µs 45 A/D converter characteristics (TA = –10 to +70°C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Condition Resolution MIN. TYP. Total error AVREF = VDD tCONV Sampling time t SAMP Analog input voltage V IAN Analog input impedance AV REF current 76 Unit bit Quantization error Conversion time MAX. 8 2.0 % ±1/2 LSB Bit 4 of ADM = 0 160t CLK1 µs Bit 4 of ADM = 1 80t CLK1 µs Bit 4 of ADM = 0 32t CLK1 µs Bit 4 of ADM = 1 16t CLK1 µs 0 AV REF Z AN 1000 AI REF 0.4 Data Sheet U12255EJ2V0DS00 V MΩ 1.2 mA µPD784927, 784928, 784927Y, 784928Y VREF amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Reference voltage VREF Charge current ICHG Condition Sets AMPM0.0 to 1 MIN. TYP. MAX. Unit 2.35 2.50 2.65 V µA 300 (pins in Note) Note RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN CTL amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter MIN. TYP. MAX. Unit RICTL 2 5 10 kΩ Feedback resistance RFCTL 20 50 100 kΩ Bias resistance RBCTL 20 50 100 kΩ Minimum voltage gain GCTLMIN 17 20 22 Maximum voltage gain GCTLMAX 71 75 dB 1.77 dB 50 dB High comparator set voltage of waveform shaping VPBCTLHS VREF + 0.47 VREF + 0.50 VREF + 0.53 V High comparator reset voltage of waveform shaping VPBCTLHR VREF + 0.27 VREF + 0.30 VREF + 0.33 V Low comparator set voltage of waveform shaping VPBCTLLS VREF – 0.53 VREF – 0.50 VREF – 0.47 V Low comparator reset voltage of waveform shaping VPBCTLLR VREF – 0.33 VREF – 0.30 VREF – 0.27 CTL+, – input resistance Symbol Gain selecting step SGAIN Same phase signal elimination ratio CMR Condition DC, voltage gain: 20 dB 200 250 V Comparator Schmitt width of waveform shaping VPBSH High comparator voltage of CTL flag S VFSH VREF + 1.00 VREF + 1.05 VREF + 1.10 V Low comparator voltage of CLT flag S VFSL VREF – 1.10 VREF – 1.05 VREF – 1.00 V High comparator voltage of CTL flag L VFLH VREF + 1.40 VREF + 1.45 VREF + 1.50 V Low comparator voltage of CTL flag L VFLL VREF – 1.50 VREF – 1.45 VREF – 1.40 V Data Sheet U12255EJ2V0DS00 150 dB mV 77 µPD784927, 784928, 784927Y, 784928Y CFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Voltage gain 1 GCFG1 fi = 2 kHz, open loop 50 dB Voltage gain 2 GCFG2 fi = 30 kHz, open loop 34 dB CFGAMPO High-level output current IOHCFG DC –1 mA CFGAMPO Low-level output current IOLCFG DC 0.1 mA High comparator voltage VCFGH VREF + 0.09 VREF + 0.12 VREF + 0.15 V Low comparator voltage VCFGL VREF – 0.15 VREF – 0.12 VREF – 0.09 V Duty accuracy PDUTY Note Note 49.7 50.0 50.3 % MAX. Unit The conditions include the following circuit and input signal. µ PD784927 Input signal : Sine wave input (5 mVp-p) fi = 1 kHz 1 kΩ Voltage gain: 50 dB – + 22 µ F 330 kΩ CFGIN CFGAMPO 0.01 µ F CFGCPIN DFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. GDFG Feedback resistance R FDFG Input protection resistance R IDFG 150 Ω High comparator voltage V DFGH VREF + 0.07 VREF + 0.10 VREF + 0.14 V Low comparator voltage VDFGL VREF – 0.14 VREF – 0.10 VREF – 0.07 V Caution f i = 900 Hz, open loop TYP. Voltage gain 50 160 400 640 kΩ Set the input resistance connected to the DFGIN pin to 16 kΩ or below. Connecting a resistor exceeding that value may cause the DFG amp to oscillate. 78 dB Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y DPG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol High comparator voltage VDPGH1 SELDPGHL0 = 0, SELDPGHL1 = 0 VREF + 0.02 VREF + 0.05 VREF + 0.08 V VDPGH2 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.56 VREF + 0.60 VREF + 0.64 V VDPGH3 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF – 0.44 VREF – 0.40 VREF – 0.36 V Voltage gain GDPG Low comparator voltage Caution Condition MIN. fI = 30 Hz TYP. MAX. 20 Unit dB VDPGL1 SELDPGHL0 = 0, SELDPGHL1 = 0 VREF – 0.08 VREF – 0.05 VREF – 0.02 V VDPGL2 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.36 VREF + 0.40 VREF + 0.44 V VDPGL3 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF – 0.64 VREF – 0.60 VREF – 0.56 V When both the SELDPGHL0 and SELDPGHL1 are set to 0, the DPG amplifier is not used. Therefore, be sure to set AMPC.7 (ENDPG) to 0. Ternary separation circuit (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZIPFG High comparator voltage VPFGH VREF + 0.5 VREF + 0.7 VREF + 0.9 V Low comparator voltage VPFGL VREF – 1.4 VREF – 1.2 VREF – 1.0 V CSYNC comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZICSYN High comparator voltage VCSYNH VREF + 0.07 VREF + 0.10 VREF + 0.13 V Low comparator voltage VCSYNL VREF – 0.13 VREF – 0.10 VREF – 0.07 V Reel FG comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZIRLFG High comparator voltage VRLFGH VREF + 0.02 VREF + 0.05 VREF + 0.08 V Low comparator voltage VRLFGL VREF – 0.08 VREF – 0.05 VREF – 0.02 V RECCTL driver (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition RECCTL+, – high-level output voltage VCHREC IOH = –4 mA RECCTL+, – low-level output voltage VOLREC IOL = 4 mA CTLDLY internal resistance RCTL MIN. CTLDLY charge current I OHCTL I OLCTL Use of internal resistor Data Sheet U12255EJ2V0DS00 MAX. VDD – 0.8 40 CTLDLY discharge current TYP. Unit V 70 0.8 V 140 kΩ –3 mA –3 mA 79 µPD784927, 784928, 784927Y, 784928Y Timing waveform AC timing test point 0.8 VDD or 2.2 V 0.8 VDD or 2.2 V Test point 0.8 V 0.8 V Serial transfer timing (SIOn: n = 1 or 2) tWSKL tWSKH SCKn tCYSK tSSSK SIn Input data tDSSK SOn 80 tHSSK Output data Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Serial transfer timing (SIO2 only) No busy processing tWSKL SCK2 tWSKH 7 8 9 10 1 2 10 10+n tCYSK BUSY Active high Busy invalid tDSTRB tWSTRB STRB Continuation of busy processing tWSKL SCK2 tWSKH 7 8 9 tCYSK BUSY tSBUSY tSBUSY Active high tDSTRB tWSTRB STRB End of busy processing tWSKL SCK2 tWSKH 7 8 9 10+n tCYSK BUSY Caution tHBUSY 11+n 1 tLBUSY Active high When an external clock is selected as the serial clock, do not use the busy control or strobe control. Data Sheet U12255EJ2V0DS00 81 µPD784927, 784928, 784927Y, 784928Y I2C bus mode (µPD784928Y subseries only) tLOW tR SCL tHD : DAT tHD : STA tHIGH tSU : DAT tF tSU : STA tHD : STA tSP tSU : STO SDA tBUF Stop condition 82 Start condition Restart condition Data Sheet U12255EJ2V0DS00 Stop condition µPD784927, 784928, 784927Y, 784928Y Super timer unit input timing tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input tWCTL 0.8 VDD 0.8 V tWCR1H When CSYNCIN logic level is input tWCR1L 0.8 VDD 0.8 V Interrupt request input timing tWNIH NMI tWNIL 0.8 VDD 0.8 V tWIPH0 INTP0, INTP3 tWIPL0 0.8 VDD 0.8 V tWIPH1 INTP1, KEY0-KEY4 tWIPL1 0.8 VDD 0.8 V tWIPH2 tWIPL2 0.8 VDD INTP2 0.8 V Data Sheet U12255EJ2V0DS00 83 µPD784927, 784928, 784927Y, 784928Y Reset input timing tWRSL RESET 0.8 V Clock output timing tCLH CLO 0.8 VDD 0.8 V tCLR tCLF tCLL tCYCL 84 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 7. PACKAGE DRAWING 100 PIN PLASTIC LQFP (FINE PITCH) (14×14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I M J K P M N L NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 16.00±0.20 0.630±0.008 B 14.00±0.20 0.551 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 D 16.00±0.20 0.630±0.008 F 1.00 0.039 G 1.00 0.039 H 0.22 +0.05 –0.04 0.009±0.002 I 0.08 0.003 J 0.50 (T.P.) 0.020 (T.P.) K 1.00±0.20 0.039 +0.009 –0.008 L 0.50±0.20 0.020 +0.008 –0.009 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.08 0.003 P 1.40±0.05 0.055±0.002 Q 0.10±0.05 0.004±0.002 R 3° +7° –3° 3° +7° –3° S 1.60 MAX. 0.063 MAX. S100GC-50-8EU Remark The package dimensions and materials of ES versions are the same as those of mass-production versions. Data Sheet U12255EJ2V0DS00 85 µPD784927, 784928, 784927Y, 784928Y 100PIN PLASTIC QFP (14x20) A B 51 50 80 81 detail of lead end C D S R Q 31 30 100 1 F J G H I P M K M N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 23.6±0.4 INCHES 0.929±0.016 B 20.0±0.2 0.795 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F 0.8 0.031 G 0.6 0.024 H 0.30±0.10 0.012 +0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7±0.1 0.106 +0.005 –0.004 Q 0.1±0.1 0.004±0.004 R S 5°±5° 3.0 MAX. 5°±5° 0.119 MAX. P100GF-65-3BA1-3 Remark The package dimensions and materials of ES versions are the same as those of mass-production versions. 86 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y 8. RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Caution µPD784927GC-×××-8EU, 784927YGC-×××-8EU, 784928GC-×××-8EU, and 784928YGC-×××-8EU are under development. Therefore their soldering conditions are not defined. Table 8-1. Surface Mount Type Soldering Conditions µPD784927GF-×××-3BA : 100-pin plastic QFP (14 × 20 mm) µPD784928GF-×××-3BA : 100-pin plastic QFP (14 × 20 mm) µPD784927YGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm) µPD784928YGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 secs. max. (210°C min.), Number of times: three times max. IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 secs. max. (200°C min.), VP15-00-3 Number of times: three times max. Wave soldering Solder bath temperature: 260°C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120°C max.(Package surface temperature) Partial heating Pin temperature: 300°C max., Time: three secs. max. (per device side) WS60-00-1 — Caution Do not use two or more soldering methods in combination (except partial heating). Data Sheet U12255EJ2V0DS00 87 µPD784927, 784928, 784927Y, 784928Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for developing systems using the µ PD784927. Refer to (5) Cautions when the development tools are used. (1) Language processing software RA78K4 78K/IV series common assembler package CC78K4 78K/IV series common C compiler package DF784928 Device file for the µ PD784928, 784928Y subseries CC78K4-L 78K/IV series common C compiler library source file (2) Flash memory writing tools Flashpro II, III (Part number: FL-PR2, FL-PR3, PG-FPIII) Dedicated flash programmer FA-100GC Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Be sure to connect depending on the target product. FA-100GF Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Be sure to connect depending on the target product. (3) Debugging tools • When using the IE-78K4-NS in-circuit emulator IE-78K4-NS 78K/IV series common in-circuit emulator IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter necessary when a PC-9800 series computer (except notebook personal computer) is used as host machine (C bus compatible) IE-70000-CD-IF-A PC card and interface cable necessary when a notebook personal computer is used as host machine (PCMCIA socket compatible) IE-70000-PC-IF-C Interface adapter necessary when an IBM PC/ATTM compatible machine is used as host machine (ISA bus compatible) IE-784928-NS-EM1 Emulation board for emulating the µ PD784928, 784928Y subseries EP-784915-GF-R Emulation probe for µ PD784915 subseries common 100-pin plastic QFP (GC-3BA type) and 100-pin plastic LQFP (GC-8EU type). EV-9200GF-100 Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in LCC system. NQPACK100RB Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in QFP system. ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 78K/IV series common system simulator DF784928 Device file for the µ PD784928, 784928Y subseries 88 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y • When using the IE-784000-R in-circuit emulator IE-784000-R 78K/IV series common in-circuit emulator IE-70000-98-IF-C Interface adapter necessary when a PC-9800 series computer (except notebook personal computer) is used as host machine (C bus compatible) IE-70000-PC-IF-C Interface adapter necessary when an IBM PC/AT compatible machine is used as host machine (ISA bus compatible) IE-78000-R-SV3 Interface adapter and cable necessary when an EWS is used as host machine IE-784928-NS-EM1 IE-784915-R-EM1 Emulation board for emulating the µ PD784928, 784928Y subseries and µ PD784915 subseries IE-784000-R-EM 78K/IV series common emulation board IE-78K4-R-EX3 Conversion board for 100-pin products necessary when the IE-784928-NS-EM1 is used in the IE-784000-R. Not necessary when the IE-784915-R-EM1 is used. EP-784915-GF-R Emulation probe for µ PD784915 subseries common 100-pin plastic QFP (GC-3BA type) and 100-pin plastic LQFP (GC-8EU type). EV-9200GF-100 Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in LCC system. NQPACK100RB Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in QFP system. ID78K4 Integrated debugger for IE-784000-R SM78K4 78K/IV series common system simulator DF784928 Device file for the µ PD784928, 784928Y subseries (4) Real-time OS RX78K/IV Real-time OS for 78K/IV series MX78K4 OS for 78K/IV series Data Sheet U12255EJ2V0DS00 89 µPD784927, 784928, 784927Y, 784928Y (5) Cautions when the development tools are used • The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784928. • The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784928. • FL-PR2, FL-PR3, FA-100GC, and FA-100GF are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: 044822-3813). Contact an NEC distributor when purchasing these products. • NQPACK100RB is a product of Tokyo Eletech Corp. Reference: Daimaru Kogyo, Ltd. Electronics Dept. (TEL: Tokyo 03-3820-7112) Electronics 2nd Dept. (TEL: Osaka 06-6244-6672) • Host machines and OSs compatible with the software are as follows: Host Machine [OS] PC [Windows TM ] PC-9800 Series IBM PC/AT compatible machines [Japanese/English Windows] Software RA78K4 Note CC78K4 Note ID78K4-NS EWS HP9000 series 700 TM [HP-UX TM ] SPARCstation TM [SunOS TM , Solaris TM ] NEWSTM (RISC) [NEWS-OS TM] – ID78K4 SM78K4 – RX78K/IV Note MX78K4 Note Note 90 DOS based software Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y APPENDIX B. RELATED DOCUMENTS Device-related documents Document Document No. Japanese English µ PD784928, 784928Y Subseries User’s Manual - Hardware U12648J U12648E µ PD784927, 784928, 784927Y, 784928Y Data Sheet U12255J This document µ PD784928 Subseries Special Function Register Table U12798J µ PD78F4928 Preliminary Product Information U12188J µ PD784928Y Subseries Special Function Register Table U12719J µ PD78F4928Y Preliminary Product Information U12271J U12271E µPD784915, 784928, 784928Y Subseries Application Note - VCR Servo U11361J U11361E 78K/IV Series User’s Manual - Instruction U10905J U10905E 78K/IV Series Instruction Table U10594J – 78K/IV Series Instruction Set U10595J – 78K/IV Series Application Note - Software Basics U10095J – U12188E – U10095E Development tool-related documents (User’s Manuals) Document Document No. Japanese RA78K4 Assembler Package U11334J U11334E Language U11162J U11162E U11743J U11743E RA78K4 Structured Assembler Preprocessor CC78K4 C Compiler English Operation Operation U11572J U11572E Language U11571J U11571E IE-78K4-NS U13356J U13356E IE-784000-R U12903J EEU-1534 IE-784928-NS-EM1 U13819J U13819E IE-784915-R-EM1, EP-784915GF-R U10931J U10931E SM78K4 System Simulator Windows Based Reference U10093J U10093E SM78K Series System Simulator External Part User Open U10092J Interface Specifications U10092E ID78K4-NS Integrated Debugger Reference U12796J U12796E ID78K4 Integrated Debugger Windows Based Reference U10440J U10440E ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based Reference U11960J U11960E Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system. Data Sheet U12255EJ2V0DS00 91 µPD784927, 784928, 784927Y, 784928Y Embedded software-related documents (User’s Manual) Document Document No. Japanese 78K/IV Series Real-Time OS 78K/IV Series OS, MX78K4 English Fundamental U10603J U10603E Installation U10604J U10604E Debugger U10364J – Fundamental U11779J – Other documents Document Document No. Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J English C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcomputer-Related Products by Third Party U11416J Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system. 92 – Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y [MEMO] Data Sheet U12255EJ2V0DS00 93 µPD784927, 784928, 784927Y, 784928Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EEPROM and FIP are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEW-OS are trademarks of Sony Corporation. 94 Data Sheet U12255EJ2V0DS00 µPD784927, 784928, 784927Y, 784928Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12255EJ2V0DS00 95 µPD784927, 784928, 784927Y, 784928Y The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8