DATA SHEET MOS INTEGRATED CIRCUITS µPD78F4938A 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78F4938A is a product in the µPD784938A Subseries in the 78K/IV Series. The µPD78F4938A has flash memory in place of the internal ROM of the µPD784938A. The flash memory incorporated enables program writing or erasing with the microcontroller mounted on the target board. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD784938A Subseries User’s Manual Hardware: U13570E 78K/IV Series User’s Manual Instructions: U10905E FEATURES • Pin-compatible with mask ROM version (except VPP pin) • Flash memory: 256 KB • Internal RAM: 10496 bytes 4 channels • Serial interface: • UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) • CSI (3-wire serial I/O): 2 channels • • Supply voltage: VDD = 4.0 to 5.5 V (@12.58 MHz operation) On-chip IEBusTM controller VDD = 3.0 to 5.5 V (@6.29 MHz operation) APPLICATION Car audio, etc. ORDERING INFORMATION Part Number Package Internal ROM Internal RAM µPD78F4938AGF-3BA 100-pin plastic QFP (14 × 20) 256 KB 10496 bytes The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14118EJ1V0DS00 Date Published March 2001 N CP(K) Printed in Japan © 2001 2001 1999, µPD78F4938A 78K/IV SERIES LINEUP : Products in mass-production : Products under development Supports I2C bus µ PD784038Y µ PD784038 Standard models µ PD784026 Enhanced A/D converter, 16-bit timer, and power management Enhanced internal memory capacity Pin-compatible with the µ PD784026 Supports multimaster I2C bus µ PD784225Y µ PD784225 80-pin, ROM correction added Supports multimaster I2C bus Supports multimaster I2C bus µPD784216AY µPD784218AY µ PD784216A 100-pin, enhanced I/O and internal memory capacity µ PD784218A Enhanced internal memory capacity, ROM correction added µ PD784054 µPD784046 ASSP models On-chip 10-bit A/D converter µ PD784956A For DC inverter control µ PD784908 On-chip IEBusTM controller µ PD784938A Enhanced functions of the µ PD784908, enhanced internal memory capacity, ROM correction added. µ PD784967 Enhanced functions of the µ PD784938A, enhanced I/O and internal memory capacity. Enhanced peripheral functions Supports multimaster I2C bus µ PD784928Y µPD784915 Software servo control On-chip analog circuit for VCRs Enhanced timer µ PD784928 Enhanced functions of the µ PD784915 µ PD784976A On-chip VFD controller/driver Remark Although VFD (Vacuum Florescent Display is generally used, in some documents, the display is described as FIPTM (Florescent Inidicator Panel). VFD and FIP are functionally equivalent. 2 Data Sheet U14118EJ1V0DS µPD78F4938A OVERVIEW OF FUNCTIONS (1/2) µPD78F4938A Part Number Item Number of basic instructions (mnemonics) 113 General-purpose registers 8 bits × 32 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory map) Minimum instruction execution time 320 ns/636 ns/1.27 µs/2.54 µs (@6.29 MHz operation) 160 ns/320 ns/636 ns/1.27 µs (@12.58 MHz operation) Internal memory ROM 256 KB RAM 10496 bytes Memory space I/O port 1 MB with program and data spaces combined Total 80 pins Input 8 pins I/O 72 pins Pins with LED direct drive output 24 pins ancillary Transistor direct drive 8 pins N-ch open drain drive 4 pins functionNote Real-time output port 4 bits × 2, or 8 bits × 1 IEBus controller Internal (simple version) Timer/counter Timer/event counter 0: Timer counter × 1 (16 bits) Capture register × 1 Compare register × 2 Pulse output possible • Toggle output • PWM/PPG output • One-shot pulse output Timer/event counter 1: Timer counter × 1 (16 bits) Capture register × 1 Capture/compare register × 1 Compare register × 1 Real-time output port Timer/event counter 2: Timer counter × 1 (16 bits) Capture register × 1 Capture/compare register × 1 Pulse output possible • Toggle output • PWM/PPG output Compare register × 1 Timer 3 (16 bits): Timer counter × 1 Compare register × 1 Watch timer Generates interrupt request at 0.5-second intervals (On-chip watch clock oscillator) Main clock (12.58 MHz) or watch clock (32.7 kHz) selectable as input clock Clock output Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (also usable as 1-bit output port) PWM output 12-bit resolution × 2 channels Serial interface UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) CSI (3-wire serial I/O): 2 channels A/D converter 8-bit resolution × 8 channels Watchdog timer 1 channel ROM correction function Internal (4 points of correction addresses can be set.) External expansion function Provided (up to 1 MB) Note Pins with ancillary functions are included in the I/O pins. Data Sheet U14118EJ1V0DS 3 µPD78F4938A (2/2) µPD78F4938A Part Number Item Standby Interrupt HALT/STOP/IDLE mode Hardware source 27 (internal: 20, external: 7 (sampling clock variable input: 1)) Software source BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 19, external: 6 Four programmable priority levels Three types of processing formats: Vectored interrupt/macro service/context switching 4 Supply voltage • VDD = 4.0 to 5.5 V (@12.58 MHz operation) • VDD = 3.0 to 5.5 V (@6.29 MHz operation) Package 100-pin plastic QFP (14 × 20) Data Sheet U14118EJ1V0DS µPD78F4938A CONTENTS 1. DIFFERENCES AMONG PRODUCTS IN µPD784938A SUBSERIES ................................... 6 2. PIN CONFIGURATION (TOP VIEW) ........................................................................................... 7 3. BLOCK DIAGRAM ......................................................................................................................... 9 4. PIN 4.1 4.2 4.3 FUNCTIONS ............................................................................................................................ Port Pins ................................................................................................................................. Non-Port Pins ........................................................................................................................ Pin I/O Circuits and Recommended Connection of Unused Pins ................................. 10 10 12 14 5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) .................................................. 18 6. PROGRAMMING FLASH MEMORY ............................................................................................ 6.1 Selecting Communication Mode ......................................................................................... 6.2 Flash Memory Programming Functions ............................................................................ 6.3 Connecting Flashpro III ........................................................................................................ 19 19 20 21 7. ELECTRICAL SPECIFICATIONS .................................................................................................. 22 8. PACKAGE DRAWING .................................................................................................................... 42 9. RECOMMENDED SOLDERING CONDITIONS ........................................................................... 43 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 44 APPENDIX B. RELATED DOCUMENTS ........................................................................................... 47 Data Sheet U14118EJ1V0DS 5 µPD78F4938A 1. DIFFERENCES AMONG PRODUCTS IN µPD784938A SUBSERIES The only difference between the µPD784935A, 784936A, 784937A, and 784938A is the internal memory capacity. The µPD78F4938A has a 256 KB flash memory in the place of the mask ROM of the above products. Table 11 shows the differences between these products. Table 1-1. Differences Among Products in µPD784938A Subseries Part Number µPD784935A µPD784936A µPD784937A µPD784938A µPD78F4938A Item Internal ROM 96 KB 128 KB 192 KB 256 KB Mask ROM Flash memory Internal RAM 5120 bytes Regulator Provided Electrical specifications Refer to the data sheet of each product. Internal memory size switching registerNote None Provided IC pin Provided None VPP pin None Provided Note 6656 bytes 8192 bytes 10496 bytes None The internal flash memory capacity and internal RAM capacity can be changed by using the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. 6 Data Sheet U14118EJ1V0DS µPD78F4938A 2. PIN CONFIGURATION (TOP VIEW) • 100-pin plastic QFP (14 × 20) P77/ANI7 AVDD AVREF1 AVSS RX TX P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 P26/INTP5 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0 P33/SO0 P27/SI0 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VPP PWM1 PWM0 P17 P16 P15 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11 P10 ASTB/CLKOUT P90 P91 P92 P93 P94 P95 P96 P97 P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 VDD VSS P54/A12 P55/A13 P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P64/RD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P63/A19 P36/T02 P37/T03 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET XT2 XT1 VSS X2 X1 REGOFF REGC VDD P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR P34/TO0 P35/TO1 µPD78F4938AGF-3BA Cautions 1. In normal operation mode, connect VPP pin directly to the VSS pin, or pull it down. In a system where the internal flash memory is rewritten while mounted on board, pull the VPP pin down. When pulling down, connection via a 470 Ω or higher and 10 kΩ or lower resistor is recommended. 2. Connect the AVDD pin directly to VDD. 3. Connect the AVSS pin directly to VSS. Data Sheet U14118EJ1V0DS 7 µPD78F4938A A8 to A19: Address bus PWM0, PWM1: Pulse width modulation output AD0 to AD7: Address/data bus RD: Read strobe ANI0 to ANI7: Analog input REFRQ: Refresh request ASCK, ASCK2: Asynchronous serial clock REGC: Regulator capacitance ASTB: Address strobe REGOFF: Regulator off AVDD: Analog power supply RESET: Reset AVREF1: Reference voltage RX: IEBus receive data AVSS: Analog ground RxD, RxD2: Receive data CI: Clock input SCK0 to SCK3: Serial clock CLKOUT: Clock output SI0 to SI3: Serial input HLDAK: Hold acknowledge SO0 to SO3: Serial output HLDRQ: Hold request TO0 to TO3: Timer output INTP0 to INTP5: Interrupt from peripherals TX: IEBus transmit data NMI: Non-maskable interrupt TxD, TxD2: Transmit data P00 to P07: Port 0 VDD: Power supply P10 to P17: Port 1 VPP: Programming power supply P20 to P27: Port 2 VSS: Ground P30 to P37: Port 3 WAIT: Wait P40 to P47: Port 4 WR: Write strobe P50 to P57: Port 5 X1, X2: Crystal (main system clock) P60 to P67: Port 6 XT1, XT2: Crystal (watch) P70 to P77: Port 7 P90 to P97: Port 9 P100 to P107: Port 10 8 Data Sheet U14118EJ1V0DS µPD78F4938A 3. BLOCK DIAGRAM NMI INTP0 to INTP5 UART/IOE 2 Programmable interrupt controller INTP3 TO0 TO1 Timer/counter 0 (16 bits) INTP0 Timer/counter 1 (16 bits) Baud-rate generator UART/IOE 1 Baud-rate generator Timer/counter 2 (16 bits) 78K/IV CPU core Flash memory PWM0 Real-time output port PWM ASCK2/SCK2 SO0 SI0 SO3 SI3 Clock output P04 to P07 RxD2/SI2 TxD2/SO2 SCK3 Clocked serial interface 3 Timer 3 (16 bits) P00 to P03 ASCK/SCK1 SCK0 Clocked serial interface INTP1 INTP2/CI TO2 TO3 RxD/SI1 TxD/SO1 ASTB/CLKOUT AD0 to AD7 A8 to A15 Bus I/F A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK Port 0 P00 to P07 Port 1 P10 to P17 Port 2 P20 to P27 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P67 Port 7 P70 to P77 Port 9 P90 to P97 Port 10 P100 to P107 RAM PWM1 ANI0 to ANI7 AVDD AVREF1 A/D converter AVSS INTP5 TX IEBus controller RX RESET VPP X1 X2 REGC REGOFF VDD VSS System control (regulator) Watchdog timer XT1 Watch timer XT2 Data Sheet U14118EJ1V0DS 9 µPD78F4938A 4. PIN FUNCTIONS 4.1 Port Pins (1/2) Pin Name I/O Alternate Function P00 to P07 I/O — Port 0 (P0): • 8-bit I/O port. • Can be used as real-time output port (4 bits × 2). • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. • Can drive transistor. P10 I/O — Port 1 (P1): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. • Can drive LED. P11 — P12 ASCK2/SCK2 P13 RxD2/SI2 P14 TxD2/SO2 P15 to 17 P20 — Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0 P30 Function I/O RxD/SI1 P31 TxD/SO1 P32 SCK0 P33 SO0 P34 to P37 TO0 to TO3 Port 2 (P2): • 8-bit input port. • P20 cannot be used as general-purpose port pin (non-maskable interrupt). However, input level can be checked by interrupt routine. • An on-chip pull-up resistor can be specified for P22 to P27 by means of software in 6-bit units. • P25/INTP4/ASCK/SCK1 pin operates as SCK1 I/O pin if so specified by CSIM1. Port 3 (P3): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. • P32 and P33 can be specified for N-ch open-drain connection. P40 to P47 I/O AD0 to AD7 Port 4 (P4): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. • Can drive LED. P50 to P57 I/O A8 to A15 Port 5 (P5): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. • Can drive LED. P60 to P63 I/O A16 to A19 Port 6 (P6): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. P64 RD P65 WR P66 WAIT/HLDRQ P67 REFRQ/HLDAK 10 Data Sheet U14118EJ1V0DS µPD78F4938A 4.1 Port Pins (2/2) Pin Name I/O Alternate Function P70 to P77 I/O ANI0 to ANI7 P90 to P97 I/O — Port 9 (P9): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. P100 to P104 I/O — Port 10 (P10): • 8-bit I/O port. P105 SCK3 P106 SI3 P107 SO3 Function Port 7 (P7): • 8-bit I/O port. • Input/output can be specified in 1-bit units. • Input/output can be specified in 1-bit units. • An on-chip pull-up resistor can be specified by means of software for pins in input mode. • P105 and P107 can be specified for N-ch open-drain connection. Data Sheet U14118EJ1V0DS 11 µPD78F4938A 4.2 Non-Port Pins (1/2) Pin Name I/O TO0 to TO3 Output P34 to P37 Timer output CI Input P23/INTP2 Count clock input to timer/counter 2 RxD Input P30/SI1 Serial data input (UART0) P13/SI2 Serial data input (UART2) P31/SO1 Serial data output (UART0) P14/SO2 Serial data output (UART2) Input P25/INTP4/SCK1 Baud rate clock input (UART0) P12/SCK2 Baud rate clock input (UART2) Input P27 Serial data input (3-wire serial I/O0) SI1 P30/RxD Serial data input (3-wire serial I/O1) SI2 P13/RxD2 Serial data input (3-wire serial I/O2) P106 Serial data input (3-wire serial I/O3) P33 Serial data output (3-wire serial I/O0) SO1 P31/TxD Serial data output (3-wire serial I/O1) SO2 P14/TxD2 Serial data output (3-wire serial I/O2) RxD2 TxD Output TxD2 ASCK ASCK2 SI0 SI3 SO0 Output SO3 Alternate Function Function P107 Serial data output (3-wire serial I/O3) P32 Serial clock input/output (3-wire serial I/O0) SCK1 P25/INTP4/ASCK Serial clock input/output (3-wire serial I/O1) SCK2 P12/ASCK2 Serial clock input/output (3-wire serial I/O2) SCK0 I/O SCK3 NMI Input INTP0 P105 Serial clock input/output (3-wire serial I/O3) P20 External interrupt requests P21 — • Count clock input to timer/counter 1 • Capture trigger signal of CR11 or CR12 INTP1 P22 • Count clock input to timer/counter 2 • Capture trigger signal of CR22 INTP2 P23/CI • Count clock input to timer/counter 2 • Capture trigger signal of CR21 INTP3 P24 • Count clock input to timer/counter 0 • Capture trigger signal of CR02 INTP4 P25/ASCK/SCK1 INTP5 P26 AD0 to AD7 — Conversion start trigger input of A/D converter I/O P40 to P47 Time-division address/data bus (external memory connection) A8 to A15 Output P50 to P57 Higher address bus (external memory connection) A16 to A19 Output P60 to P63 Higher address for address extension (external memory connection) RD Output P64 Read strobe to external memory WR Output P65 Write strobe to external memory Input P66/HLDRQ Wait insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo-static memory HLDRQ Input P66/WAIT Bus hold request input WAIT HLDAK Output P67/REFRQ Bus hold acknowledge output ASTB Output CLKOUT Latch timing output of time-division address (A0 to A7) (when external memory is accessed) 12 Data Sheet U14118EJ1V0DS µPD78F4938A 4.2 Non-Port Pins (2/2) Pin Name I/O CLKOUT Output PWM0 Output PWM1 Alternate Function ASTB Function Clock output — PWM output 0 Output — PWM output 1 RX Input — Data input (IEBus) TX Output — Data output (IEBus) — — Connecting capacitor for regulation output stabilization/power supply when REGC regulator is stopped REGOFF — — Regulator operation specification signal RESET Input — Chip reset X1 Input — Connecting crystal resonator for system clock oscillation (clock can be also X2 — input to X1.) XT1 Input — XT2 — — ANI0 to ANI7 AVREF1 Input — P70 to P77 — Watch clock connection Analog voltage input for A/D converter Application of reference voltage for A/D converter AVDD Positive power supply for A/D converter AVSS GND for A/D converter VDD Positive power supply VSS GND VPP Input Sets flash memory programming mode. For high voltage application when program is written or verified. In normal operation mode, connect VPP pin directly to the VSS pin, or pull it down. In a system where the internal flash memory is rewritten while mounted on board, pull the VPP pin down. When pulling down, connection via a 470 Ω or higher and 10 kΩ or lower resistor is recommended. Data Sheet U14118EJ1V0DS 13 µPD78F4938A 4.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 4-1. For the I/O circuit configuration of each type, refer to Figure 4-1. Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) Pin Name P00 to P07 I/O Circuit Type 5-A I/O I/O P10, P11 Recommended Connection of Unused Pins Input: Connect to VDD. Output: Leave open. P12/ASCK2/SCK2 8-A P13/RxD2/SI2 5-A P14/TxD2/SO2 P15 to P17 P20/NMI 2 Input Connect to VDD or VSS. P21/INTP0 P22/INTP1 2-A Connect to VDD. P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input: Connect to VDD. Output: Leave open. P26/INTP5 2-A Input 5-A I/O Connect to VDD. P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0 Input: Connect to VDD. Output: Leave open. 10-A P33/SO0 P34/TO0 to P37/TO3 5-A P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 20 P90 to P97 5-A I/O Input: Connect to VDD or VSS. Output: Leave open. P100 to P104 P105/SCK3 10-A P106/SI3 8-A P107/SO3 10-A ASTB/CLKOUT 4 Output RESET 2 Input VPP 1 XT2 — — XT1 — Input 14 Leave open. — Connect directly to VSS. Leave open. Connect directly to VSS. Data Sheet U14118EJ1V0DS µPD78F4938A Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2) Pin Name REGOFF I/O Circuit Type 1 REGC — I/O — Connect directly to VDD. — Connect to VDD. PWM0, PWM1 3 Output RX 1 Input TX 3 Output AVREF1 — Recommended Connection of Unused Pins — Leave open. Connect to VDD or VSS. Leave open. Connect to VSS. AVSS AVDD Connect to VDD. Caution Connect an I/O pin to VDD via a resistor of several 10 kΩ if the I/O mode of the pin is unstable (especially if the voltage on the reset pin is higher than the low-level input voltage on power application or if the mode is changed between input and output by software). Remark The circuit type numbers are common for the 78K Series and are not always sequential for one product (some circuits are not provided). Data Sheet U14118EJ1V0DS 15 µPD78F4938A Figure 4-1. Pin I/O Circuits (1/2) Type 1 Type 4 VDD VDD Data P OUT P Output disable IN N N Push-pull output that can go into a high-impedance state (both P-ch and N-ch are off). Type 2 Type 5-A Pull-up enable VDD P VDD Data P IN IN/OUT Output disable Schmitt-triggered input with hysteresis characteristics Type 2-A N Input enable Type 8-A VDD VDD Pull-up enable Pull-up enable P P VDD Data P IN/OUT Output disable IN N Schmitt-triggered input with hysteresis characteristics Type 3 Type 10-A VDD Pull-up enable VDD P VDD Data P-ch Data OUT N-ch 16 P IN/OUT Open-drain Output disable Data Sheet U14118EJ1V0DS N µPD78F4938A Figure 4-1. Pin I/O Circuits (2/2) Type 20 VDD Data P IN/OUT Output disable N Comparator + – P N VREF (threshold voltage) Input enable Data Sheet U14118EJ1V0DS 17 µPD78F4938A 5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) IMS is a register to prevent a certain part of the internal memory from being used by software. By setting the IMS, it is possible to establish a memory map that is the same as that of mask ROM version with a different internal memory (ROM, RAM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to FFH. Figure 5-1. Internal Memory Size Switching Register (IMS) Format Address Symbol IMS 0FFFCH After reset FFH W 7 6 5 4 3 2 1 0 1 1 ROM1 ROM0 1 1 RAM1 RAM0 ROM1 ROM0 0 0 256 KB 0 1 96 KB 1 0 128 KB 1 1 192 KB RAM1 RAM0 0 0 10496 bytes 0 1 5120 bytes 1 0 6656 bytes 1 1 8192 bytes Internal ROM Capacity Selection Internal RAM Capacity Selection Caution IMS is not available for mask ROM versions (µPD784935A, 784936A, 784937A, and 784938A). The IMS settings to create the same memory map as mask ROM versions are shown in Table 5-1. Table 5-1. Internal Memory Size Switching Register (IMS) Settings Relevant Mask ROM Version Note IMS Setting µPD784935A DDH µPD784936A EEH µPD784937A FFH µPD784938A CCH Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. Therefore, if the external devices do not acknowledge the port state immediately after reset, handling such as connecting to VDD via a resistor or connecting to VSS via a resistor is required. 18 Data Sheet U14118EJ1V0DS µPD78F4938A 6. PROGRAMMING FLASH MEMORY Flash memory can be written while mounted on the target system (on-board writing). Connect the dedicated flash programmer (Flashpro III (part No.: FL-PR3, PG-FP3)) to the host machine and target system for programming. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 6.1 Selecting Communication Mode The Flashpro III is used to write data into a flash memory by serial communications. Select the communication mode for writing from Table 6-1. Figure 6-1 shows the format used to select the communication mode. Each communication mode is selected with the number of VPP pulses shown in Table 6-1. Table 6-1. Communication Mode Communication Mode Number of Channels 3-wire serial I/O 3 UART Pins Used 1 Number of VPP Pulses SCK3/P105 SI3/P106 SO3/P107 1 SCK0/P32 SI0/P27 SO0/P33 0 SCK3/P105 SI3/P106 SO3/P107 P104 (for handshake) 3 RxD/P30 TxD/P31 8 Caution Always select the communication mode using the number of VPP pulses shown in Table 6-1. Figure 6-1. Communication Mode Selection Format VPP pulses 10 V VPP VDD VSS 1 2 n VDD RESET VSS Flash memory write mode Data Sheet U14118EJ1V0DS 19 µPD78F4938A 6.2 Flash Memory Programming Functions By transmitting and receiving various commands and data by the selected communication mode, operations such as writing to the flash memory are performed. Table 6-2 shows the major functions. Table 6-2. Flash Memory Programming Functions Function Description Area erase Erase the contents of the specified memory area where one memory block is 16 KB. Area blank check Checks the erase state of the specified area. Data write Writes to the flash memory based on the start write address and the number of data written (number of bytes). Area verify Compares the data input with the contents of the specified memory area. Verification for the flash memory entails supplying the data to be verified from an external source via a serial interface, and then outputting the existence of unmatched data to the external source after referencing the areas or all of the data. Consequently, the flash memory is not equipped with a read function, and it is not possible for third parties to read the contents of the flash memory with the use of the verification function. 20 Data Sheet U14118EJ1V0DS µPD78F4938A 6.3 Connecting Flashpro III The connection between the Flashpro III and the µPD78F4938A differs depending on the communication mode (3-wire serial I/O or UART). Figures 6-2 and 6-3 are the connection diagrams in each case. Figure 6-2. Flashpro III Connection in 3-Wire Serial I/O Mode µ PD78F4938A Flashpro III VPP VPP VDD VDD RESET RESET SCK Note SCK SO SI SI SO HS P104Note VSS VSS Only in the handshake communication Figure 6-3. Flashpro III Connection in UART Mode µPD78F4938A Flashpro III VPP VPP VDD VDD RESET RESET SO RxD SI TxD VSS VSS Data Sheet U14118EJ1V0DS 21 µPD78F4938A 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Ratings Unit VDD –0.3 to +6.5 V AVDD –0.3 to VDD + 0.3 V AVSS –0.3 to VSS + 0.3 V –0.3 to VDD + 0.3 V –0.3 to +10.5 V AVSS – 0.3 to AVREF1 + 0.3 V –0.3 to VDD + 0.3 V Per pin 10 mA Total for all pins of ports 0, 3, 6, 10 and P54 to P57 50 mA Total for all pins of ports 1, 4, 7, 9, P50 to P53, PWM0, PWM1, and TX pins 50 mA Per pin –6 mA Total for all pins of ports 0, 3, 6, 10,and –30 mA –30 mA AVREF1 Input voltage VI2 Analog input voltage VIAN Output voltage VO Output current, low IOL Output current, high IOH Conditions A/D converter reference voltage input Analog input voltage P54 to P57 Total for all pins of ports 1, 4, 7, 9, P50 to P53, PWM0, PWM1, and TX pins Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –40 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 22 Data Sheet U14118EJ1V0DS µPD78F4938A Operating Conditions • Clock frequency Clock Frequency Supply Voltage 4 MHz ≤ fXX ≤ 12.58 MHz 4.0 ≤ VDD ≤ 5.5 V 4 MHz ≤ fXX ≤ 6.29 MHz 3.0 ≤ VDD ≤ 5.5 V • Operating ambient temperature (TA): –40 to +85°C • Power supply voltage and clock cycle time: Refer to Figure 7-1 • Selection of internal regulator operation (REGOFF pin: low-level input) Figure 7-1. Power Supply Voltage and Clock Cycle Time 10000 Clock cycle time tCYK [ns] 2000 1/8 of fXX = 2 MHz 1000 Guaranteed operation range 500 200 fXX = 6.29 MHz undivided 159 100 fXX = 12.58 MHz undivided 79 0 0 1 2 3 4 5 6 Power supply voltage [V] Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT Conditions MAX. Unit f = 1 MHz 15 pF Unmeasured pins returned to 0 V. 15 pF 15 pF CIO Data Sheet U14118EJ1V0DS MIN. TYP. 23 µPD78F4938A Main Oscillator Characteristics (TA = –40 to +85°C, VDD = 3.0 to 5.5 V, VSS = 0 V) Parameter Oscillator frequency Symbol fXX Conditions MIN. MAX. Unit Ceramic resonator or 4.0 ≤ VDD ≤ 5.5 V 4.0 12.58 MHz recommended resonator 3.0 ≤ VDD ≤ 5.5 V 4.0 6.29 MHz Caution When using the main clock oscillator, wire as follows to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Remarks 1. Connect a 12.582912 MHz or 6.291456 MHz oscillator to operate the internal clock timer with the main clock. 2. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 3.0 to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Oscillator frequency fXT Ceramic resonator or crystal resonator Oscillation stabilization time fsxt 4.5 ≤ VDD ≤ 5.5 V MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s 10 s Oscillation hold voltage VDDXT 3.0 5.5 V Watch timer operating voltage VDDW 3.0 5.5 V 24 Data Sheet U14118EJ1V0DS µPD78F4938A DC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (1/2) Parameter Input voltage, lowNote Input voltage, high Output voltage, low Output voltage, high Input leakage current, low Symbol Conditions TYP. MAX. Unit VIL1 P10, P11, P13 to P17, P30, P31, P34 to P37, P70 to P77, P90 to P97, P100 to P104, X1, X2, XT1, XT2 –0.3 0.3VDD V VIL2 P12, P20 to P27, P32, P33, P105 to P107 RESET –0.3 0.2VDD V VIL3 P00 to P07, P40 to P47, 4.5 ≤ VDD ≤ 5.5 V –0.3 0.8 V VIL4 P50 to P57, P60 to P67 –0.3 0.2VDD V VIH1 P10, P11, P13 to P17, P30, P31, P34 to P37, P70 to P77, P90 to P97, P100 to P104, X1, X2, XT1, XT2 0.7VDD VDD+0.3 V VIH2 P12, P20 to P27, P32, P33, P105 to P107 RESET 0.8VDD VDD+0.3 V VIH3 P00 to P07, P40 to P47, 4.5 ≤ VDD ≤ 5.5 V 2.2 VDD+0.3 V VIH4 P50 to P57, P60 to P67 0.7VDD 0.3VDD V VOL1 IOL = 20 µA 0.1 V IOL = 100 µA 0.2 V IOL = 2 mA 0.4 V VOL2 IOL = 8 mA, P10 to P17, 4.5 ≤ VDD ≤ 5.5 V P40 to P47, P50 to P57 1.0 V VOH1 IOH = –20 µA VDD–0.1 V IOL = –100 µA VDD–0.2 V IOL = –2 mA VDD–1.0 V VOH2 IOL = –5 mA, 4.5 V ≤ VDD ≤ 5.5 V VDD–2.4 P10 to P17, P40 to P47, P50 to P57 V ILIL1 VIN = 0 V ILIL2 Input leakage current, high MIN. ILIH1 VIN = VDD ILIH2 10 µA X1, X2, XT1, XT2 –20 µA For pins other than X1, X2, XT1, and XT2 10 µA X1, X2, XT1, XT2 20 µA For pins other than X1, X2, XT1, and XT2 Output leakage current, low ILOL1 VOUT = 0 V –10 µA Output leakage current, high ILOH1 VOUT = VDD 10 µA Note These values are valid when the pull-up resistor is off. Data Sheet U14118EJ1V0DS 25 µPD78F4938A DC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (2/2) Parameter Power supply current Symbol IDD1 IDD2 IDD3 Conditions Operating mode HALT mode IDLE mode Data hold voltage VDDDR STOP mode Data hold current IDDDR STOP mode Pull-up resistor Note RL MIN. TYP. MAX. Unit fXX = 12.58 MHz, 4.0 V ≤ VDD ≤ 5.5 V 19 38 mA fXX = 6.29 MHz, 3.0 V ≤ VDD ≤ 5.5 V 10 20 mA fXX = 12.58 MHz, when peripheral clock stopsNote, 4.0 V ≤ VDD ≤ 5.5 V 3 6 mA fXX = 6.29 MHz, when peripheral clock stopsNote, 3.0 V ≤ VDD ≤ 5.5 V 1.8 3.6 mA fXX = 12.58 MHz, 4.0 ≤ VDD ≤ 5.5 V 2 4 mA fXX = 6.29 MHz, 3.0 V ≤ VDD ≤ 5.5 V 1 2 mA 5.5 V 2.5 VDD = 2.5 V, subsystem clock stops 4 20 µA VDD = 5.5 V, subsystem clock stops 20 100 µA 40 80 kΩ VIN = 0 V 15 When the main system clock: fCLK = fXX/8 is selected (set by the standby control register (STBC)) and the watch timer is operating. Remark These values are valid when the internal regulator is on (REGOFF pin = low-level input). 26 Data Sheet U14118EJ1V0DS µPD78F4938A AC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2) Parameter Cycle time Address setup time Symbol tCYK tSAST (to ASTB↓) Address hold time tHSTLA (from ASTB↓) ASTB high-level width Address hold time (from RD↑) Delay time from address to tWSTH tHRA tDAR RD↓ Address float time (from RD↓) tFAR Data input time from address tDAID Data input time from ASTB↓ Data input time from RD↓ Delay time from ASTB ↓ to tDSTID tDRID tDSTR RD↓ Data hold time (from RD↑) tHRID Address active time from RD↑ tDRA Delay time from RD↑ to tDRST ASTB↑ RD low-level width tWRL Conditions MIN. TYP. MAX. Unit 4.0 ≤ VDD ≤ 5.5 V 79 ns VDD = 3.0 V 159 ns VDD = 5.0 V (0.5+a) T–11 ns VDD = 3.0 V (0.5+a) T–15 ns VDD = 5.0 V 0.5T–19 ns VDD = 3.0 V 0.5T–24 ns VDD = 5.0 V (0.5+a) T–17 ns VDD = 3.0 V (0.5+a) T–40 ns VDD = 5.0 V 0.5T–14 ns VDD = 3.0 V 0.5T–14 ns VDD = 5.0 V (1+a) T–5 ns VDD = 3.0 V (1+a) T–10 ns 0 ns VDD = 5.0 V (2.5+a+n) T–37 ns VDD = 3.0 V (2.5+a+n) T–52 ns VDD = 5.0 V (2+n) T–35 ns VDD = 3.0 V (2+n) T–50 ns VDD = 5.0 V (1.5+n) T–40 ns VDD = 3.0 V (1.5+n) T–50 ns VDD = 5.0 V 0.5T–9 ns VDD = 3.0 V 0.5T–9 ns 0 ns VDD = 5.0 V 0.5T–2 ns VDD = 3.0 V 0.5T–12 ns VDD = 5.0 V 0.5T–9 ns VDD = 3.0 V 0.5T–9 ns VDD = 5.0 V (1.5+n) T–25 ns VDD = 3.0 V (1.5+n) T–30 ns Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n ≥ 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V Data Sheet U14118EJ1V0DS 27 µPD78F4938A AC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (2/2) Parameter Delay time from address to Symbol tDAW WR↓ Address hold time (from WR↑) Delay time from ASTB ↓ to tHWA tDSTOD data output Data output time from WR↓ tDWOD Delay time from ASTB ↓ to tDSTW WR↓ Data setup time (to WR↑) Data hold time (from WR↑) Delay time from WR ↑ to tSODWR tHWOD tDWST ASTB↑ WR low-level width tWWL Conditions MIN. MAX. Unit VDD = 5.0 V (1+a) T–5 ns VDD = 3.0 V (1+a) T–10 ns VDD = 5.0 V 0.5T–14 ns VDD = 3.0 V 0.5T–14 ns VDD = 5.0 V 0.5T+15 ns VDD = 3.0 V 0.5T+20 ns 15 ns VDD = 5.0 V 0.5T–9 ns VDD = 3.0 V 0.5T–9 ns VDD = 5.0 V (1.5+n) T–20 ns VDD = 3.0 V (1.5+n) T–25 ns VDD = 5.0 V 0.5T–14 ns VDD = 3.0 V 0.5T–14 ns VDD = 5.0 V 0.5T–9 ns VDD = 3.0 V 0.5T–9 ns VDD = 5.0 V (1.5+n) T–25 ns VDD = 3.0 V (1.5+n) T–30 ns Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n ≥ 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V 28 TYP. Data Sheet U14118EJ1V0DS µPD78F4938A AC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (2) External wait timing Parameter WAIT↓ input time from Symbol tDAWT address WAIT↓ input time from ASTB↓ WAIT hold time from ASTB ↓ Delay time from ASTB↓ to tDSTWT tHSTWTH tDSTWTH WAIT↑ WAIT↓ input time from RD↓ WAIT hold time from RD↓ Delay time from RD↓ to tDRWTL tHRWT tDRWTH WAIT↑ Data input time from WAIT↑ Delay time from WAIT↑ to tDWTID tDWTR RD↑ Delay time from WAIT↑ to tDWTW WR↑ WAIT↓ input time from WR↓ WAIT hold time from WR↓ Delay time from WR↓ to WAIT↑ tDWWTL tHWWT tDWWTH Conditions MIN. TYP. MAX. Unit VDD = 5.0 V (2+a) T–40 ns VDD = 3.0 V (2+a) T–60 ns VDD = 5.0 V 1.5T–40 ns VDD = 3.0 V 1.5T–60 ns VDD = 5.0 V (0.5+n) T+5 ns VDD = 3.0 V (0.5+n) T+10 ns VDD = 5.0 V (1.5+a) T–40 ns VDD = 3.0 V (1.5+a) T–60 ns VDD = 5.0 V T–40 ns VDD = 3.0 V T–60 ns VDD = 5.0 V nT+5 ns VDD = 3.0 V nT+10 ns VDD = 5.0 V (1+n) T–40 ns VDD = 3.0 V (1+n) T–60 ns VDD = 5.0 V 0.5T–5 ns VDD = 3.0 V 0.5T–10 ns VDD = 5.0 V 0.5T ns VDD = 3.0 V 0.5T ns VDD = 5.0 V 0.5T ns VDD = 3.0 V 0.5T ns VDD = 5.0 V T–40 ns VDD = 3.0 V T–60 ns VDD = 5.0 V nT+5 ns VDD = 3.0 V nT+10 ns VDD = 5.0 V (1+n) T–40 ns VDD = 3.0 V (1+n) T–60 ns Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n ≥ 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V Data Sheet U14118EJ1V0DS 29 µPD78F4938A AC Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (3) Bus hold/refresh timing Parameter Delay time from HLDRQ↑ Symbol tFHQC to float Delay time from HLDRQ↑ to tDHQHHAH HLDAK↑ Delay time from float to tDCFHA HLDAK↑ Delay time from HLDRQ↓ to tDHQLHAL HLDAK↓ Delay time from HLDAK↓ to tDHAC active Random read/write cycle time REFRQ low-level pulse width Delay time from ASTB↓ to tRC tWRFQL tDSTRFQ REFRQ Delay time from RD↑ to tDRRFQ REFRQ Delay time from WR↑ to tDWRFQ REFRQ Delay time from REFRQ↑ to tDRFQST ASTB REFRQ high-level pulse width tWRFQH Conditions MIN. MAX. Unit VDD = 5.0 V (2+4+a+n) T+50 ns VDD = 3.0 V (2+4+a+n) T+50 ns VDD = 5.0 V (3+4+a+n) T+30 ns VDD = 3.0 V (3+4+a+n) T+40 ns VDD = 5.0 V T+30 ns VDD = 3.0 V T+30 ns VDD = 5.0 V 2T+40 ns VDD = 3.0 V 2T+60 ns VDD = 5.0 V T–20 ns VDD = 3.0 V T–30 ns VDD = 5.0 V 3T ns VDD = 3.0 V 3T ns VDD = 5.0 V 1.5T–25 ns VDD = 3.0 V 1.5T–30 ns VDD = 5.0 V 0.5T–9 ns VDD = 3.0 V 0.5T–9 ns VDD = 5.0 V 1.5T–9 ns VDD = 3.0 V 1.5T–9 ns VDD = 5.0 V 1.5T–9 ns VDD = 3.0 V 1.5T–9 ns VDD = 5.0 V 0.5T–9 ns VDD = 3.0 V 0.5T–9 ns VDD = 5.0 V 1.5T–25 ns VDD = 3.0 V 1.5T–30 ns Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n ≥ 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V 30 TYP. Data Sheet U14118EJ1V0DS µPD78F4938A Timing Waveform (1) Read operation tWSTH ASTB tSAST tDRST tDSTID tHSTLA A8 to A19 tDAID tHRA AD0 to AD7 tDSTR tFRA tDAR tHRID tDRID tDRA RD tWRL (2) Write operation tWSTH ASTB tSAST tDWST tDSTOD tHSTLA A8 to A19 tHWA AD0 to AD7 tDSTW tDAW tHWOD tDWOD tSODWR WR tWWL Data Sheet U14118EJ1V0DS 31 µPD78F4938A Hold Timing ASTB, A8 to A19, AD0 to AD7, RD, WR tFHQC tDCFHA tDHAC HLDRQ tDHQLHAL tDHQHHAH HLDAK External Wait Signal Input Timing (1) Read operation ASTB tDSTWT tDSTWTH tHSTWTH A8 to A19 AD0 to AD7 tDAWT tDWTID RD tDWTR tDRWTL WAIT tHRWT tDRWTH (2) Write operation ASTB tDSTWT tDSTWTH tHSTWTH A8 to A19 AD0 to AD7 tDAWT WR tDWTW tDWWTL WAIT tHWWT tDWWTH 32 Data Sheet U14118EJ1V0DS µPD78F4938A Refresh Timing Waveform (1) Random read/write cycle tRC ASTB WR tRC tRC tRC tRC RD (2) When refresh memory is accessed for a read and write at the same time ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after a read ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after a write ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL Data Sheet U14118EJ1V0DS 33 µPD78F4938A Serial Operation (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (a) CSI0, CSI3 3-wire serial I/O mode (SCK0, SCK3 ... External clock input) Parameter Symbol Conditions MIN. MAX. Unit SCK cycle time tCYSK0, SO0 and SO3 are fCLK = fXX 8/fXX ns (SCK0, SCK3) tCYSK3 CMOS outputs Except fCLK = fXX 4/fCLK ns SCK low-level width tWSKL0, SO0 and SO3 are fCLK = fXX 4/fXX – 40 ns (SCK0, SCK3) tWSKL3 CMOS outputs Except fCLK = fXX 2/fCLK – 40 ns SCK high-level width tWSKH0, SO0 and SO3 are fCLK = fXX 4/fXX – 40 ns (SCK0, SCK3) tWSKH3 CMOS outputs Except fCLK = fXX 2/fCLK – 40 ns SI0, SI3 setup time (to SCK0, SCK3↑) tSSSK0, tSSSK3 80 ns SI0, SI3 hold time (from SCK0, SCK3↑) tHSSK0, tHSSK3 1/fCLK + 80 ns Delay time from SCK0, tDBSK0, CMOS output 0 1/fCLK + 150 ns SCK3↓ to output tDBSK3 N-ch open-drain output (RL = 1 kΩ) 0 1/fCLK + 400 ns SO0, SO3 output hold time (from SCK0, SCK3↑) tHSBSK0, tHSBSK3 When data is transferred 0.5tCYSK0 – 40, 0.5tCYSK3 – 40 ns Remarks 1. The values in this table are those when CL = 100 pF. 2. fXX: External oscillator frequency (fXX = 12.58 MHz or fXX = 6.29 MHz) 3. fCLK: System clock oscillation frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) (b) CSI0, CSI3 3-wire serial I/O mode (SCK0, SCK3 ... Internal clock output) Parameter Symbol Conditions MIN. MAX. SCK cycle time tCYSK0, SO0 and SO3 are Except fCLK = fXX/8 (SCK0, SCK3) tCYSK3 CMOS outputs fCLK = fXX/8 16/fXX ns SCK low-level width tWSKL0, SO0 and SO3 are Except fCLK = fXX/8 4/fXX – 40 ns (SCK0, SCK3) tWSKL3 CMOS outputs fCLK = fXX/8 8/fXX – 40 ns SCK high-level width tWSKH0, SO0 and SO3 are Except fCLK = fXX/8 4/fXX – 40 ns (SCK0, SCK3) tWSKH3 CMOS outputs fCLK = fXX/8 8/fXX – 40 ns SI0, SI3 setup time (to SCK0, SCK3↑) tSSSK0, tSSSK3 80 ns SI0, SI3 hold time (from SCK0, SCK3↑) tHSSK0, tHSSK3 80 ns Delay time from SCK0, tDBSK0, CMOS output 0 150 ns SCK3↓ to output tDBSK3 N-ch open-drain output (RL = 1 kΩ) 0 400 ns SO0, SO3 output hold time (from SCK0, SCK3↑) tHSBSK0, tHSBSK3 When data is transferred 8/fXX Unit 0.5tCYSK0 – 40, 0.5tCYSK3 – 40 ns ns Remarks 1. The values in this table are those when CL = 100 pF. 2. fXX: External oscillator frequency (fXX = 12.58 MHz or fXX = 6.29 MHz) 3. fCLK: System clock oscillation frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) 34 Data Sheet U14118EJ1V0DS µPD78F4938A Serial Operation (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (c) UART0, UART3 (Asynchronous serial interface mode) Parameter ASCK0, ASCK2 cycle time ASCK0, ASCK2 low-level width ASCK0, ASCK2 high-level width Symbol tCYASK tWASKL tWASKH Conditions 4.0 ≤ VDD ≤ 5.5 V 4.0 ≤ VDD ≤ 5.5 V 4.0 ≤ VDD ≤ 5.5 V Data Sheet U14118EJ1V0DS MIN. TYP. MAX. Unit 160 ns 320 ns 65 ns 120 ns 65 ns 120 ns 35 µPD78F4938A Serial Operation (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (d) IOE1, IOE2 3-wire serial I/O mode (SCK1, SCK2 ... External clock input) Parameter SCK cycle time (SCK1, SCK2) Symbol tCYSK1 Conditions MIN. 4.0 ≤ VDD ≤ 5.5 V tCYSK2 4.0 ≤ VDD ≤ 5.5 V MAX. Unit 640 ns 1280 ns 280 ns 600 ns SCK low-level width tWSKL1, (SCK1, SCK2) tWSKL2 SCK high-level width tWSKH1, 280 ns (SCK1, SCK2) tWSKH2 600 ns SI1, SI2 setup time (to SCK1, SCK2↑) tSSSK1, tSSSK2 40 ns SI1, SI2 hold time (from SCK1, SCK2↑) tHSSK1, tHSSK2 40 ns Delay time from SCK1, SCK2↓ to output tDSOSK1, tDSOSK2 0 SO1, SO2 output hold time (from SCK1, SCK2↑) tHSOSK1, tHSOSK2 4.0 ≤ VDD ≤ 5.5 V When data is transferred 50 0.5tCYSK1 – 40, 0.5tCYSK2 – 40 ns ns Remarks 1. The values in this table are those when CL = 100 pF. 2. T: Selected serial clock cycle. The minimum value is 8/fXX. (e) IOE1, IOE2 3-wire serial I/O mode (SCK1, SCK2 ... Internal clock output) Parameter Symbol Conditions SCK cycle time (SCK1, SCK2) tCYSK1 tCYSK2 T ns SCK low-level width (SCK1, SCK2) tWSKL1, tWSKL2 0.5T – 40 ns SCK high-level width (SCK1, SCK2) tWSKH1, tWSKH2 0.5T – 40 ns SI1, SI2 setup time (to SCK1, SCK2↑) tSSSK1, tSSSK2 40 ns SI1, SI2 hold time (from SCK1, SCK2↑) tHSSK1, tHSSK2 40 ns Delay time from SCK1, SCK2↓ to output tDSOSK1, tDSOSK2 0 SO1, SO2 output hold time (from SCK1, SCK2↑) tHSOSK1, tHSOSK2 When data is transferred Remarks 1. The values in this table are those when CL = 100 pF. 2. T: Selected serial clock cycle. The minimum value is 8/fXX. 36 Data Sheet U14118EJ1V0DS MIN. 0.5tCYSK1 – 40, 0.5tCYSK2 – 40 MAX. 50 Unit ns ns µPD78F4938A Other Operations (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit NMI high-/low-level width tWNIL tWNIH 10 µs INTP0 high-/low-level width tWIT0L tWIT0H 4tCYSMP s INTP1 to INTP3, CI high-/ low-level width tWIT1L tWIT1H 4tCYCPU s INTP4, INTP5 high-/ low-level width tWIT2L tWIT2H 10 µs RESET high-/low-level widthNote tWRSL tWRSH 10 µs Note When the power is turned on or when STOP mode is released by reset, secure the oscillation stabilization wait time while the RESET is at a low-level width. When the power is applied, be sure to activate VDD in the RESET = low-level state. Remark tCYSMP: Sampling clock set by software tCYCPU: CPU clock set by software in the CPU Clock Output Operation (TA = –40 to +85°C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions CLKOUT cycle time tCYCL nT CLKOUT low-level width tCLL 4.5 ≤ VDD ≤ 5.5 V CLKOUT high-level width CLKOUT rise time CLKOUT fall time tCLH tCLR tCLF MIN. TYP. 79 4.5 ≤ VDD ≤ 5.5 V MAX. Unit 32000 ns 0.5T – 10 ns 0.5T – 20 ns 0.5T – 10 ns 0.5T – 20 ns 4.5 ≤ VDD ≤ 5.5 V 10 ns 3.0 ≤ VDD ≤ 4.5 V 20 ns 4.5 ≤ VDD ≤ 5.5 V 10 ns 3.0 ≤ VDD ≤ 4.5 V 20 ns Remark n: Division ratio of clock output frequency, T: tCYK = 1/fCLK (system clock cycle time) IEBus Controller Characteristics (TA = –40 to +85°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol IEBus system clock frequency fs Conditions Mode 1 MIN. TYP. 6.29 MAX. Unit MHz Remark Although the system clock frequency in the IEBus specifications is 6.0 MHz, in the µPD784938A, operation at 6.29 MHz is also guaranteed. Note, however, that operation at 6.0 MHz and 6.29 MHz cannot be used together. Data Sheet U14118EJ1V0DS 37 µPD78F4938A A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF1 = 3.0 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution Overall MIN. TYP. 8 errorNote 1 bit ±0.6 %FSRNote 2 6.29 MHz ≤ fXX ≤ 12.58 MHz and FR = 1 ±1.5 %FSRNote 2 ±1 ±2.2 %FSRNote 2 ±1.4 ±2.6 %FSRNote 2 ±1/2 LSB 3.0 ≤ VDD < 5.5 V Quantization error Sampling time tCONV tSAMP Analog input voltage VIAN Analog input impedance RAN Unit IEAD = 00H 6.29 MHz ≤ fXX ≤ 12.58 MHz and other than FR = 1 IEAD = 01H 4.5 ≤ VDD ≤ 5.5 V Conversion time MAX. FR = 1: 120tCYK 9.5 480 µs FR = 0: 240tCYK 19.1 960 µs FR = 1: 18tCYK 1.4 72 µs FR = 0: 36tCYK 2.9 144 µs AVSS AVREF1 V 1000 MΩ Reference voltage AVREF1 3.0 AVREF1 resistor RAVREF1 3.0 AVREF1 current AIREF1 0.5 1.5 mA AVDD current AIDD1 2.0 5.0 mA 20 mA AIDD2 AVDD 10 V kΩ Notes 1. Excludes quantization error (±1/2 LSB). 2. It is indicated as a ratio (%FSR) to the full-scale value. Caution The analog input pins of the µPD78F4938A function alternately as the port 7 pins (I/O port pins). However when using the A/D converter, it is necessary to set all the pins of port 7 to input mode in order to prevent data from being inverted by the output port operation, thus degrading the A/D conversion accuracy. At this time, pins cannot be used as output ports even though they are not used as A/D analog input port. 38 Data Sheet U14118EJ1V0DS µPD78F4938A Serial Operation (CSI, CSI3) tWSKLn tWSKHn SCK0, SCK3 tSSSKn tHSSKn tCYSKn Input data SI0, SI3 tHSBSKn tDSBSKn Output data SO0, SO3 n = 0, 3 Serial Operation (IOE1, IOE2) tWSKL1 tWSKH1 SCK1, SCK2 tSSSK1 tCYSK1 tHSSK1 Input data SI1, SI2 tDSOSK tHSOSK Output data SO1, SO2 Serial Operation (UART0, UART2) tWASKH tWASKL ASCK0, ASCK2 tCYASK Clock Output Timing tCLH tCLL CLKOUT tCLR tCLF tCYCL Data Sheet U14118EJ1V0DS 39 µPD78F4938A Interrupt Request Input Timing tWNIH tWNIL tWIT0H tWIT0L tWIT1H tWIT1L tWIT2H tWIT2L NMI INTP0 CI, INTP1 to INTP3 INTP4, INTP5 Reset Input Timing tWRSH tWRSL RESET 40 Data Sheet U14118EJ1V0DS µPD78F4938A Data Retention Characteristics STOP mode setting VDD VDDDR tHVD tFVD tRVD tDREL tWAIT RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge) Data Sheet U14118EJ1V0DS 41 µPD78F4938A 8. PACKAGE DRAWING 100PIN PLASTIC QFP (14x20) A B 51 50 80 81 detail of lead end C D S R Q 31 30 100 1 F J G H I P M K M N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 23.6±0.4 INCHES 0.929±0.016 B 20.0±0.2 0.795 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F 0.8 0.031 G 0.6 0.024 H 0.30±0.10 0.012 +0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7±0.1 0.106 +0.005 –0.004 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. P100GF-65-3BA1-3 Remark The external dimensions and material of the ES version are the same as those of the mass-produced version. 42 Data Sheet U14118EJ1V0DS µPD78F4938A 9. RECOMMENDED SOLDERING CONDITIONS The µPD78F4938A should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions µPD78F4938AGF-3BA: 100-pin plastic QFP (14 × 20) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) IR35-207-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) VP15-207-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: once, Preheating temperature: 120°C max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) WS60-207-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Note – After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet U14118EJ1V0DS 43 µPD78F4938A APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD78F4938A. Also refer to (5) Cautions on using development tools. (1) Language processing software RA78K4 Assembler package common to 78K/IV Series CC78K4 C compiler package common to 78K/IV Series DF784937 Device file for µPD784938A Subseries CC78K4-L C compiler library source file common to 78K/IV Series (2) Flash memory writing tools Flashpro III (PG-FP3) Flash programmer for microcontroller with on-chip flash memory FA-100GF Flash memory writing adapter for 100-pin plastic QFP (GF-3BA type). Wiring must be performed according to the product used. (3) Debugging tools • When IE-78K4-NS in-circuit emulator is used IE-78K4-NS In-circuit emulator common to 78K/IV Series IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter used when PC-9800 series (except notebook type) is used as host machine IE-70000-CD-IF-C PC card and cable used when PC-9800 series notebook type PC is used as host machine IE-70000-PC-IF-C Interface adapter used when IBM PC/ATTM or compatible is used as host machine IE-784937-NS-EM1 Emulation board to emulate µPD784938A Subseries NP-100GF Emulation probe for 100-pin plastic QFP (GF-3BA type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 System simulator common to 78K/IV Series DF784937 Device file for µPD784938A Subseries 44 Data Sheet U14118EJ1V0DS µPD78F4938A • When IE-784000-R in-circuit emulator is used IE-784000-R In-circuit emulator common to 78K/IV Series IE-70000-98-IF-B IE-70000-98-IF-C Interface adapter used when PC-9800 series (except notebook type) is used as host machine IE-70000-98N-IF Interface adapter and cable used when PC-9800 series notebook type PC is used as host machine IE-70000-PC-IF-B IE-70000-PC-IF-C Interface adapter used when IBM PC/AT or compatible is used as host machine IE-78000-R-SV3 Interface adapter and cable used when EWS is used as host machine IE-784937-NS-EM1 Emulation board to emulate µPD784938A Subseries IE-784000-R-EM Emulation board common to 78K/IV Series IE-78K4-R-EX2 Emulation probe conversion board necessary when using IE-784937-NS-EM1 on IE-784000-R. Not necessary when using IE-784937-R-EM1 EP-78064GF-R Emulation probe for 100-pin plastic QFP (GF-3BA type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) ID78K4 Integrated debugger for IE-784000-R SM78K4 System simulator common to 78K/IV Series DF784937 Device file for µPD784938A Subseries (4) Real-time OS RX78K/IV Real-time OS for 78K/IV Series MX78K4 OS for 78K/IV Series Data Sheet U14118EJ1V0DS 45 µPD78F4938A (5) Cautions on using development tools • The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784937. • The CC78K4 and RX78K/IV are used in combination with the RA78K4 or DF784937. • The Flashpro III, FA-100GF, and NP-100GF are products made by Naito Densei Machida Mfg. Co, Ltd (TEL +81-44-822-3813). • The host machine and OS suitable for each software are as follows: Host Machine [OS] PC EWS Software PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] RA78K4 √ Note √ CC78K4 √ Note √ ID78K4-NS √ — ID78K4 √ √ SM78K4 √ — RX78K/IV √ Note √ MX78K4 √ Note √ Note 46 DOS-based software Data Sheet U14118EJ1V0DS µPD78F4938A APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents related to devices Document Name Document No. µPD784935A, 784936A, 784937A, 784938A Data Sheet Under preparation µPD78F4938A Data Sheet This document µPD784938 Subseries User’s Manual Hardware U13987E 78K/IV Series User’s Manual Instructions U10905E 78K/IV Series Application Note Software Basics U10095E • Documents related to development tools (user’s manuals) Document Name RA78K4 Assembler Package Document No. Language U11162E Operation U11334E Structured Assembler U11743E Preprocessor CC78K4 C Compiler Language U11571E Operation U11572E PG-FP3 Flash Memory Programmer U13502E IE-78K4-NS U13556E IE-784000-R U12903E IE-784937-R-EM1 To be prepared IE-784937-NS-EM1 To be prepared EP-78064 EEU-1469 SM78K4 System Simulator Windows Based Reference U10093E SM78K Series System Simulator External Part User Open Interface Specifications U10092E ID78K4 Integrated Debugger Windows Based Reference U10440E ID78K4-NS Integrated Debugger Windows Based Reference U12796E Project Manager Ver. 3.12 or Later Windows Based U14610E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U14118EJ1V0DS 47 µPD78F4938A • Documents related to embedded software (user’s manuals) Document Name 78K/IV Series Real-Time OS Document No. Fundamental U10603E Installation U10604E • Other documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System U10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 48 Data Sheet U14118EJ1V0DS µPD78F4938A [MEMO] Data Sheet U14118EJ1V0DS 49 µPD78F4938A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM, FIP, and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 50 Data Sheet U14118EJ1V0DS µPD78F4938A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U14118EJ1V0DS 51 µPD78F4938A • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00.4