DATA SHEET MOS Integrated Circuit µPD78P322 16/8-BIT SINGLE-CHIP MICROCONTROLLER The µPD78P322 is a version provided by replacing the µPD75322's internal mask ROM with one-time PROM or EPROM. Because the one-time PROM version is programmable only once by users, it is ideally suited for small-scale production of many different products, and rapid development and time-to-market of application sets. The EPROM version is reprogrammable, and suited for the evaluation of systems. The µPD78P322K, which is the EPROM version, does not maintain planned reliability when used in mass-produced products. Please use only experimentally or for evaluating functions during trial manufacture. Functions are described in detail in the following user's manual. Be sure to read it for designing. µPD78322 User's Manual: IEU-1248 FEATURES • µPD78322 compatible • For mass-production, the µPD78P322 can be replaced with the µPD78322 which incorporates mask ROM • Internal PROM: 16,384 × 8 bits • Programmable once only (one-time PROM version without window) • Erasable with ultraviolet rays and electrically programmable (EPROM version with window) • • PROM programming characteristics: µPD27C256A compatible The µPD78P328 is a QTOPTM microcontroller Remark QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM, and are totally supported by NEC's programming service (from programming to marking, screening, and verification). ORDERING INFORMATION Part Number Package Internal ROM Quality Grade µPD78P322GF-3B9 80-pin plastic QFP (14 × 20 mm) One-time PROM Standard µPD78P322GJ-5BJ 74-pin plastic QFP (20 × 20 mm) One-time PROM Standard µPD78P322L 68-pin plastic QFJ (950 × 950 mils) One-time PROM Standard µPD78P322K 80-pin ceramic WQFN EPROM Not applicable µPD78P322KC 68-pin ceramic WQFN EPROM Standard µPD78P322KD 74-pin ceramic WQFN EPROM Standard Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document. The information in this document is subject to change without notice. Document No. U10435EJ5V0DS00 (5th edition) (Previous No. IC-2485) Date Published December 1995 P Printed in Japan The mark * shows revised points. © © 1991 1994 µPD78P322 PIN CONFIGURATIONS (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 20 mm) µPD78P322GF-3B9 • 80-pin ceramic WQFN NC P26/INTP5 P25/INTP4 P24/INTP3 P23/INTP2 P22/INTP1 P21/INTP0 P20/NMI VDD AVDD AVREF P77/AN7 P76/AN6 P75/ANI5 P74/AN4 P73/AN3 µPD78P322K 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P72/ANI2 NC NC P71/ANI1 P70/ANI0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 NC NC NC P42/AD2 RTP2/P02 RTP3/P03 RTP4/P04 RTP5/P05 RTP6/P06 RTP7/P07 EA VSS VSS P93/TMD P92/TAS P91/WR P90/RD ASTB P40/AD0 P41/AD1 P27/INTP6/ TI NC NC P30/TxD P31/RxD P32/SO/SB0 P33/S1/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 NC P85/TO11 RESET X2 X1 VSS WDTO RTP0/P00 NC TRP1/P01 NC Caution Connect NC pins to VSS as a measure against noise (can leave open). Remark These pins are compatible with the µPD78322GF pins. The µPD78P322K does not maintain planned reliability when used in mass-produced products. Please use only experimentally or for evaluating functions during trial manufacture. 2 µPD78P322 • 74-pin plastic QFP (20 × 20 mm) µPD78P322GJ-5BJ • 74-pin ceramic WQFN P42/AD2 P41/AD1 P40/AD0 ASTB P90/RD P91/WR P92/ TAS P93/ TMD VSS EA P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 P01/RTP1 NC µPD78P322KD P00/RTP0 WDTO VSS NC X1 X2 RESET P85/TO11 P84/TO10 P83/TO03 P82/TO02 P81/TO01 P80/TO00 NC P34/SCK P33/SI/SBI P32/SO/SB0 P31/RxD P30/TxD NC P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVREF AVDD VDD P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P25/INTP4 P26/INTP5 P27/INTP6 NC P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 NC P56/A14 P57/A15 VDD AVSS P70/AN0 P71/AN1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 54 2 3 53 4 52 5 51 6 50 7 49 8 48 9 47 10 46 11 45 12 44 13 43 14 42 15 41 16 40 17 39 18 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Caution Connect NC pins to VSS for measures against noise (can leave open). Remark These pins are compatible with the µPD78322GJ pins. 3 µPD78P322 • 68-pin plastic QFJ (950 × 950 mils) µPD78P322L • 68-pin ceramic WQFN 4 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVREF AVDD VDD P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P25/INTP4 Remark These pins are compatible with the µPD78322L pins. P42/AD2 P41/AD1 P40/AD0 ASTB P90/RD P91/WR P92/TAS P93/TMD VSS EA P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P01/RTP1 P30/TxD P31/RxD P32/SO/SB0 P33/SI/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 P85/TO11 RESET X2 X1 VSS WDTO RTP0/P00 P26/INTP5 P27/INTP6/TI µPD78P322KC P71/AN1 P70/AN0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 µPD78P322 P00-P07 : Port 0 RESET : Reset P20-P27 : Port 2 X1, X2 : Crystal P30-P34 : Port 3 WDTO : Watchdog Timer Output P40-P47 : Port 4 EA : External Access P50-P57 : Port 5 TMD : Turbo Mode P70-P77 : Port 7 TAS : Turbo Access Strobe P80-P85 : Port 8 WR : Write Strobe P90-P93 : Port 9 RD : Read Strobe NMI : Nonmaskable Interrupt ASTB : Address Strobe INTP0-INTP6 : Interrupt From Peripherals AD0-AD7 : Address/Data Bus RTP0-RTP7 : Real-Time Port A8-A15 : Address Bus TI : Timer Input AN0-AN7 : Analog Input TxD : Transmit Data AVREF : Analog Reference Voltage RxD : Receive Data AVSS : Analog VSS SB0/SO : Serial Bus/Serial Output AVDD : Analog VDD SB1/SI : Serial Bus/Serial Input VDD : Power Supply SCK : Serial Clock VSS : Ground TO00-TO03 : NC : No Connection TO10, TO11 : } Timer Output 5 µPD78P322 (2) PROM programming mode (RESET = H, AVDD = L) • 80-pin plastic QFP (14 × 20 mm) µPD78P322GF-3B9 • 80-pin ceramic WQFN Cautions 1. (G) A9 VDD AVDD A2 A3 A4 A5 A6 A7 VPP VSS VSS A8 A10 A11 A12 A13 NC A14 RESET (Open) (G) VSS (Open) A0 NC A1 NC (G) NC NC (G) VDD (Open) D7 D6 D5 D4 D3 NC NC NC D2 D0 D1 (L) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (Open) (G) NC NC OE CE (G) NC µPD78P322K The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. 2. L : Connect each pin to VSS via a resistor. G : Connect the pin to VSS. Open : Leave the pin unconnected. Connect NC pins to VSS for measures against noise (can leave open). The µPD78P322K does not maintain planned reliability when used in mass-produced products. Please use only experimentally or for evaluating functions during trial manufacture. 6 µPD78P322 • 74-pin plastic QFP (20 × 20 mm) µPD78P322GJ-5BJ • 74-pin ceramic WQFN NC (G) Cautions 1. VSS VPP A7 A6 A5 A4 A3 A2 A1 NC A0 (Open) VSS NC (G) (Open) RESET A14 A13 A12 A11 A10 A8 NC (L) CE OE NC VDD (G) NC (L) AVDD VDD A9 (L) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 54 2 3 53 4 52 5 51 6 50 7 49 8 48 9 47 10 46 11 45 12 44 13 43 14 42 15 41 16 40 17 39 18 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 (G) D3 D4 D5 D6 D7 (L) D2 D1 D0 (Open) µPD78P322KD The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. 2. L : Connect each pin to VSS via a resistor. G : Connect the pin to VSS. Open : Leave the pin unconnected. Connect NC pins to VSS as measure against noise. 7 µPD78P322 • 68-pin plastic QFJ (950 × 950 mil) µPD78P322L • 68-pin ceramic WQFN (G) AVDD VDD (G) VDD (L) D7 D6 D5 D4 D3 D2 D1 D0 (Open) (L) VSS A7 VPP A6 A5 A1 (Open) A0 A4 A8 A10 A11 A12 A13 A14 RESET (Open) (G) VSS A3 (L) 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A2 OE CE A9 (G) µPD78P322KC Caution The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. 8 L : Connect each pin to VSS via a resistor. G : Connect the pin to VSS. Open : Leave the pin unconnected. A0-A14 : Address Bus RESET : D0-D7 : Data Bus AV DD : CE : Chip Enable VPP : Programming Power Supply OE : Output Enable NC : No Connection } Programming Mode set BCU X1 X2 RESET ASTB RD WR TAS TMD EA/VPP Note (P20) NMI INTP0-INTP5 (P21-P26) (P80) TO00 (P81) TO01 (P82) TO02 (P83) TO03 (P84) TO10 (P85) TO11 (P27) TI/INTP6 PROGRAMMABLE INTERRUPT CONTROLLER TIMER/COUNTER UNIT (REALTIME PULSE UNIT) GENERAL REGISTERS 128 bytes & DATA MEMORY 128 bytes ALU PROM 16 Kbytes / Peripheral RAM 384 bytes MICRO SEQUENCE CONTROL SYSTEM CONTROL & BUS CONTROL & PREFETCH CONTROL BLOCK DIAGRAM PROM/RAM EXU Main RAM A8-A15 (P50-P57) AD0-AD7 (P40-P47) A0-A14 D0-D7 MICRO ROM Note CE OE (P34) SCK (P32) SO/SB0 (P33) SI/SB1 (P30) TxD SERIAL INTERFACE (SBI) (UART) A/D CONVERTER (10 bits) 9 µPD78P322 P00-P07 (REALTIME PORT) P20-P27 P30-P34 P40-P47 P50-P57 P70-P77 P80-P85 P90-P93 VDD WDTO VSS AVREF AVSS During PROM programming mode AVDD ANI0-ANI7 (P70-P77) Note PORT 2 2 (P31) RxD WDT µPD78P322 CONTENTS 1. PIN FUNCTIONS ... 11 1.1 Normal Operating Mode ... 11 1.2 PROM Programming Mode (RESET = H, AVDD = L) ... 13 1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 14 2. DIFFERENCES BETWEEN µPD78P322 and µPD78322 ... 16 3. PROM PROGRAMMING ... 17 3.1 Operation Mode ... 17 3.2 PROM Write Procedure ... 18 3.3 PROM Read Procedure ... 20 4. ERASURE CHARACTERISTICS (FOR µPD78P322K/KC/KD ONLY) ... 21 5. OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P322K/KC/KD ONLY) ... 21 6. ONE-TIME PROM VERSION SCREENING ... 21 7. ELECTRICAL SPECIFICATIONS ... 22 8. PACKAGE DRAWINGS ... 36 9. RECOMMENDED SOLDERING CONDITIONS ... 42 APPENDIX A. * DRAWINGS OF CONVERSION SOCKETS AND RECOMMENDED FOOTPRINTS ... 44 APPENDIX B. TOOLS ... 48 B.1 Development Tools ... 48 B.2 Evaluation Tools ... 52 B.3 Embedded Software ... 52 10 µPD78P322 1. PIN FUNCTIONS 1.1 Normal Operating Mode (1) Port Pins Pin Name Input/Output Function P00-P07 Input/Output PORT0 (Output) 8-bit input/output port Alternate Function RTP0-RTP7 Input or output mode can be specified bit-wise. The port can also operate as a real-time output port. P20 Input P21 PORT 2 NMI 8-bit input-only port INTP0 P22 INTP1 P23 INTP2 P24 INTP3 P25 INTP4 P26 INTP5 P27 P30 INTP6/TI Input/Output PORT 3 TxD P31 5-bit input/output port RxD P32 Input or output mode can be specified bit-wise. SO/SB0 P33 SI/SB1 P34 SCK P40-P47 Input/Output PORT 4 AD0-AD7 8-bit input/output port Input or output mode can be specified in 8-bit units. P50-P57 Input/Output PORT 5 A8-A15 8-bit input/output port Input or output mode can be specified bit-wise. P70-P77 Input PORT 7 AN0-AN7 8-bit input-only port PORT 8 TO00 P81 P80 Input/Output 6-bit input/output port TO01 P82 Input or output mode can be specified bit-wise. TO02 P83 TO03 P84 TO10 P85 TO11 P90 PORT 9 RD P91 4-bit input/output port WR P92 Input or output mode can be specified bit-wise. TAS P93 Input/Output TMD 11 µPD78P322 (2) Non-Port Pins (1/2) Pin Name Input/Output Function Alternate Function RTP0-RTP7 Output Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07 the real-time pulse unit (RPU). INTP0 Input INTP1 Edge-detected external interrupt request input. P21 The valid edge can be specified in the mode register. P22 INTP2 P23 INTP3 P24 INTP4 P25 INTP5 P26 INTP6 P27/TI NMI Input Edge-detected nonmaskable interrupt request input. P20 TI Input External count clock input pin to timer 1 (TM1). P27/INTP6 RxD Input Serial data input pin to asynchronous serial interface (UART). P31 TxD Output Serial data output pin from asynchronous serial interface (UART). P30 SI Input Serial data input pin to clocked serial interface in 3-wire mode. P33/SB1 SO Output Serial data output pin from clocked serial interface in 3-wire mode. P32/SB0 SB0 Input/Output Serial data input/output pins to/from clocked serial interface in SBI mode. The rising or falling edge can be selected for the valid edge by setting the mode register. SB1 SCK Input/Output Serial clock input/output pin to/from clocked serial interface. P34 AD0-AD7 Input/Output Multiplexed address/data bus used when external memory is added. P40-P47 A8-A15 Output Address bus used when external memory is added. P50-P57 RD Output Strobe signal output for external memory read operation. P90 WR * P32/SO P33/SI TAS Strobe signal output for external memory write operation. P91 Output Control signal output pins to access turbo access manager (µPD71P301). Note P92 Output Pulse output from real-time pulse unit. TMD TO00 P93 P80 TO01 P81 TO02 P82 TO03 P83 TO10 P84 TO11 P85 ASTB Output Timing signal output pin to externally latch low-order address information output from — WDTO Output Signal output which indicates that watchdog timer generated non-maskable interrupt. — EA Input For µPD78P322, normally connect the EA pin to VDD. When the EA pin is connected to — AD0-AD7 for external memory access. VSS, the µPD78P322 enters the ROMless mode and external memory is accessed. The EA pin level cannot be changed during operation. Note Turbo access manager (µPD71P301) is available for maintenance purposes only. 12 µPD78P322 (2) Non-Port Pins (2/2) Pin Name Input/Output Function Alternate Function AN0-AN7 Input Analog input to A/D converter. P70-P77 AVREF Input A/D converter reference voltage input. — AVDD — A/D converter analog power supply. — AVSS — A/D converter GND. — RESET Input System reset input. — X1 Input Crystal resonator connection pin for system clock generation. To supply external clock, — X2 input to the X1 and input inverted signal to the X2 pin (X2 pin can be unconnected.) VDD — Positive power supply pin. — VSS — GND pin. — NC — No internal connection. Connect to VSS (can leave open). — 1.2 PROM Programming Mode (RESET = H, AVDD = L) Pin Name Input/Output Function AVDD Input PROM programming mode setting. Input Address bus. D0-D7 Input/Output Data bus. CE Input PROM enable to PROM. RESET A0-A14 OE Input Read strobe to PROM. VPP — Write power supply. VDD Positive power supply. VSS GND. NC No internal connection. Connect to VSS (can leave open). 13 µPD78P322 1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Table 1-1 and Figure 1-1 show the pin input/output circuit schematically. Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins Pin Input/Output Recommended connection of unused pins circuit type P00/RTP0-P07/RTP7 5 P20/NMI 2 Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. Connect to VSS. P21/INTP0-P26/INTP5 P27/INTP6/TI P30/TxD 5 P31/RxD P32/SO/SB0 Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. 8 P33/SI/SB1 P34/SCK P40/AD0-P47/AD7 5 P50/A8-P57/A15 P70/AN0-P77/AN7 9 P80/TO00-P83/TO03 5 P84/TO10, P85/TO11 P90/RD Connect to VSS. Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. 5 P91/WR P92/TAS P93/TMD WDTO 3 ASTB 4 Leave Open. EA 1 — RESET 2 — AVDD — Connect to VDD. AVREF — Connect to VSS. VPP — Connect to VDD. NC — Connect to VSS (can leave open). AVSS 14 µPD78P322 Figure 1-1. Pin Input/Output Circuits TYPE 1 TYPE 5 VDD VDD IN P-ch data P-ch output disable N-ch IN/OUT N-ch input disable TYPE 2 TYPE 8 VDD IN data P-ch output disable N-ch IN/OUT Schmitt-triggerred input with hysteresis characteristics TYPE 3 TYPE 9 VDD IN P-ch OUT P-ch N-ch Comparator + – VREF (Threshold voltage) N-ch input enable TYPE 4 VDD data P-ch output disable N-ch OUT Push-pull output that can be placed in high impedance (both P-ch and N-ch off). 15 µPD78P322 2. DIFFERENCES BETWEEN µPD78P322 and µPD78322 The µPD78P322 is a version provided by replacing the µPD78322's on-chip mask ROM with one-time PROM or EPROM. Thus, the µPD78P322 and µPD78322 are the same in function except for the ROM specifications such as write or verify. Table 2-1 lists the differences between these two products. This Data Sheet describes the PROM specification function. Refer to the µPD78322 documents for details of other functions. Table 2-1. Differences between µPD78P322 and µPD78322 Part Number µPD78P322 Item * * * µPD78322 Internal program memory One-time PROM EPROM (electrical program) (programmable only once) (reprogrammable) PROM programming pin Contained Package • 68-pin plastic QFJ • 68-pin ceramic WQFN • 68-pin plastic QFJ • 74-pin plastic QFP • 74-pin ceramic WQFN • 74-pin plastic QFP • 80-pin plastic QFP • 80-pin ceramic WQFN • 80-pin plastic QFP Electrical specifications Others Mask ROM (nonprogrammable) Not contained Current dissipations are different. Noise immunity and noise radiation differ because circuit complexity and mask layout are different. Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To replace the PROM version with the mask ROM version when shifting from experimental production to mass production, evaluate your system by using the CS version (not ES version) of the mask ROM version. 16 µPD78P322 3. PROM PROGRAMMING The PROM incorporated in the µPD78P322 is a 16,384 × 8-bit electrically writable PROM. For programming, set the PROM programming mode by using the RESET and AVDD pins. The programming characteristics are compatible with the µPD27C256A programming characteristics. Table 3-1. Pin Function in Programming Mode Function Normal Operating Mode Programming Mode Address input P00-P07, P80, P20, P81-P85 A0-A14 Data input P40-P47 D0-D7 Chip enable/program pulse P31 CE Output enable P30 OE Program voltage VPP Mode control RESET, AVDD 3.1 Operation Mode To set the program write/verify mode, set RESET = H and AVDD = L. For the mode, the operation mode can be selected by setting the CE and OE pins, as listed in Table 3-2. To read the PROM contents, set the read mode. Connect the unused pins exactly as indicated in Pin Configuration. Table 3-2. PROM Programming Operation Mode Mode RESET AVDD Program write H L CE OE VPP VDD +12.5 V +6 V D0-D7 L H Program verify H L Data output Program inhibit H H High impedance Read L L +5 V +5 V Data input Data output Output disable L H High impedance Standby H L/H High impedance Caution When VPP is set to +12.5 V and VDD is set to +6V, setting both CE and OE to L is prohibited. 17 µPD78P322 3.2 PROM Write Procedure The write procedure into PROM is as follows: (1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated in section "Pin Configuration." (2) Supply +6 V to the VDD and +12.5 V to the VPP pin. (3) Supply an initial address. (4) Supply write data. (5) Supply 1 ms program pulse (active low) to the CE pin. (6) Execute the verify mode. Check whether or not the write data is written normally. • When it is written normally: Proceed to step (8). • When it is not written normally: Repeat steps (4) to (6). If the data is not written normally after 25 repetitions of the steps, proceed to step (7). (7) Assume the device to be defective. Stop write operation. (8) Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write). (9) Increment the address. (10) Repeat steps (4) to (9) to the last address. Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above. Figure 3-1. PROM Write/Verify Timing X-time repetition Write Address input A0-A14 Hi-Z D0-D7 Additional data write Verify Hi-Z Data input Data output Hi-Z Hi-Z Data input +12.5 V VPP VDD +6 V VDD VDD CE (input) OE (input) 18 3 X ms µPD78P322 Figure 3-2. Write Procedure Flowchart (1) WRITE START (2) Supply power (3) Supply initial address (4) Supply write data (5) Supply program pulse Write NG (after 24 repetition or less) (6) Verify mode Write NG (at the 25th repetition) Write OK (8) Make additional write (3X ms pulses) (9) Increment address X: Number of write repetitions (10) < end address End address > end address WRITE END (7) Defective device 19 µPD78P322 3.3 PROM Read Procedure The read procedure of the PROM contents into the external data bus (D0-D7) is as follows. (1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated in Pin Configuration. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to the A0-A14 pins. (4) Execute the read mode. (5) The data is output to the D0-D7 pins. Figure 3-3 shows the PROM read timing steps (2) to (5) above. Figure 3-3. PROM Read Timing A0-A14 Address input CE (input) OE (input) D0-D7 20 Hi-Z Data output Hi-Z µPD78P322 4. ERASURE CHARACTERISTICS (FOR µPD78P322K/KC/KD ONLY) The data written into the µPD78P322K/KC/KD program memory can be erased (FFH) and new data can be rewritten into the memory. To erase data, apply light with a wavelength shorter than 400 nm to the window. Normally, apply ultraviolet rays having the 254-nm wavelength. The radiation amount required to completely erase data is as follows: • Ultraviolet strength x erasure time: 15 W•s/cm2 or more • Erasure time: 15 to 20 minutes when a 12,000 µW/cm2 ultraviolet lamp is used. However, the time may be prolonged due to ultraviolet lamp performance deterioration, dirty window, etc. For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the ultraviolet lamp, remove the filter before applying ultraviolet rays. 5. OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P322K/KC/KD ONLY) If the µPD78P322K/KC/KD window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may be erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a protective seal on the window. A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at shipment. 6. ONE-TIME PROM VERSION SCREENING The one-time PROM versions (µPD78P322GF-3B9, 78P322GJ-5BJ, 78P322L) cannot be completely tested by NEC for shipment because of their structure. For screening, it is recommended to verify PROM after storing the necessary data under the following conditions: Storage temperature Storage time 125˚C 24 hours NEC provides chargeable services ranging from one-time PROM writing to marking, screening and verification for QTOP microcontroller products. For details, contact an NEC sales representative. 21 µPD78P322 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Ratings Unit Power supply voltage VDD Test Conditions –0.5 to +7.0 V AVDD –0.5 to VDD +0.5 V VPP –0.5 to +13.5 V AVSS Input voltage –0.5 to +0.5 V VI1 Note 1 –0.5 to VDD +0.5 V VI2 P20/NIM (A9) PIN –0.5 to +13.5 V –0.5 to VDD +0.5 V All output pins 4.0 mA Total for all pins 90 mA All output pins –1.0 mA Total for all pins –20 mA Note 2 AVDD > VDD –0.5 to VDD +0.5 V VDD ≥ AVDD –0.5 to AVDD +0.5 AVDD > VDD –0.5 to VDD +0.3 VDD ≥ AVDD –0.5 to AVDD +0.3 Output voltage VO Output current, low IOL Output current, high IOH Analog input voltage VIAN A/D converter reference AVREF input voltage V Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Notes 1. Pins except for P20/NMI (A9), P70/AN0-P77/AN7 2. P70/AN0-P77/AN7 * Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions Oscillation frequency TA VDD 8 MHz ≤ fXX ≤ 16 MHz –10 to +70 ˚C +5.0 V ±5% Capacitance (TA = 25 °C, VSS = VDD = 0 V) 22 Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz 10 pF Output capacitance CO Unmeasured pins returned to 0 V 20 pF I/O capacitance CIO 20 pF µPD78P322 Oscillator Characteristics (TA = –10 to +70 °C, VDD = +5 V±5%, VSS = 0 V) Resonator Recommended Circuit Parameter MIN. MAX. Unit Oscillation frequency (fXX) 8 16 MHz X1 input frequency (fX) 8 16 MHz X2 Open X1 input rise, fall time (fXR, tXF) 0 20 ns HCMOS Inverter X1 input high, low level width 25 80 ns Ceramic or crystal resonator X2 VSS X1 C2 C1 External clock X1 X2 HCMOS Inverter or X1 (tWXH, tWXL) Caution When using the system clock oscillator, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influences on the wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillator. 23 µPD78P322 Recommended Oscillator Constants Ceramic resonator Manufacturer Name MURATA Part Number Frequency Recommended [MHz] Constants C1 [pF] C2 [pF] 30 30 15 15 Internal Internal CSA8.00MT 8.0 CSA12.0MT 12.0 CSA14.74MXZ040 14.74 CSA16.00MX040 16.0 CST8.00MTW 8.0 CST12.0MTW 12.0 CST14.74MXW0C3 14.74 CST16.00MXW0C3 16.0 Part Number Frequency Recommended [MHz] Constants Crystal resonator Manufacturer Name KINSEKI HC49/U-S HC49/U 24 8 to 16 C1 [pF] C2 [pF] 10 10 µPD78P322 DC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. Input voltage, low VIL Input voltage, high VIH1 Note 1 2.2 VIH2 Note 2 0.8VDD Output voltage, low VOL IOL = 2.0 mA Output voltage, high VOH IOH = –400 µA Input leakage current ILI 0 V ≤ VI ≤ VDD ±10 µA Output leakage current ILO 0 V ≤ VO ≤ VDD ±10 µA V DD power supply current IDD1 Operation mode 40 65 mA IDD2 HALT mode 20 35 mA Data retention voltage VDDDR STOP mode Data retention current IDDDR STOP mode 0 MAX. Unit 0.8 V V 0.45 VDD–1.0 V V 2.5 V VDDDR = 2.5 V 2 10 µA VDDDR = 5.0 V ±5% 10 50 µA Notes 1. Pins other than mentioned in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, or P34/SCK pins. 25 µPD78P322 * AC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V) Discontinuous read/write operation (when general-purpose memory is connected) Parameter Symbol System clock cycle time MIN. MAX. Unit tCYK 125 250 ns Address setup time (to ASTB ↓) tSAST 32 ns Address hold time (from ASTB ↓) tHSTA 32 ns Address → RD ↓ delay time tDAR 85 ns RD ↓ → address float time tFRA 0 ns Address → data input time tDAID 222 ns RD ↓ → data input time tDRID 112 ns ASTB ↓ → RD ↓ delay time tDSTR 42 ns Data hold time (from RD ↑) tHRID 0 ns RD ↑ → address active time tDRA 50 ns RD low level width tWRL 157 ns ASTB high level width tWSTH 37 ns Address → WR ↓ delay time tDAW 85 ns ASTB ↓ → data output time tDSTOD 102 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 42 ns Data setup time (to WR ↑) tSODW 147 ns Data hold time (from WR ↑) tHWOD 32 ns WR ↑ → ASTB ↑ delay time tDWST 42 ns WR low level width tWWL 157 ns 26 Test Conditions µPD78P322 tCYK-Dependent Bus Timing Definition Parameter Calculation expression MIN./MAX. Unit tSAST 0.5T – 30 MIN. ns tHSTA 0.5T – 30 MIN. ns tDAR T – 40 MIN. ns tDAID (2.5 + n) T – 90 MAX. ns tDRID (1.5 + n) T – 75 MAX. ns tDSTR 0.5T – 20 MIN. ns tDRA 0.5T – 12 MIN. ns tWRL (1.5 + n) T – 30 MIN. ns tWSTH 0.5T – 25 MIN. ns tDAW T – 40 MIN. ns tDSTOD 0.5T + 40 MAX. ns tDSTW 0.5T – 20 MIN. ns tSODW 1.5T – 40 MIN. ns tHWOD 0.5T – 30 MIN. ns tDWST 0.5T – 20 MIN. ns tWWL (1.5 + n) T – 30 MIN. ns Remarks 1. T = tCYK = 1/fCLK (fCLK is the internal system clock frequency). 2. n is the number of wait cycles defined by user software. 3. Only parameters listed in the table are dependent on tCYK. 27 µPD78P322 Serial Operation (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V) Parameter Symbol Test Conditions MIN. Serial clock cycle time tCYSK SCK Output Internal divide by 8 1 µs SCK Input External clock 1 µs SCK Output Internal divide by 8 420 ns SCK Input External clock 420 ns SCK Output Internal divide by 8 420 ns SCK Input External clock 420 ns Serial clock high-level width Serial clock high-level width tWSKL tWSKH MAX. Unit SI setup time (to SCK ↑) tSRXSK 80 ns SI hold time (from SCK ↑) tHSKRX 80 ns SCK ↓ → SO delay time tDSKTX R = 1 kΩ, C = 100 pF 210 ns MAX. Unit Other operations (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V) Parameter Symbol NMI high, low-level width tWNIH, Test Conditions MIN. 5 µs 8T tCYK 8T tCYK 8T tCYK 8T tCYK 8T tCYK 8T tCYK 8T tCYK 5 µs 8T tCYK tWNIL INTP0 high, low-level width tWI0H, tWI0L INTP1 high, low-level width tWI1H, tWI1L INTP2 high, low-level width tWI2H, tWI2L INTP3 high, low-level width tWI3H, tWI3L INTP4 high, low-level width tWI4H, tWI4L INTP5 high, low-level width tWI5H, tWI5L INTP6 high, low-level width tWI6H, tWI6L RESET high, low-level width tWRSH, tWRSL TI high, low-level width 28 tWTIH, TM1 tWTIL In the event counter mode µPD78P322 A/D Converter (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Test Conditions MIN. Resolution Total error TYP. MAX. 10 Note1 bit 4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR 3.4 V ≤ AVREF ≤ AVDD ±0.7 %FSR ±1/2 LSB Quantization error Conversion time Sampling time Zero scale error Fullscale error Nonlinear error tCONV 144 tCYK tSAMP 24 tCYK Note1 Note1 Note1 Analog input voltage Note2 Unit 4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB V IAN –0.3 AVDD V Basic voltage AVREF 3.4 AVDD V AVREF current AI REF 1.0 3.0 mA AVDD supply current AIDD 2.0 6.0 mA A/D converter data AI DDDR AVDDDR = 2.5 V 2.0 10 µA AVDDDR = 5 V±5% 10 50 µA STOP mode retention current * Notes 1. Quantization error is excluded. 2. When –0.3 V ≤ VIAN ≤ 0 V, conversion result is 000H. When 0 V < VIAN < AVREF, conversion is executed with 10-bit resolution. When AVREF ≤ V IAN ≤ AVDD, conversion result is 3FFH. 29 µPD78P322 Discontinuous Read Operation tCYK (CLK) P50-P57 (output) High-order address tDAID tSAST P40-P47 (input/output) Hi-Z High-order address Low-order address (output) Hi-Z Hi-Z Data (input) tWSTH Low-order address (output) Hi-Z tHRID ASTB (output) tHSTA tFRA RD (output) tDSTR tDRA tDRID tDAR tWRL Discontinuous Write Operation (CLK) P50-P57 (output) High-order address High-order address tSAST P40-P47 (input/output) Low-order address (output) Data (output) Undefined tHWOD tWSTH ASTB (output) tHSTA tDWST tDSTOD WR (output) tDSTW tDWOD tSODW tDAW tWWL 30 Low-order address (output) µPD78P322 Serial Operation tCYSK tWSKL tWSKH SCK tDSKTX SO SI tSRXSK tHSKRX Interrupt Input Timing tWNIL tWNIH NMI 0.8VDD 0.8 V tWInH tWInL INTPn Remark n = 0-6 31 µPD78P322 Reset Input Timing tWRSL tWRSH RESET 0.8VDD 0.8 V TI Pin Input Timing tWTIH TI 32 tWTIL µPD78P322 DC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V) Parameter Symbol Symbol Test conditions MIN. TYP. MAX. Unit VDDP V Note1 Input voltage, high VIH VIH 2.2 +0.3 Input voltage, low VIL VIL Input leakage current ILIP ILI 0 ≤ VI ≤ VDDP –0.3 Output voltage, high VOH VOH IOH = –400 µA Output voltage, low VOL VOL IOL = 2.0 mA 0.45 V Input current IA9 — A9 (P20/NMI) pin ±10 µA Output leakage current ILO — 0 ≤ VO ≤ VDDP, OE = VIN 10 µA PROG pin high voltage input IIP — ±10 µA VDDP VDD Note 2 0.8 V ±10 µA 2.4 V current V DDP power supply voltage V PP power supply voltage V DDP power supply current VPP IDD VPP IDD Program memory write mode 5.75 6.0 6.25 V Program memory read mode 4.5 5.0 5.5 V Program memory write mode 12.2 12.5 12.8 Program memory read mode VPP = VDDP V V Program memory write mode 10 30 mA Program memory read mode 10 30 mA 10 30 mA 1 100 µA CE = VIL, VI = VIH V PP power supply current IPP IPP Program memory write mode CE = VIL, OE = VIH Program memory read mode Notes 1. Corresponding µPD27C256A symbols. 2. VDDP is VDD pin during the programming mode. 33 µPD78P322 AC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V) Parameter Symbol Symbol Test conditions MIN. TYP. MAX. Unit Note tSAC tAS 2 µs Data → OE ↓ delay time tDDOO tOES 2 µs Input data setup time (to CE ↓) tSIDC tDS 2 µs Address hold time (from CE ↑) tHCA tAH 2 µs Input data hold time (from CE ↑) tHCID tDH 2 µs Output data hold time (from OE ↑) tHOOD tDF 0 VPP setup time (to CE ↓) tSVPC tVPS 2 VDDP setup time (to CE ↓) tSVDC tVDS 2 Initial program pulse width tWL1 tPW 0.95 Additional program pulse width tWL2 tOPW Address → data output time tDAOD tACC OE ↓ → data output time tDOOD tOE Data hold time (from OE ↑) tHCOD tDF Data hold time (from address) tHAOD tOH Address setup time (to CE ↓) Note 34 Corresponding µPD27C256A symbols. 2.85 OE = VIL 0 OE = VIL 0 130 ns µs µs 1.0 1.05 ms 78.75 ms 2 µs 1 µs 130 ns ns µPD78P322 PROM Write Mode Timing A12-A0 Effective address tSAC D7-D0 Hi-Z Data input tSIDC tHOOD Hi-Z Data output Hi-Z tHCID tHCA Hi-Z Data input tSIDC tHCID VPP VPP VDDP VDDP tSVPC VDDP +1 VDDP tSVDC VIH CE VIL tWL1 tDDOO tWL2 tDOOD VIH OE VIL Cautions 1. Apply VDDP before VPP and remove it after VPP. 2. VPP must not exceed +13 V, including the overshoot. PROM Read Mode Timing A12-A0 Effective address OE tDAOD D7-D0 Hi-Z tDOOD tHCOD tHAOD Data output Hi-Z 35 µPD78P322 8. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×20) A B 41 40 64 65 F Q 5°±5° S D C detail of lead end 25 24 80 1 G H I M J M P K N L P80GF-80-3B9-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 36 ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 0.8 0.031 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.15 0.006 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. +0.008 µPD78P322 74 PIN PLASTIC QFP ( 20) A F2 B 56 57 38 37 F1 Q R S D C detail of lead end 74 19 18 1 G1 G2 H I M J M P K N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.2±0.4 0.913 +0.017 –0.016 B 20.0±0.2 0.787 +0.009 –0.008 C 20.0±0.2 0.787 +0.009 –0.008 D 23.2±0.4 0.913 +0.017 –0.016 F1 2.0 0.079 F2 1.0 0.039 G1 2.0 0.079 G2 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 I 0.20 0.008 J 1.0 (T.P.) 0.039 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P Q 3.7 0.146 R 0.1±0.1 5°±5° 0.004±0.004 5°±5° S 4.0 MAX. 0.158 MAX. S74GJ-100-5BJ-3 37 µPD78P322 68 PIN PLASTIC QFJ ( 950 mil) A B C D F E H G U J 68 1 I T Q K M N M P P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 38 ITEM MILLIMETERS INCHES A 25.2 ± 0.2 0.992 ± 0.008 B 24.20 0.953 C 24.20 0.953 D 25.2 ± 0.2 0.992 ± 0.008 E 1.94 ± 0.15 0.076+0.007 –0.006 F 0.6 0.024 G 4.4 ± 0.2 0.173+0.009 –0.008 H 2.8 ± 0.2 0.110+0.009 –0.008 I 0.9 MIN. 0.035 MIN. J 3.4 0.134 K 1.27 (T.P.) 0.050 (T.P.) M 0.40 ± 1.0 0.016+0.004 –0.005 N 0.12 0.005 P 23.12 ± 0.20 0.910+0.009 –0.008 Q 0.15 0.006 T R 0.8 R 0.031 U 0.20 +0.10 –0.05 0.008+0.004 –0.002 µPD78P322 80 PIN CERAMIC WQFN A Q K C D B T W S 80 H U I 1 M R E F G J X80KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 20.0 ± 0.4 0.787+0.017 –0.016 B 19.0 0.748 C 13.2 0.520 D 14.2 ± 0.4 0.559 ± 0.016 E 1.64 0.065 F 2.14 0.084 G 4.064 MAX. 0.160 MAX. H 0.51 ± 0.10 0.020 ± 0.004 I 0.08 0.003 J 0.8 (T.P.) 0.031 (T.P.) K 1.0 ± 0.2 0.039 –0.008 Q C 0.5 C 0.020 R 0.8 0.031 S 1.1 0.043 T R 3.0 R 0.118 U 12.0 0.472 W 0.75 ± 0.2 0.030 –0.009 +0.009 +0.008 39 µPD78P322 74 PIN CERAMIC WQFN A K Q B D C T W S 74 Y H U I 1 M R G F E J X74KW-100A-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 40 ITEM MILLIMETERS INCHES A 20.0 ± 0.4 0.787+0.017 –0.016 B 18.0 0.709 C 18.0 0.709 D 20.0 ± 0.4 0.787+0.017 –0.016 E 1.94 0.076 F 2.14 0.084 G 4.0 MAX. 0.158 MAX. H 0.51 ± 0.10 0.020 ± 0.004 I 0.10 0.004 J 1.0 (T.P.) 0.039 (T.P.) K 1.0 ± 0.2 0.039 –0.008 Q C 0.3 C 0.012 R 2.0 0.079 S 2.0 0.079 T R 2.0 R 0.079 +0.009 U 10.0 0.394 W 0.7 ± 0.2 0.028 –0.009 Y C 1.5 C 0.059 +0.008 µPD78P322 68 PIN CERAMIC WQFN A L K B Q P S C 68 1 D U T Y G F E H I M J R X68KW-50A-1 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 24.13 ± 0.4 0.950 ± 0.016 B 21.5 0.846 C 21.5 0.846 D 24.13 ± 0.4 0.950 ± 0.016 E 1.65 0.065 F 2.03 0.080 G 3.50 MAX. 0.138 MAX. H 0.64 ± 0.10 0.025+0.005 –0.004 I 0.12 0.005 J 1.27 (T.P.) 0.05 (T.P.) K 1.27 ± 0.2 0.05 ± 0.008 L 2.16 ± 0.2 0.085 ± 0.008 P R 0.2 R 0.008 Q C 1.02 C 0.04 R 1.905 0.075 S 1.905 0.075 T R 3.0 R 0.118 U 12.0 0.472 Y C 0.5 C 0.020 41 µPD78P322 9. RECOMMENDED SOLDERING CONDITIONS It is recommended that this device be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document "Semiconductor Devices Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 9-1. Soldering Conditions for Surface Mount Devices (1/2) * µPD78P322GF-3B9: 80-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions Recommended Soldering Code Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (210˚C min.), Number of times: 2 max., Maximum number of days: 7 daysNote IR35-207-2 (thereafter, 20 hours of prebaking is required at 125˚C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. VPS Package peak temperature: 215˚C, Time: 40 seconds max. (200˚C min.), Number of times: 2 max., Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125˚C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. VP15-207-2 Wave soldering Soldering bath temperature: 260˚C max., Time: 10 seconds max., Number of times: 1, Preheating temperature: 120°C max. (package surface temperature), Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125˚C). WS60-207-1 Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin) — µPD78P322GJ-5BJ: 74-pin plastic QFP (20 × 20 mm) Soldering Method Soldering Conditions Recommended Soldering Code Infrared reflow Package peak temperature: 230˚C, Time: 30 seconds max. (210˚C min.), Number of times: 1, Maximum number of days: 7 daysNote (thereafter, 10 hours of prebaking is required at 125˚C) IR30-107-1 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (200˚C min.), Number of times: 1, Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125˚C) VP15-107-1 Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin) — Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max. Caution 42 Do not use different soldering methods together (except for partial heating method). µPD78P322 Table 9-1. Soldering Conditions for Surface Mount Devices (2/2) * µPD78P322L: 68-pin plastic QFJ (950 × 950 mils) Soldering Method Soldering Conditions Recommended Soldering Code Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (210˚C min.), Number of times: 2 max., Maximum number of days: 7 daysNote (thereafter, 36 hours of prebaking is required at 125˚C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. IR35-367-2 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (200˚C min.), Number of times: 2 max., Maximum number of days: 7 daysNote VP15-367-2 (thereafter, 36 hours of prebaking is required at 125˚C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin) — Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max. Caution Do not use different soldering methods together (except for partial heating method). 43 µPD78P322 APPENDIX A. DRAWINGS OF CONVERSION SOCKETS AND RECOMMENDED FOOTPRINTS (1) EV-9200G-74 Figure A-1. Drawing of Conversion Socket (EV-9200G-74) (For reference only) A M E N O L T K J C D S R F Q B EV-9200G-74 C 1.5 1 P No.1 pin index G H I EV-9200G-74-G0 ITEM 44 MILLIMETERS INCHES A 25.0 0.984 B 20.35 0.801 C 20.35 0.801 D 25.0 0.984 E 4-C 2.8 4-C 0.11 F 1.0 0.039 G 11.0 0.433 H 22.0 0.866 I 24.7 0.972 J 5.0 0.197 K 22.0 0.866 L 24.7 0.972 M 8.0 0.315 N 7.8 0.307 O 2.5 0.098 P 2.0 0.079 Q 1.35 0.053 R 0.35 ± 0.1 0.014+0.004 –0.005 S φ 2.3 φ 0.091 T φ 1.5 φ 0.059 µPD78P322 Figure A-2. Recommended Footprint of Conversion Socket (EV-9200G-74) (For reference only) G H D E K I F J C B A EV-9200G-74-P0 ITEM MILLIMETERS A 25.7 B 21.0 INCHES 1.012 0.827 C 1.0±0.02 × 18=18.0±0.05 D +0.002 1.0±0.02 × 18=18.0±0.05 0.039+0.002 –0.001 × 0.709=0.709 –0.003 0.039+0.002 –0.001 × 0.709=0.709 +0.002 –0.003 E 21.0 0.827 F 25.7 1.012 G 11.00 ± 0.08 0.433+0.004 –0.003 H 5.00 ± 0.08 0.197+0.003 –0.004 I 0.6 ± 0.02 0.024+0.001 –0.002 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207). 45 µPD78P322 (2) EV-9200G-80 Figure A-3. Drawing of Conversion Socket (EV-9200G-80) (For reference only) N B O P S G R A M U L K D C E T F EV-9200G-80 1 Q No.1 pin index H I J EV-9200G-80-G0 ITEM 46 MILLIMETERS INCHES A 25.0 0.984 B 20.30 0.799 C 4.0 0.157 D 14.45 0.569 E 19.0 0.748 F 4-C 2.8 4-C 0.11 G 0.8 0.031 H 11.0 0.433 I 22.0 0.866 J 24.7 0.972 K 5.0 0.197 L 16.2 0.638 M 18.9 0.744 O 8.0 0.315 N 7.8 0.307 P 2.5 0.098 Q 2.0 0.079 R 1.35 0.053 S 0.35 ± 0.1 0.014+0.004 –0.005 T φ 2.3 φ 0.091 U φ 1.5 φ 0.059 µPD78P322 Figure A-4. Recommended Footprint of Conversion Socket (EV-9200G-80) (For reference only) G J H I D E F L K M C B A EV-9200G-80-P0 ITEM MILLIMETERS A 25.7 B 21.0 INCHES 1.012 0.827 C 0.8±0.02 × 23=18.4±0.05 D +0.003 0.8±0.02 × 15=12.0±0.05 0.031+0.002 –0.001 × 0.591=0.472 –0.002 0.031+0.002 –0.001 × 0.906=0.724 +0.003 –0.002 E 15.2 0.598 F 19.9 0.783 G 11.00 ± 0.08 0.433+0.004 –0.003 H 5.50 ± 0.03 0.217+0.001 –0.002 I 5.00 ± 0.08 0.197+0.003 –0.004 J 2.50 ± 0.03 0.098+0.002 –0.001 K 0.5 ± 0.02 0.02+0.001 –0.002 L φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 M φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207). 47 µPD78P322 * APPENDIX B. TOOLS B.1 Development Tools The following development tools are readily available to support development of systems using the µPD78P322: Language Processor 78K/III Series Relocatable assembler common to the 78K/III series. Since it contains the macro function, the relocatable assembler development efficiency can be improved. A structured assembler which enables you to explicity (RA78K/III) describe program control structure is also attached and program productivity and maintenance can be improved. Host machine Ordering code OS PC-9800 series IBM PC/AT TM TM MS-DOS PC DOS TM Supply medium (product name) 3.5-inch 2HD µS5A13RA78K3 5-inch 2HD µS5A10RA78K3 3.5-inch 2HC µS7B13RA78K3 5-inch 2HC µS7B10RA78K3 HP9000 series 700TM HP-UXTM DAT µS3P16RA78K3 SPARCstationTM SunOSTM Cartridge tape µS3K15RA78K3 (QIC-24) µS3R15RA78K3 and compatible machine TM TM NEWS NEWS-OS 78K/III Series C compiler common to the 78K/III series. This is a program to convert a program written in C C compiler language into an object code executable with a microcontroller. When using the compiler, (CC78K/III) 78K/III series relocatable assembler (RA78K/III) is necessary. Host machine PC-9800 series IBM PC/AT TM Ordering code OS Supply medium (product name) MS-DOS 3.5-inch 2HD µS5A13CC78K3 5-inch 2HD µS5A10CC78K3 3.5-inch 2HC µS7B13CC78K3 PC DOS 5-inch 2HC µS7B10CC78K3 HP9000 series 700 HP-UX DAT µS3P16CC78K3 SPARCstation SunOS Cartridge tape µS3K15CC78K3 NEWS NEWS-OS (QIC-24) µS3R15CC78K3 and compatible machine Remark The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under the operating systems listed above. 48 µPD78P322 PROM Write Tools Hard- PG-1500 ware PG-1500 is a PROM programmer which enables you to program single chip microcontrollers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. UNISITE PROM programmer manufactured by Data I. O. Japan. 2900 PA-78P322GF PROM programmer adapters to write programs onto the µPD78P322 on a general PA-78P322GJ purpose PROM programmer such as PG-1500. PA-78P322K PA-78P322GF ... µPD78P322GF PA-78P322KC PA-78P322GJ ... µPD78P322GJ PA-78P322KD PA-78P322K ... µPD78P322K PA-78P322L PA-78P322KC ... µPD78P322KC PA-78P322KD ... µPD78P322KD PA-78P322L ... µPD78P322L Soft- PG-1500 controller ware Connects PG-1500 and a host machine by a serial or parallel interface and controlls PG-1500 on the host machine. Host machine Ordering code OS Supply medium (product name) PC-9800 series MS-DOS 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 IBM PC/AT PC DOS 3.5-inch 2HD µS7B13PG1500 5-inch 2HC µS7B10PG1500 and compatible machine Remark The operation of the PG-1500 controller is guaranteed only on the host machine under the operating systems listed above. 49 µPD78P322 Debugging Tools Hard- IE-78327-R ware IE-78320-R IE-78327-R and IE-78320-R are in-circuit emulators that can be used for application Note system development and debugging. Connect a host machine for debugging. IE-78327-R can be used in common for the µPD78322 subseries and the µPD78328 subseries. IE-78320-R can be used for the µPD78322 subseries. EP-78320GF-R Emulation probe to connect IE-78327-R or IE-78320-R to the target system. EP-78320GJ-R EP-78320GF-R ................. 80-pin plastic QFP EP-78320L-R EP-78320GJ-R .................. 74-pin plastic QFP EP-78320L-R .................... 68-pin plastic QFJ Soft- IE-78327-R Program to control IE-78327-R on a host machine. Automatic execution of commands, ware control program etc., is enabled for more efficient debugging. (IE controller) Host machine PC-9800 series IBM PC/AT Ordering code OS Supply medium (product name) MS-DOS 3.5-inch 2HD µS5A13IE78327 5-inch 2HD µS5A10IE78327 3.5-inch 2HC µS7B13IE78327 5-inch 2HC µS7B10IE78327 PC DOS and compatible machine IE-78320-R Program to control IE-78320-R on a host machine. Automatic execution of commands, control program Note etc., is enabled for more efficient debugging. (IE controller) Host machine PC-9800 series IBM PC/AT Ordering code OS Supply medium (product name) MS-DOS 3.5-inch 2HD µS5A13IE78320 5-inch 2HD µS5A10IE78320 5-inch 2HC µS7B10IE78320 PC DOS and compatible machine Remarks 1. The operation of the IE controller is guaranteed only on the host machine under the operating systems listed above. 2. µPD78322 subseries: µPD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1), 78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2) µPD78328 subseries: µPD78327, 78328, 78P328, 78327(A), 78328(A) Note Conventional IE-78320-R is a maintenance product. When purchasing a new incircuit emulator, use an alternative product IE-78327-R. 50 Development Tool Configuration Host machine PC-9800 series or IBM PC/AT RS-232-C Emulation probe Software IE-78327-R In-circuit emulator Relocatable assembler PG-1500 IE controller controller (with structured assembler) On-chip PROM version µPD78P322GF µPD78P322GJ µPD78P322L + + Programmer adapter RS-232C PROM programmer EP-78320GF-R EP-78320L-R EP-78320GJ-R + + Socket to connect emulation probe and target systemNote PG-1500 EV-9200G-80 EV-9200G-74 Socket for plastic QFJ µPD78P322K µPD78P322KC µPD78P322KD + Target system PA-78P322GF PA-78P322GJ PA-78P322L µPD78P322K µPD78P322KC µPD78P322KD The socket is attached to the emulation probe. Remarks The host machine and PG-1500 can be connected directly by RS-232-C. 51 µPD78P322 Note µPD78P322 B.2 Evaluation Tools The following evaluation tools are provided to evaluate the µPD78P322 function: Ordering Code Host Machine Function PC-9800 series The µPD78P322 function can be easily evaluated by connecting the evaluation tool to (product name) EB-78320-98 a host machine. The EB-78320-98/PC command system basically is compliant with the EB-78320-PC IBM PC/AT IE-78327-R or IE-78320-R command system. Thus, easy transition to application system and compatible development process by IE-78327-R or IE-78320-R can be made. The evaluation tools machine enable turbo access manager (µPD71P301)Note to be mounted on the printed circuit board. Note Turbo access manager (µPD71P301) is available for maintenance purpose only. Cautions 1. 2. EB-78320-98/PC is not the µPD78P322 application system development tool. EB-78320-98/PC does not contain the emulation function at internal PROM execution of the µPD78P322. B.3 Embedded Software The following embedded software products are readily available to support more efficient program development and maintenance: Real-time OS Real-time OS The purpose of RX78K/III is to realize a multi-task environment in a control area which requires (RX78K/III) real-time processing. RX78K/III allocates idle times of CPU to other processing to improve overall performance of the system. RX78K/III provides a system call based on the µITRON specification. RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to prepare multiple information tables. Host machine PC-9800 series IBM PC/AT and compatible machine Ordering code OS Supply medium (product name) MS-DOS 3.5-inch 2HD µS5A13RX78320 5-inch 2HD µS5A10RX78320 3.5-inch 2HC µS7B13RX78320 5-inch 2HC µS7B10RX78320 PC DOS Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the User's Agreement. Remark When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary. 52 µPD78P322 Fuzzy Inference Development Support System Fuzzy Knowledge Data Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), Preparation Tool input/editing (edit), and evaluation (simulation). (FE9000, FE9200) Host machine Ordering code OS Supply medium (product name) PC-9800 series MS-DOS 3.5-inch 2HD µS5A13FE9000 5-inch 2HD µS5A10FE9000 IBM PC/AT PC DOS WindowsTM 3.5-inch 2HC and compatible machine Translator (FT78K3) Note 5-inch 2HC µS7B13FE9200 µS7B10FE9200 Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to the assembler source program for the RA78K/III. Host machine PC-9800 series IBM PC/AT Ordering code OS Supply medium (product name) MS-DOS 3.5-inch 2HD µS5A13FT78K3 5-inch 2HD µS5A10FT78K3 3.5-inch 2HC µS7B13FT78K3 5-inch 2HC µS7B10FT78K3 PC DOS and compatible machine Fuzzy Inference Module Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge (FI78K/III)Note data converted by translator. Host machine Ordering code OS Supply medium (product name) PC-9800 series MS-DOS 3.5-inch 2HD µS5A13FI78K3 5-inch 2HD µS5A10FI78K3 IBM PC/AT PC DOS 3.5-inch 2HC µS7B13FI78K3 5-inch 2HC µS7B10FI78K3 and compatible machine Fuzzy Inference Debugger Support software evaluating and adjusting fuzzy knowledge data at hardware level by using (FD78K/III) in-circuit emulator. Host machine Ordering code OS Supply medium (product name) PC-9800 series MS-DOS 3.5-inch 2HD µS5A13FD78K3 5-inch 2HD µS5A10FD78K3 IBM PC/AT PC DOS 3.5-inch 2HC µS7B13FD78K3 5-inch 2HC µS7B10FD78K3 and compatible machine Note Under development 53 µPD78P322 [MEMO] 54 µPD78P322 NOTES FOR CMOS DEVICES (1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. QTOP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. 55 µPD78P322 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: µPD78P322K, 78P322KC, 78P322KD The customer must judge the need for license: µPD78P322GF-3B9, 78P322GJ-5BJ, 78P322L No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11