DATA SHEET MOS INTEGRATED CIRCUIT µ PD8871 10680 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD8871 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD8871 has 3 rows of 10680 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : 10680 pixels × 3 • Photocell pitch : 4 µm • Photocell size : 4 × 4 µm • Line spacing : 32 µ m (8 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side) 2 7 1200 dpi US letter (8.5” × 11”) size (shorter side) : • Drive clock level : CMOS output under 5 V operation • Data rate : 10 MHz Max. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits :: Voltage amplifiers ORDERING INFORMATION Part Number µ PD8871CY Package CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15329EJ2V0DS00 (2nd edition) Date Published September 2002 NS CP (K) Printed in Japan The mark shows major revised points. 2001 µ PD8871 BLOCK DIAGRAM GND GND φ2 φ1 29 1 16 22 19 30 CCD analog shift register 31 2 32 17 φ TG2 (Green) 15 φ TG3 (Red) D66 D67 S10679 S10680 D65 φTG1 (Blue) D66 D67 Photocell (Green) S10679 S10680 D65 ······ D64 S1 S2 Transfer gate CCD analog shift register D66 D67 Photocell (Red) S10679 S10680 D65 ······ D64 S1 S2 Transfer gate D14 VOUT3 (Red) Photocell (Blue) 18 CCD analog shift register D14 VOUT2 (Green) ······ D64 S1 S2 Transfer gate D14 VOUT1 (Blue) VOD 2 4 3 11 14 φ CLB φ RB φ 1L φ2 φ1 Data Sheet S15329EJ2V0DS µ PD8871 PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) • µ PD8871CY 32 VOUT3 Output signal 3 (Red) Reset feed-through level clamp clock φ CLB 2 31 VOUT2 Output signal 2 (Green) Last stage shift register clock 1 φ 1L 3 30 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 4 29 VOD Output drain voltage No connection NC 5 28 NC No connection Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection No connection NC 8 25 NC No connection No connection NC 9 24 NC No connection No connection NC 10 23 NC No connection Shift register clock 2 φ2 11 22 φ2 Shift register clock 2 Internal connection IC 12 21 IC Internal connection Internal connection IC 13 20 IC Internal connection Shift register clock 1 φ1 14 19 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 15 18 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 16 17 φ TG2 Transfer gate clock 2 (for Green) Blue 10680 Green 10680 Red 10680 1 1 1 GND 1 Ground Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Data Sheet S15329EJ2V0DS 3 µ PD8871 PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 4 µm 4 µm 2 µm Blue photocell array 2 µm 8 lines (32 µm) Channel stopper 4 µm Green photocell array 8 lines (32 µm) Aluminum shield 4 4 µm Data Sheet S15329EJ2V0DS Red photocell array µ PD8871 ABSOLUTE MAXIMUM RATINGS (TA = +25°°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2, Vφ 1L −0.3 to +8 V Reset gate clock voltage Vφ RB −0.3 to +8 V Reset feed-through level clamp Vφ CLB −0.3 to +8 V Vφ TG1 to Vφ TG3 −0.3 to +8 V clock voltage Transfer gate clock voltage Note Operating ambient temperature TA 0 to +60 °C Storage temperature Tstg −40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°°C) Min. Typ. Max. Unit Output drain voltage Parameter VOD Symbol 11.4 12.0 12.6 V Shift register clock high level Vφ 1H, Vφ 2H, Vφ 1LH 4.75 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L, Vφ 1LL −0.3 0 +0.25 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.5 V Reset feed-through level clamp clock Vφ CLBH 4.5 5.0 5.5 V Vφ CLBL −0.3 0 +0.5 V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.75 Vφ 1H Transfer gate clock low level Vφ TG1L to Vφ TG3L −0.3 0 +0.15 V Data rate fφ RB − 2.0 10.0 MHz high level Reset feed-through level clamp clock low level Note Note Vφ 1H V Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H), Image lag can increase. Data Sheet S15329EJ2V0DS 5 µ PD8871 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Min. Typ. Max. Unit Vsat 2.5 3.2 − V Red SER − 0.889 − lx•s Green SEG − 0.970 − lx•s Blue SEB − 1.455 − lx•s Saturation voltage Saturation exposure Test Conditions Photo response non-uniformity PRNU VOUT = 1.0 V − 6 20 % Average dark signal ADS Light shielding − 0.2 4.0 mV Dark signal non-uniformity DSNU Light shielding − 1.0 4.0 mV Power consumption PW − 360 540 mW Output impedance ZO − 0.30 1.00 kΩ Red RR 2.52 3.60 4.68 V/lx•s Green RG 2.31 3.30 4.29 V/lx•s Blue RB 1.54 2.20 2.86 V/lx•s − 1.0 7.0 % 4.5 6.0 7.5 V Response Image lag Offset level IL Note 1 Output fall delay time VOUT = 1.0 V VOS Note 2 td VOUT = 1.0 V, (t1’) = 5 ns − 25 − ns TTE VOUT = 1.0 V, data rate = 10 MHz 92 98 − % Red − 630 − nm Green − 540 − nm Total transfer efficiency Response peak − 460 − nm DR1 Vsat/DSNU − 3200 − times DR2 Vsat/σ CDS − 3200 − times RFTN Light shielding −2000 +100 +1000 mV σ CDS Light shielding − 1.0 − mV Blue Dynamic range Reset feed-through noise Random noise (CDS) Note 1 Notes 1. Refer to TIMING CHART 2, 3. 2. When the fall time of φ 1L (t1’) is the Typ. value (refer to TIMING CHART 2, 3). 6 Data Sheet S15329EJ2V0DS µ PD8871 INPUT PIN CAPACITANCE (TA = +25°°C, VOD = 12 V) Parameter Symbol Shift register clock pin capacitance 1 Cφ 1 Shift register clock pin capacitance 2 Cφ 2 Pin φ1 φ2 Pin No. Min. Typ. Max. Unit 14 − 450 − pF 19 − 450 − pF 11 − 450 − pF 22 − 450 − pF Last stage shift register clock pin capacitance Cφ L φ 1L 3 − 10 − pF Reset gate clock pin capacitance Cφ RB φ RB 4 − 10 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 2 − 10 − pF Transfer gate clock pin capacitance Cφ TG φ TG1 18 − 100 − pF φ TG2 17 − 100 − pF φ TG3 15 − 100 − pF Remark Pin 14 and 19 (φ 1), 11 and 22 (φ 2) are each connected inside of the device. Data Sheet S15329EJ2V0DS 7 8 TIMING CHART 1 (for each color) φ TG1 to φ TG3 φ 1, φ 1L φ2 Note Note φ CLB (Bit clamp mode) 10743 10744 10745 10746 10747 10748 10749 61 62 63 64 65 66 φ CLB (Line clamp mode) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Sheet S15329EJ2V0DS φ RB VOUT1 to VOUT3 Optical black (48 pixels) Valid photocell (10680 pixels) Invalid photocell (3 pixels) And stop the φ RB pulse while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. µ PD8871 Note Set the φ RB pulse to high level during the φ TG1 to φ TG3 pulse. Invalid photocell (3 pixels) µ PD8871 TIMING CHART 2 (Bit clamp mode, for each color) t1 t2 90% φ1 10% 90% φ2 10% t1' 90% φ 1L 10% t5 φ RB t2' t6 t3 t4 90% 10% t9 t7 t8 t10 t11 90% φ CLB 10% td RFTN VOUT VOS 10% Symbol Min. Typ. Max. Unit 0 25 − ns t1, t2 t1’, t2’ 0 5 − ns t3 20 100 − ns t4 40 150 − ns t5, t6 0 25 − ns −5 Note 25 − ns t8 20 100 − ns t9, t10 0 25 − ns t11 10 25 − ns t7 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S15329EJ2V0DS 9 µ PD8871 TIMING CHART 3 (Line clamp mode, for each color) t1 t2 90% φ1 10% 90% φ2 10% t1' 90% φ 1L 10% t5 t6 t3 t4 90% φ RB φ CLB t2' 10% "H" td RFTN VOUT VOS 10% Symbol t1, t2 10 Min. Typ. Max. Unit 0 25 − ns t1’, t2’ 0 5 − ns t3 20 100 − ns t4 40 150 − ns t5, t6 0 25 − ns Data Sheet S15329EJ2V0DS µ PD8871 φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART t13 t14 t12 90% 10% t15 φ TG1 to φ TG3 t16 90% φ 1, φ 1L φ2 90% φ 1, φ 1L t17 Note 1 t18 90% φ RB t7 t11 90% φ CLB (Bit clamp mode) t20 t22 t21 Note 2 t23 90% 10% φ CLB (Line clamp mode) t9 Symbol Min. −5 t7 t9, t10 Note 3 0 t19 t10 Typ. Max. Unit 25 − ns 25 − ns t11 10 25 − ns t12 5000 10000 50000 ns t13, t14 0 50 − ns t15, t16 900 1000 − ns t17, t18 200 400 − ns t19 t12 t12 50000 ns t20, t21 0 50 − ns t22, t23 0 350 − ns Notes 1. Set the φ RB pulse to high level during this period. 2. Stop the φ RB pulse during this period. 3. Min. of t7 shows that the φ RB and φ CLB overlap each other. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. φ 1, φ 2 cross points φ2 φ1 2 V or more 2 V or more φ 1L, φ 2 cross points φ2 φ 1L 2 V or more 0.5 V or more Remark Adjust cross points (φ 1, φ 2) and (φ 1L, φ 2) with input resistance of each pin. Data Sheet S15329EJ2V0DS 11 µ PD8871 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x 10680 Σx x= j j=1 10680 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 10680 Σd ADS (mV) = j j=1 10680 dj : Dark signal of valid pixel number j 12 Data Sheet S15329EJ2V0DS µ PD8871 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 10680 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT Data Sheet S15329EJ2V0DS 13 µ PD8871 9. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) i 2 i=1 100 , V= 1 100 Σ VCDS 100 i = 1 Reset feed-through Video output 14 Data Sheet S15329EJ2V0DS i µ PD8871 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 1 Relative Output Voltage 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R G B 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S15329EJ2V0DS 15 µ PD8871 APPLICATION CIRCUIT EXAMPLE +5 V + µ PD8871 1 10 µ F/16 V 0.1 µ F 47 Ω φ CLB 150 Ω φ 1L 47 Ω φ RB 2 3 4 32 GND VOUT3 φ CLB VOUT2 φ 1L VOUT1 φ RB VOD NC NC IC IC IC IC NC NC 26 NC NC NC NC φ2 φ2 IC IC IC IC φ1 φ1 16 22 φ TG 4.7 Ω 20 φ TG3 φ TG1 GND φ TG2 19 4.7 Ω 18 4.7 Ω 17 4.7 Ω Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. Connect the No connection pins (NC) to GND. Data Sheet S15329EJ2V0DS 10 µ F/16 V φ1 21 16 2. 0.1 µ F 23 13 Cautions 1. + 24 12 15 47 µ F/25 V +5 V 25 10 4.7 Ω 0.1 µ F 27 9 14 + 28 8 4.7 Ω B1 29 7 11 B2 30 6 4.7 Ω +12 V 31 5 φ2 B3 µ PD8871 Remarks 1. B1 to B3 in the application circuit example are shown in the figure below. B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 100 Ω 47 µ F/25 V 2SC945 2 kΩ 2. Number and type of inverters in the application circuit example are different by data rate. The following table shows the recommended number and type of inverters for data rate. Pin Name Pin No. Data Rate (MHz) Inverter Type Number (each pin) φ CLB 2 (data rate) < 10 74HC04 1 φ 1L 3 (data rate) < 2 74HC04 1 2 ≤ (data rate) < 10 74AC04 1 (data rate) < 10 74HC04 1 φ RB 4 φ 1, φ 2 14, 19, 11, 22 φ TG1 to φ TG3 18, 17, 15 (data rate) < 2 74HC04 1 2 ≤ (data rate) < 6 74AC04 1 6 ≤ (data rate) < 10 74AC04 3 (data rate) < 10 74HC04 1 Data Sheet S15329EJ2V0DS 17 µ PD8871 PACKAGE DRAWING µ PD8871CY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 55.2±0.5 54.8±0.5 1st valid pixel 6.15±0.3 1 1 9.25±0.3 17 9.05±0.3 32 16 46.7 2.0 12.6±0.5 4.1±0.5 10.16±0.20 4.55±0.5 1.02±0.15 (1.80) 2 2.58±0.3 0.46±0.1 2.54±0.25 0.25±0.05 (5.42) 4.21±0.5 3 10.16 +0.7 −0.2 Name Dimensions Refractive index Plastic cap 52.2×6.4×0.7 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 32C-1CCD-PKG5-1 18 Data Sheet S15329EJ2V0DS µ PD8871 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD8871CY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin) Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S15329EJ2V0DS 19 µ PD8871 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Symbol Ethyl Alcohol Methyl Alcohol EtOH MeOH Isopropyl Alcohol N-methyl Pyrrolidone IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. 3. 4. 5. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. 20 Data Sheet S15329EJ2V0DS µ PD8871 [MEMO] Data Sheet S15329EJ2V0DS 21 µ PD8871 [MEMO] 22 Data Sheet S15329EJ2V0DS µ PD8871 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15329EJ2V0DS 23 µ PD8871 • The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4