SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993
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54AC11533 . . . JT PACKAGE
74AC11533 . . . DW OR NT PACKAGE
8-Latches in a Single Package
3-State Bus-Driving Inverting Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OC
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
C
54AC11533 . . . FK PACKAGE
description
(TOP VIEW)
3D
4D
VCC
NC
VCC
5D
6D
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
2D
1D
OC
NC
1Q
2Q
3Q
4
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
7D
8D
C
NC
8Q
7Q
6Q
4Q
GND
GND
NC
GND
GND
5Q
The eight latches of the ′AC11533 are transparent
D-type latches. While the enable (C) is high, the
Q outputs will follow the complements of the (D)
inputs. When the output control OC is taken low,
the Q outputs will be latched. The ′AC11533 is
functionally equivalent to the ′AC11373 except for
having inverted outputs.
5
A buffered output-control (OC) input can be used
NC − No internal connection
to place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive
provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up
components.
The output control (OC) does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off.
The 54AC11533 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC11533 is characterized for operation from − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
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•
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•
2−1
SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993
FUNCTION TABLE
(each latch)
INPUTS
OC
C
D
OUTPUT
Q
L
H
H
L
L
H
L
H
L
L
X
Q0
H
X
X
Z
logic symbol†
OC
C
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
logic diagram (positive logic)
EN
OC
C1
C
1D
1
2
21
3
20
4
17
9
16
10
15
11
14
12
1Q
1D
2Q
3Q
2D
4Q
24
13
23
22
5Q
6Q
3D
7Q
8Q
4D
21
20
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5D
6D
7D
8D
17
16
15
14
C1
1
1D
C1
2
1D
C1
3
1D
C1
4
1D
C1
9
1D
C1
10
1D
C1
11
1D
C1
1D
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
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SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993
recommended operating conditions
54AC11533
VCC
Supply voltage
VIH
High-level input voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
MAX
3
5
5.5
Low-level output current
Dt /Dv
Input transition rise or fall rate
TA
Operating free-air temperature
MIN
NOM
MAX
3
5
5.5
2.1
2.1
3.15
3.15
3.85
3.85
VCC = 3 V
VCC = 4.5 V
UNIT
V
V
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
High-level output current
IOL
NOM
0
Output voltage
IOH
MIN
VCC = 4.5 V
VCC = 5.5 V
Input voltage
74AC11533
0
VCC
VCC
0
−4
−4
− 24
− 24
VCC = 5.5 V
VCC = 3 V
−24
−24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
V
V
V
mA
mA
0
10
0
10
ns/ V
−55
125
− 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 mA
VOH
IOH = − 4 mA
IOH = − 24 mA
VOL
VCC
MIN
TA = 25°C
TYP
MAX
54AC11533
MIN
MAX
74AC11533
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MAX
V
IOH = − 50 mA{
IOH = − 75 mA{
5.5 V
3V
0.1
0.1
0.1
IOL = 50 mA
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3.85
5.5 V
IOL = 12 mA
IOL = 24 mA
UNIT
3.85
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA{
IOL = 75 mA{
5.5 V
IOZ
II
VO = VCC or GND
VI = VCC or GND
5.5 V
± 0.5
± 10
±5
mA
5.5 V
± 0.1
±1
±1
mA
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
5.5 V
8
160
80
mA
1.65
5.5 V
IO = 0
1.65
5V
4
Co
VO = VCC or GND
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
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•
pF
pF
2−3
SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993
timing requirements (see Figure 1)
TA = 25°C
MIN
MAX
VCC
RANGE
3.3 ± 0.3 V
tw
Pulse duration, C high
tsu
Setup time, data before C
th
Hold time, data after C↓
5 ± 0.5 V
3.3 ± 0.3 V
54AC11533
MIN
MAX
74AC11533
MIN
5.5
5.5
5.5
4
4
4
4
4
4
3.5
3.5
3.5
3.3 ± 0.3 V
2
2
2
5 ± 0.5 V
2
2
2
5 ± 0.5 V
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
C
Any Q
tPZH
tPZL
OC
Any Q
tPHZ
tPLZ
OC
Any Q
MIN
TA = 25°C
TYP
MAX
54AC11533
74AC11533
MIN
MAX
MIN
MAX
1.5
8.5
12.6
1.5
15.2
1.5
14.3
1.5
7.5
10.1
1.5
12
1.5
11.3
1.5
10
14.5
1.5
17.6
1.5
16.5
1.5
9.5
12.8
1.5
15.2
1.5
14.3
1.5
9
13.1
1.5
15.7
1.5
14.7
1.5
8.5
11.6
1.5
14.1
1.5
13.1
1.5
9.5
12
1.5
13.2
1.5
12.8
1.5
7.5
10.2
1.5
11.4
1.5
11
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
C
Any Q
tPZH
tPZL
OC
Any Q
tPHZ
tPLZ
OC
Any Q
MIN
TA = 25°C
TYP
MAX
54AC11533
74AC11533
MIN
MAX
MIN
MAX
1.5
5.5
8.4
1.5
10.6
1.5
9.8
1.5
5
7.1
1.5
8.6
1.5
8
1.5
6.5
10
1.5
12.1
1.5
11.3
1.5
6.5
9.1
1.5
11
1.5
10.3
1.5
6.5
9.5
1.5
11.7
1.5
10.8
1.5
6
8.6
1.5
10.9
1.5
9.7
1.5
8.5
10.7
1.5
11.7
1.5
11.4
1.5
6
8.2
1.5
9.3
1.5
8.9
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
2−4
Power dissipation capacitance per latch
Outputs disabled
•
UNIT
55
CL = 50 pF,
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•
TYP
f = 1 MHz
44
pF
SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
Timing Input
(see Note B)
VCC
50%
Input
(see Note B)
50%
0V
tPHL
0V
tPLH
th
tsu
Data Input
VCC
50%
VCC
50%
50% VCC
Output
50%
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VOLTAGE WAVEFORMS
VCC
50%
50%
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
VOL
50% VCC
tPZH
[ VCC
20% VCC
VOL
tPHZ
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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2−5
SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993
2−6
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•
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74AC11533DW
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
74AC11533NT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
74AC11533NT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
74AC11533NT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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