Qualification Report January 1992 QTP 90172 256 x 4 Static RAM MARKETING PART NBR DEVICE DESCRIPTION CY7C122 SIO Version 1.1 PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied: Marketing Part #: CY7C122 Device Description: 256 X 4 Static RAM, Separate I/O Cypress Division: Cypress Semiconductor Overall Die (or Mask) REV Level (pre-requisite for qualification): Die Size (stepping): 54 mil x 113 mil A What ID markings on Die: 7C122A Cypress Qualification completion/Marketing Availability Dates (Current REV): 1991 Now DIE/FAB DESCRIPTION Number of Metal Layers: 1 Metal Composition: Passivation Type and Materials: 1200Å Ti, 9000Å 1%SiAl 4KÅ 2%P LTO, + 15KÅ Oxynitride Free Phosphorus contents in top glass layer(%): Die Coating(s), if used: 2% None Generic Process Technology/Design Rule (µ-drawn): CMOS, Double Poly, Single Metal / 1.2µm Gate Oxide Material/Thickness (MOS): SiO2 / 245Å Name/Location of Die Fab (prime) Facility: Cypress Semiconductor / Round Rock, TX Die Fab Line ID/Wafer Process ID: Fab 2 / R13 PLASTIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 22-pin, 400 mil Plastic DIP Die to Package edge clearance: 173 mil / side Mold Compound Name/Manufacturer: Lead Frame material: Sumitomo EME-6300H(R) Copper Lead Finish, composition: Solder, 63%Sn 37%Pb Die Attach Area Plating: Silver Die Attach Pad Dim: 140 X 170 Die Attach Method: Epoxy Die Attach Material: Silver Epoxy Wire Bond Method: Thermocompression Wire Material/Size: Gold / 1.3 mil Name/Location of Assembly (prime) facility: Cypress Semiconductor, San Jose, CA Assembly Line ID and Process ID: Cypress Semiconductor/ P27 CYPRESS SEMICONDUCTOR PAGE 3 HERMETIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 22-pin, 400 mil Ceramic DIP Die to Package edge clearance: 173 mil / side Mold Compound Name/Manufacturer: Lead Frame material: N/A Alloy-42 Lead Finish, composition: Solder, 63%Sn 37%Pb Die Attach Area Plating: Aluminum Die Attach Pad Dim: 180 X 210 Die Attach Method: Paste Die Attach Material: Silver Glass Wire Bond Method: Ultrasonic Wire Material/Size: Aluminum / 1.25 mil Name/Location of Assembly (prime) facility: Cypress Semiconductor, San Jose, CA Assembly Line ID and Process ID: Cypress Semiconductor / D2 CYPRESS SEMICONDUCTOR PAGE 4 OTHER INFORMATION For approval by similarity, identify other devices using the same basic die with bonding or metal mask options or test selections and explain: CY7C122, CY9122, CY91L22, CY93422, CY93L422 -- Test paramaters options If Cypress is planning any changes in the near future, identify change (Qtr/Yr) in: Die Design Rev./Shrink/Date None Die Process Change/Date: None Fab/Assembly site change/Date None Cross Licensee/Licensor : None ESD Voltage Rating (per MIL STD-008, Method 3018): >2000V Flammability Classification (UL-94V): UL-94V0 1/8 Alternate Fab/Assembly Locations: Fab: San Jose, CA (Fab 1) Assembly: Omedata Corporation, Indonesia Please attach the following Qualification / Reliability data for the die revision and Package type, for the fab and assembly sites identified above (mark [X] if included): 1 X H A S T (130°C/85%RH) 7 X Operating Life at (temp): 2 X Temperature Cycle (-65°C to 150°C) 8 Latchup Testing 3 Data Retention Bake, Plastic (185°C) 9 Other: 4 Data Retention Bake, Hermetic (250°C) 10 Other: 5 X Autoclave (PCT, 130°C, 100%RH) 11 Other: 6 X ESD Tests (MIL-STD 883, method 3015) 12 Other: 150°C CYPRESS SEMICONDUCTOR PAGE 5 PRODUCT INFORMATION FOR QUALIFICATION BY SIMILARITY Product Family: 1K Static RAM Mfg Division: San Jose, CA Supplier's Part Number Rated Pkg Size/ Die Speed Type Revision /ID Die Size mil x mil Design Rule (µ µ) Fabrication Passivatio Mold Assembly n Type Compound Line Location ESD Volt Rating Availability (mm/yy) Process Line ID ID CY7C122 -xxPC -xxDC -xxDMB 15ns to 45ns 22.4 PDIP 22.4 CDIP 22.4 CDIP 7C122A 54 x 113 1.2µ R13 CMOS 2 1* 2%P LTO + Oxynitride Sumitomo San Jose, CA >2000V Now CY9122 -xxPC -xxDC -xxDMB 15ns to 45ns 22.4 PDIP 22.4 CDIP 22.4 CDIP 7C122A 54 x 113 1.2µ R13 CMOS 2 1* 2%P LTO + Oxynitride Sumitomo San Jose, CA >2000V Now CY91L22 -xxPC -xxDC -xxDMB 25ns to 45ns 22.4 PDIP 22.4 CDIP 22.4 CDIP 7C122A 54 x 113 1.2µ R13 CMOS 2 1 2%P LTO + Oxynitride Sumitomo San Jose, CA >2000V Now CY93422 PC APC DC ADC DMB ADMB 35ns 22.4 PDIP 22.4 PDIP 22.4 CDIP 22.4 CDIP 22.4 CDIP 22.4 CDIP 22.4 PDIP 22.4 PDIP 22.4 CDIP 22.4 CDIP 22.4 CDIP 22.4 CDIP 7C122A 54 x 113 1.2µ R13 CMOS 2 1 2%P LTO + Oxynitride Sumitomo San Jose, CA >2000V Now CY93L422PC APC DC ADC DMB ADMB NOTE: "xx" replaces all speed grades for device. Options for 7C122 are 15ns, 25ns, 35ns, and 45ns Military grade starts at 25ns (xMB) for 7C122 AND 9122 and 35ns for 91L22, 93422, and 93L422. CYPRESS SEMICONDUCTOR PAGE 6 DEVICE RELIABILITY SUMMARY Marketing Part: Pkg Description: CY7C122 22-pin 400 mil PDIP Wafer Fab: Assembly: Fab 2, San Jose, CA San Jose, CA High Temperature Dynamic Operating Life (HTOL, 5.75V, 150°C) Device Lot# 24 Hours Cumulative 7C122 2026786 6/19751 6/1975 High Temperature Dynamic Operating Life (HTOL, 5.75V, 150°C), LFR Device Lot# 80 Hours 500 Hours Cumulative 7C122 2026786 0/343 0/341 0/341 Temperature Cycle (Condition C, -65°C to 150°C) Device Lot# 100 cycles 500 Cycles Cumulative 7C122 2026786 0/76 0/76 0/76 Pressure Cooker (PCT, Unbiased, 130°C, 100%RH, Device Lot# 96 Hours 288 Hours Cumulative 7C122 2026786 0/76 0/76 0/76 High Accelerated Saturation Test (HAST, Unbiased, 130°C, 85%RH, 15psig) 1 Device Lot# 100 Hours Cumulative 7C122 2026786 0/76 0/76 EOS(5), ESD(1) CYPRESS SEMICONDUCTOR PAGE 7 Device Reliability Summary 256 x 4 Static RAM CY7C122 Electrostatic Discharge Human Body Model Circuit per Mil Std 883, Method 3015 +2000 Unit 1 -2000 +2000 Unit 2 -2000 +2000 Unit 3 -2000 (Highest Passing Voltage, +100% Guard-banded) CYPRESS SEMICONDUCTOR PAGE 8 CYPRESS PREVIOUS QUALIFICATION Device ID: Status: Process ID: Package: Die Attach Mat: 7C122A Prod. Family: Production R13 PDIP (Plastic) CDIP (Ceramic) Cypress Test No. Stress/Test Mask ID: Results: Passed Complete Date: Technology: CMOS Process Loc: Mold Compound: Silver Epoxy (Plastic) Silver Glass (Ceramic) 256 x 4 Static Ram Package Loc: Reference Method Sumitomo (Plastic Only) Lead Frame PDIP: San Jose, Omedata Ceramic: San Jose Actual Conditions Test Loc: Status * 7C122A 1984 Fab 1, San Jose, CA PDIP: Copper CDIP: Alloy 42 San Jose, CA Qualification Data Reference Test Result Temp/Bias Hrs/Cyc SS/Fail Pass 12 hrs 1191/0 C Reliability Monitor X 22A HTOL - EFR 150°/5.75V 22 HTOL - LFR 150°/5.75V 24 Steam Test/Autoclave/PCT 121°/100%RH 288 hrs 220/0 C Reliability Monitor X HAST 121°/85%RH 200 hrs 75/0 C Reliability Monitor X Cond. C 500 cy 55/0 C Reliability Monitor X Corner Pins Internal Pins ---- C R&D X 200mA 5/0 C R&D X 12 Temperature Cycle 34 Accelerated Soft Error Rate 20 Mechanical Sequence 26 X-Ray 6 ESD-HBM - 2000V 33 Latch-up 50 Flammability & Oxygen Index Thermal Series Group D3 Various 168/0 C QCI Inspection X Mechanical Series Group D4 Various 182/0 C QCI Inspection X 2 Solvent Resistance 4 Internal Visual 1 Physical Dimensions 3 Solderability 7 Lead Integrity 5 Bond Strength 29 Die Shear Strength 11 Lid Torque * I - Interim, C - Complete Fail