STMICROELECTRONICS STE48NM50

STE48NM50
N-CHANNEL 500V - 0.08Ω - 48A ISOTOP
MDmesh™Power MOSFET
TYPE
STE48NM50
n
n
n
n
n
n
VDSS
RDS(on)
ID
500V
< 0.1Ω
48 A
TYPICAL RDS(on) = 0.08Ω
HIGH dv/dt AND AVALANCHE CAPABILITIES
100% AVALANCHE TESTED
LOW INPUT CAPACITANCE AND GATE
CHARGE
LOW GATE INPUT RESISTANCE
TIGHT PROCESS CONTROL AND HIGH
MANUFACTURING YIELDS
DESCRIPTION
The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar competition’s products.
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
The MDmesh™ family is very suitable for increasing
power density of high voltage converters allowing
system miniaturization and higher efficiencies.
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Drain-source Voltage (VGS = 0)
500
V
Drain-gate Voltage (RGS = 20 kΩ)
500
V
Gate- source Voltage
±30
V
ID
Drain Current (continuous) at TC = 25°C
48
A
ID
Drain Current (continuous) at TC = 100°C
30
A
A
VDS
VDGR
VGS
IDM (l)
PTOT
dv/dt (1)
Tstg
Tj
Parameter
Drain Current (pulsed)
192
Total Dissipation at TC = 25°C
450
W
Derating Factor
3.6
W/°C
Peak Diode Recovery voltage slope
15
V/ns
–65 to 150
°C
150
°C
Storage Temperature
Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
September 2002
(1) ISD ≤48A, di/dt ≤400A/µs, VDD ≤ V (BR)DSS, T j ≤ TJMAX.
1/8
STE48NM50
THERMAL DATA
Rthj-case
Thermal Resistance Junction-case
Max
Rthc-sink (*) Thermal Resistance Case-sink
Typ
0.28
°C/W
0.05
°C/W
(*) with conductive GREASE Applies
AVALANCHE CHARACTERISTICS
Symbol
Parameter
Max Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
15
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
810
mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
V(BR)DSS
IDSS
IGSS
Parameter
Test Conditions
Min.
Typ.
Max.
500
Unit
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
V
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
10
µA
VDS = Max Rating, TC = 125 °C
100
µA
Gate-body Leakage
Current (VDS = 0)
VGS = ± 30V
±100
nA
ON (1)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 24A
Min.
Typ.
Max.
Unit
3
4
5
V
0.08
0.1
Ω
Typ.
Max.
Unit
DYNAMIC
Symbol
gfs (1)
Parameter
Forward Transconductance
Test Conditions
VDS > ID(on) x RDS(on)max,
ID = 24A
VDS = 25V, f = 1 MHz, VGS = 0
20
S
3700
pF
Ciss
Input Capacitance
Coss
Output Capacitance
610
pF
Crss
Reverse Transfer
Capacitance
50
pF
RG
Gate Input Resistance
1.7
Ω
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2/8
Min.
STE48NM50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
td(on)
tr
Parameter
Turn-on Delay Time
Rise Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
Test Conditions
Min.
VDD = 250V, ID = 24 A
RG = 4.7Ω VGS = 10 V
(see test circuit, Figure 3)
VDD = 400 V, ID = 48 A,
VGS = 10 V
Typ.
Max.
Unit
40
ns
35
ns
87
117
nC
23
nC
42
nC
SWITCHING OFF
Symbol
tr(Voff)
Parameter
Off-voltage Rise Time
tf
Fall Time
tc
Cross-over Time
Test Conditions
Min.
VDD = 400 V, ID = 48 A,
RG = 4.7Ω, VGS = 10 V
(see test circuit, Figure 5)
Typ.
Max.
Unit
18
ns
23
ns
44
ns
SOURCE DRAIN DIODE
Symbol
ISD
Parameter
Test Conditions
Min.
Typ.
Source-drain Current
Max.
Unit
48
A
192
A
1.5
V
ISDM (2)
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 48 A, VGS = 0
trr
Qrr
Irrm
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 40 A, di/dt = 100A/µs,
VDD = 100 V, Tj = 25°C
(see test circuit, Figure 5)
520
7.8
30
ns
µC
A
trr
Qrr
Irrm
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 40 A, di/dt = 100A/µs,
VDD = 100 V, Tj = 150°C
(see test circuit, Figure 5)
680
11.2
33
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedence
3/8
STE48NM50
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STE48NM50
Normalized Gate Thereshold Voltage vs Temp.
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STE48NM50
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STE48NM50
ISOTOP MECHANICAL DATA
mm
DIM.
MIN.
A
TYP.
11.8
inch
MAX.
MIN.
TYP.
MAX.
12.2
0.466
0.480
B
8.9
9.1
0.350
0.358
C
1.95
2.05
0.076
0.080
D
0.75
0.85
0.029
0.033
E
12.6
12.8
0.496
0.503
F
25.15
25.5
0.990
1.003
G
31.5
31.7
1.240
1.248
H
4
J
4.1
4.3
0.161
0.169
K
14.9
15.1
0.586
0.594
L
30.1
30.3
1.185
1.193
M
37.8
38.2
1.488
1.503
8.2
0.307
0.157
N
4
O
7.8
0.157
0.322
A
G
B
O
F
E
H
D
N
J
K
C
L
M
7/8
STE48NM50
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
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