100343 Low Power 8-Bit Latch General Description Features The 100343 contains eight D-type latches, individual inputs, (Dn), outputs (Qn), a common enable pin (E), and a latch enable pin (LE). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH. The 100343 outputs are designed to drive a 50Ω termination resistor to −2.0V. All inputs have 50 kΩ pull-down resistors. n n n n Low power operation 2000V ESD protection Voltage compensated operating range = −4.2V to −5.7V Available to MIL-STD-883 Logic Symbol DS100298-1 Pin Names Description D0–D7 Data Inputs E Enable Input LE Latch Enable Input Q0–Q7 Data Inputs NC No Connect © 1998 National Semiconductor Corporation DS100298 www.national.com 100343 Low Power 8-Bit Latch August 1998 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak DS100298-3 DS100298-2 Logic Diagram DS100298-5 Truth Table Inputs Outputs Dn E LE L L L L H L L H X H X Latched (Note 1) X X H Latched (Note 1) Qn H = HIGH voltage level L = LOW voltage level X = Don’t care Note 1: Retains data present before either LE or E went HIGH www.national.com 2 Absolute Maximum Ratings (Note 2) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) Case Temperature (TC) Military Supply Voltage (VEE) −65˚C to +150˚C +175˚C −7.0V to +0.5V VEE to +0.5V −50 mA ≥2000V −55˚C to +125˚C −5.7V to −4.2V Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C Symbol VOH Parameter Output HIGH Voltage Min Max Units TC −1025 −870 mV 0˚C to −1085 −870 mV −55˚C −1830 −1620 mV 0˚C to −1830 −1555 mV −55˚C −1035 mV 0˚C to +125˚C VOL Output LOW Voltage Conditions Notes VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2.0V 1, 2, 3 VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2.0V 1, 2, 3 +125˚C VOHC Output HIGH Voltage +125˚C −1085 VOLC Output LOW Voltage mV −55˚C −1610 mV 0˚C to −1555 mV −55˚C −870 mV −55˚C to +125˚C VIH Input HIGH Voltage −1165 Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4 Guaranteed LOW Signal for All Inputs 1, 2, 3, 4 VEE = −4.2V VIN = VIL (Min) VEE = −5.7V VIN = VIH (Max) 1, 2, 3 +125˚C VIL Input LOW Voltage −1830 −1475 mV −55˚C to +125˚C IIL Input LOW Current 0.50 µA −55˚C to +125˚C IIH Input HIGH Current 240 µA 0˚C to +125˚C 340 IEE µA Power Supply Current −55˚C −55˚C to −100 −35 −105 −35 mA 1, 2, 3 +125˚C Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V 1, 2, 3 Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 5: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 7: Guaranteed by applying specified input condition and testing VOH/VOL. Military Version AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dn to Output TC = −55˚C TC = +25˚C TC = +125˚C Min Max Min Max Min Max 0.50 2.70 0.50 2.30 0.50 2.80 3 Units ns Conditions Figures 1, 2, 3 Notes (Notes 8, 9, 10, 12) www.national.com Military Version AC Electrical Characteristics (Continued) VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL LE, E to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% ts Setup Time th Hold Time tpw(H) Pulse Width HIGH TC = −55˚C TC = +25˚C TC = +125˚C Min Max Min Max Min Max 0.90 3.40 1.0 3.10 1.10 3.90 ns 0.40 2.50 0.40 2.40 0.40 2.70 ns Figures 1, 3 (Note 11) Units Conditions Figures 1, 2, 3 Notes (Notes 8, 9, 10, 12) D0–D7 0.60 0.60 0.60 ns Figures 1, 4 (Note 11) D0–D7 1.50 1.50 1.70 ns Figures 1, 4 (Note 11) LE, E 2.40 2.40 2.40 ns Figures 1, 4 (Note 11) Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 9: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9. Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 11: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Note 12: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Test Circuitry DS100298-6 Note 13: VCC, VCCA = +2V, VEE = −2.5V Note 14: L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms DS100298-7 FIGURE 2. Propagation Delays www.national.com 4 Switching Waveforms (Continued) DS100298-8 FIGURE 3. Propagation and Transition Times DS100298-9 FIGURE 4. Setup, Hold and Pulse Width Times 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 24-Pin Ceramic Dual-In-Line Package (D) NS Package Number J24E 24-Lead Quad Cerpak (F) NS Package Number W24B 7 www.national.com 100343 Low Power 8-Bit Latch LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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