100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential receiver. An internal reference voltage generator provides VBB for single-ended operation, or for use in Schmitt trigger applications. All inputs have 50 kΩ pull-down resistors. When the inputs are either unconnected or at the same potential the outputs will go low. When used in single-ended operation the apparent input threshold of the true inputs is 20 mV to 40 mV higher (positive) than the threshold of the complementary inputs. The VEE and VTTL power may be applied in either order. n n n n n n n n Logic Diagram Pin/function compatible with 100125 Meets 100125 AC specifications 50% power reduction of the 100125 Differential inputs with built in offset Standard FAST ® outputs 2000V ESD protection −4.2V to −5.7V operating range Available to Microcircuit Drawing (SMD) 5962-9153101 Pin Names Description D0–D5 Data Inputs D0–D5 Inverting Data Inputs Q0–Q5 Data Outputs DS100314-4 FAST ® is a registered trademark of Fairchild Semiconductor. © 1998 National Semiconductor Corporation DS100314 www.national.com 100325 Low Power Hex ECL-to-TTL Translator August 1998 Connection Diagrams Truth Table Inputs 24-Pin DIP DS100314-1 Dn L H L H L H DS100314-2 www.national.com 2 Qn L L L H H L Open Open L VEE VEE L L VBB L H VBB H VBB L H VBB H L H = HIGH Voltage Level L = LOW Voltage Level 24-Pin Quad Cerpak Outputs Dn Absolute Maximum Ratings (Note 1) Voltage Applied to Output in HIGH State (with VCC = 0V) Current Applied to Output in LOW State (Max) ESD (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired. Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin Input Voltage (DC) −65˚C to +150˚C −0.5V to VCC twice the rated IOL (mA) ≥2000V Recommended Operating Conditions +175˚C −7.0V to +0.5V −0.5V to +6.0V VEE to +0.5V Case Temperature (TC) Military Supply Voltage (VEE) −55˚C to +125˚C −5.7V to −4.2V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol VBB Parameter Output Reference Voltage Min Max −1380 −1260 −1396 −1260 −1165 −870 Units TC 0˚C to +125˚C IVBB = −2.1 mA mV VIH Input HIGH Voltage −55˚C mV Conditions −55˚C to +125˚C Notes IVBB = −3 µA, VEE = −4.2V VEE = −5.7V Guaranteed HIGH Signal for All Inputs (with One Input Tied to VBB) VIL Input LOW Voltage −1830 −1475 mV −55˚C to +125˚C Guaranteed LOW Signal for All Inputs (with One Input Tied to VBB) VOH Output HIGH Voltage 2.5 mV 0˚C to +125˚C 2.4 VOL Output LOW Voltage VDIFF Input Voltage Differential 150 VCM Common Mode Voltage −2000 IIH Input HIGH Current IOS Input LOW Current 0.50 Output Short Circuit −150 −55˚C to +125˚C IOL = 20 mA mV −55˚C to +125˚C Required for Full Output Swing −500 mV −55˚C to +125˚C 350 µA 0˚C to +125˚C −60 −55˚C µA −55˚C to +125˚C mA −55˚C to +125˚C Current ICEX VIN = VIH VIN = VIH (Max), D0–D5 = VIL VIN = VIL D0–D5 = VBB , (Min) (Min), D0–D5 = VBB VOUT = GND ITTL VEE Power Supply Current VTTL Power Supply Current −35 (Notes 3, 4, 5) (Notes 3, 4, 5) (Notes 3, 4, 5) (Notes 3, 4, 5) (Notes 3, 4, 5) 250 µA −55˚C to +125˚C VOUT = 5.5V (Notes 3, 4, 5) −12 mA −55˚C to +125˚C D0–D5 = VBB (Notes 3, 4, 5) −55˚C to +125˚C D0–D5 = VBB (Notes 3, 4, 5) Leakage Current IEE (Notes 3, 4, 5, 6) (Notes 3, 4, 5, 6) Test One Output at a Time Output HIGH (Notes 3, 4, 5, 6) (Max) or VIL (Min) mV 500 IIL IOH = −2.0 mA −55˚C 0.5 (Notes 3, 4, 5) IVBB = −3 mA 65 mA Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, + 25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL. 3 www.national.com AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V Symbol Parameter tPLH Propagation Delay tPHL Data to Output TC = −55˚C TC = +25˚C TC = +125˚C Min Max Min Max Min Max 1.50 5.00 1.60 4.70 1.70 5.70 Units ns Conditions CL = 50 pF Figures 1, 3 Notes (Notes 7, 8, 9) Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at +25˚C, temperature only, Subgroup A9. Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Switching Waveform DS100314-6 FIGURE 1. Propagation Delay www.national.com 4 Test Circuits DS100314-5 Notes: VCC = 0V, VEE = −4.5V, VTTL = +5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC, VEE and VTTL All unused outputs are loaded with 500Ω to GND CL = Fixture and stray capacitance = 15 pF FIGURE 2. AC Test Circuit for 15 pF Loading 5 www.national.com Test Circuits (Continued) DS100314-8 Notes: VCC = 0V, VEE = −4.5V, VTTL = +5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC, VEE and VTTL All unused outputs are loaded with 500Ω to GND CL = Fixture and stray capacitance = 50 pF FIGURE 3. AC Test Circuit for 50 pF Loading www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 24 Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24 Lead Quad Cerpak (F) NS Package Number W24B 7 www.national.com 100325 Low Power Hex ECL-to-TTL Translator LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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